Move the cache profile counter type definitions to hal/cache_types.h so
that
esp_cache_cnt.h can use them without depending on the public soc header
soc/cache_periph.h (which CI rejects as non-public).
The remaining cache_periph.h header and its per-target cache_periph.c
sources
are moved from the soc component into the hal component, with the
sources
organized per target directory as usual for the hal component.
Removes the soc/cache_periph.h dependency from esp_cache_cnt.h and
hal/cache_ll.h by using hal/cache_periph.h instead.
Move the PMU internal voltage calibration related efuse read LL
functions
from efuse_ll.h into pmu_ll.h, renaming them with the pmu_ll prefix.
efuse_ll.h should only contain efuse controller or system-global
functions;
other modules' private efuse bits belong to their own LL layer.
Affected chips: esp32c5, esp32c6, esp32c61, esp32h2, esp32h4, esp32p4.
Moved functions (renamed efuse_ll_get_* -> pmu_ll_get_*):
- get_active_hp_dbias, get_active_lp_dbias
- get_dbias_vol_gap
- get_lslp_dbg, get_dslp_dbg (where present)
- get_lslp_hp_dbias, get_dslp_lp_dbias (where present)
- get_dslp_dbias (esp32h2)
Keep gated-clk refcnt under s_clk_tree_spinlock only, and call
esp_crypto_common_clk_enable outside PERIPH_RCC so crypto (RCC→clk_tree)
and modem (clk_tree→RCC) cannot deadlock on periph_spinlock
Co-authored-by: Cursor <cursoragent@cursor.com>
On ESP32-S3, USB PHY is clocked from BBPLL,
however if the BBPLL is not used as CPU clock source,
the power management unit can turn it off.
This commit registers USB as BBPLL consumer so it is not turned off.
Closes https://github.com/espressif/esp-idf/issues/15451
ESP32-S2 disables the brownout detector before deep sleep; if sleep is
rejected, re-init it so BOD is not left disabled (PM-519).
Co-authored-by: Cursor <cursoragent@cursor.com>
change(esp_tee): Force non-deterministic ECDSA signing for TEE secure storage keys
Closes IDF-15937 and IDF-15939
See merge request espressif/esp-idf!50355
The bootloader programs only unlocked PMA entries (no PMP), so the layout is
not a bootloader<->application ABI; the application resets all entries, programs
them in ascending order from IRAM, and locks everything. Verified on ESP32-H4 v0.1.
Every other SOC_*_HIGH macro in soc.h is an exclusive region end;
SOC_RAM_ICACHE1_HIGH was the inclusive last byte (0x40867fff). This
also made the reclaimed ICache1 heap region in single core mode
(components/heap/port/esp32h4/memory_layout.c, sized as HIGH - LOW)
one byte short. Change the value to the exclusive end 0x40868000 and
drop the +1 compensation at the SOC_HP_RAM_HIGH definition.
