fix(soc): make SOC_RAM_ICACHE1_HIGH an exclusive bound on ESP32-H4

Every other SOC_*_HIGH macro in soc.h is an exclusive region end;
SOC_RAM_ICACHE1_HIGH was the inclusive last byte (0x40867fff). This
also made the reclaimed ICache1 heap region in single core mode
(components/heap/port/esp32h4/memory_layout.c, sized as HIGH - LOW)
one byte short. Change the value to the exclusive end 0x40868000 and
drop the +1 compensation at the SOC_HP_RAM_HIGH definition.

components/esp_hw_support/port/esp32h4/cpu_region_protect.c

@@ -45,7 +45,7 @@
  * outside the valid RAM window.
  */
 #if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
-#define SOC_HP_RAM_HIGH   (SOC_RAM_ICACHE1_HIGH + 1)
+#define SOC_HP_RAM_HIGH   SOC_RAM_ICACHE1_HIGH
 _Static_assert(SOC_IRAM_HIGH == SOC_RAM_ICACHE1_LOW, "ICache1 RAM must be contiguous with D/IRAM");
 #else
 #define SOC_HP_RAM_HIGH   SOC_IRAM_HIGH

components/soc/esp32h4/include/soc/soc.h

@@ -196,7 +196,7 @@
 
 //ICache1 region
 #define SOC_RAM_ICACHE1_LOW    0x40860000
-#define SOC_RAM_ICACHE1_HIGH   0x40867fff
+#define SOC_RAM_ICACHE1_HIGH   0x40868000
 
 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
 //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.