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Merge branch 'fix/fix_cryto_module_locked_after_pd_top_lslp' into 'master'

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fix(esp_hw_support): fix cryto module locked after pd_top lightsleep

Closes WIFIBUG-2126 and PM-861

See merge request espressif/esp-idf!52460
This commit is contained in:
Jiang Jiang Jian
2026-09-09 13:59:46 +08:00
parent 752db18455 4bcc24ca6b
commit 716e9e5121
13 changed files with 357 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c
+8 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,6 +7,7 @@
#include "esp_private/sleep_clock.h"
#include "soc/pcr_reg.h"
#include "soc/pmu_reg.h"
#include "soc/ds_reg.h"
#include "modem/i2c_ana_mst_reg.h"
#include "modem/modem_lpcon_reg.h"
#include "modem/modem_syscon_reg.h"
@@ -15,7 +16,7 @@ ESP_LOG_ATTR_TAG(TAG, "sleep_clock");
esp_err_t sleep_clock_system_retention_init(void *arg)
{
#define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
#define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
const static sleep_retention_entries_config_t pcr_regs_retention[] = {
/* Enable i2c master clock */
@@ -29,8 +30,12 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
/* Clock configuration retention */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR() - 1, 0, 0,
0xffffffff, 0xfeffffff, 0x7fff, 0x0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
/* TOP PD wake: DS CLK_EN defaults to 1 and starts mem clean; wait idle before restoring DS clock */
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[9] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(9), PCR_DS_CONF_REG, PCR_DS_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c
+6 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include "soc/lp_analog_peri_reg.h"
#include "soc/pcr_reg.h"
#include "soc/pmu_reg.h"
#include "soc/ecdsa_reg.h"
#include "modem/i2c_ana_mst_reg.h"
#include "modem/modem_lpcon_reg.h"
#include "modem/modem_syscon_reg.h"
@@ -34,7 +35,10 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
[9] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(9), LP_ANA_POWER_GLITCH_CNTL_REG, 0, LP_ANA_POWER_GLITCH_RESET_ENA_M,0, 1), .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */
[10] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF, LP_ANA_POWER_GLITCH_RESET_ENA_M,1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
[11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
[11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 62, 0, 0, 0xfd73ffff, 0xfdff7fff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
/* TOP PD wake: ECDSA CLK_EN defaults to 1 and starts mem clean; wait idle before restoring ECDSA clock */
[12] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_PCR_LINK(12), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
[13] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(13), PCR_ECDSA_CONF_REG, PCR_ECDSA_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1) },
#endif
};
components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c
+13 -5
View File
@@ -1,11 +1,13 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_private/sleep_clock.h"
#include "soc/pcr_reg.h"
#include "soc/ds_reg.h"
#include "soc/ecdsa_reg.h"
#include "modem/i2c_ana_mst_reg.h"
#include "modem/modem_syscon_reg.h"
#include "modem/modem_lpcon_reg.h"
@@ -29,10 +31,16 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
/* Clock configuration retention */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR() - 2, 0, 0,
0xffffffff, 0xfd7fffff, 0x1fffff, 0x0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[11] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(11), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[12] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(12), PCR_DS_CONF_REG, PCR_DS_CONF_REG, 2, 0, 0,
0x5, 0x0, 0x0, 0x0), .owner = ENTRY(0) | ENTRY(2) },
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c
+11 -3
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@@ -6,6 +6,8 @@
#include "esp_private/sleep_clock.h"
#include "soc/pcr_reg.h"
#include "soc/ds_reg.h"
#include "soc/ecdsa_reg.h"
#include "modem/i2c_ana_mst_reg.h"
#include "modem/modem_syscon_reg.h"
#include "modem/modem_lpcon_reg.h"
@@ -29,9 +31,15 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
/* Clock configuration retention */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR() - 2, 0, 0,
0xffffffff, 0xfd7fffff, 0x1fffff, 0x0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), PCR_DS_CONF_REG, PCR_DS_CONF_REG, 2, 0, 0,
0x5, 0x0, 0x0, 0x0), .owner = ENTRY(0) | ENTRY(2) },
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32h21/sleep_clock_icg.c
-4
View File
@@ -96,10 +96,6 @@ void sleep_clock_icg_retention_clock_config(sleep_retention_module_bitmap_t *mod
}
}
#if !CONFIG_SECURE_ENABLE_TEE
clocks_mask &= ~PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_SEC);
#endif
esp_sleep_enter_critical_safe();
s_retention_icg_flags = clocks_mask;
esp_sleep_exit_critical_safe();
components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c
+9 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,8 @@
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/pmu_reg.h"
#include "soc/lpperi_reg.h"
#include "soc/ds_reg.h"
#include "soc/ecdsa_reg.h"
#include "pmu_bit_defs.h"
ESP_LOG_ATTR_TAG(TAG, "sleep_clock");
@@ -26,11 +28,16 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
/* Stop SYSPLL self-calibration */
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP, HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) },
/* Clock configuration retention */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) }, /* pcr */
[4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR() - 1, 0, 0,
0xffffffff, 0x0ffffbff, 0x0, 0x0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_M, 1, 0), .owner = ENTRY(0) },
[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_M, 1, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), HP_SYS_CLKRST_PERI_CLK_CTRL02_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), HP_SYS_CLKRST_PERI_CLK_CTRL02_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) },
/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) },
[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) },
[11] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(11), HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, 1, 0, 0), .owner = ENTRY(0) },
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c
+8 -1
View File
@@ -8,6 +8,8 @@
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/pmu_reg.h"
#include "soc/lp_peri_clkrst_reg.h"
#include "soc/ds_reg.h"
#include "soc/ecdsa_reg.h"
#include "pmu_bit_defs.h"
#include "modem/modem_syscon_reg.h"
#include "modem/modem_lpcon_reg.h"
@@ -28,11 +30,16 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
/* Stop SYSPLL self-calibration */
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
/* Clock configuration retention */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(1)}, /* pcr */
[4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR() - 1, 0, 0,
0xffbfffff, 0xffffffff, 0xffffffff, 0x7fffffff), .owner = ENTRY(0) | ENTRY(1)},
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[11] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(11), HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_CRYPTO_CTRL0_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1)},
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32s31/sleep_clock_icg.c
-3
View File
@@ -126,9 +126,6 @@ void sleep_clock_icg_retention_clock_config(sleep_retention_module_bitmap_t *mod
#if !CONFIG_SPIRAM
clocks_mask &= ~PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_MSPI_PSRAM);
#endif
#if !CONFIG_SECURE_ENABLE_TEE
clocks_mask &= ~PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_SEC);
#endif
esp_sleep_enter_critical_safe();
s_retention_icg_flags[0] = PMU_SLEEP_CLK_ICG_FUNC_LO(clocks_mask);
components/mbedtls/test_apps/.build-test-rules.yml
+1
View File
@@ -10,6 +10,7 @@ components/mbedtls/test_apps/mbedtls_ut:
- if: CONFIG_NAME == "psram_all_ext_flash_enc_f4r8" and IDF_TARGET != "esp32s3"
- if: CONFIG_NAME == "ecdsa_sign" and SOC_ECDSA_SUPPORTED != 1
- if: CONFIG_NAME == "hmac_opaque" and SOC_HMAC_SUPPORTED != 1
- if: CONFIG_NAME == "pd_top" and (SOC_PM_SUPPORT_TOP_PD != 1 or SOC_PAU_SUPPORTED != 1)
disable_test:
- if: CONFIG_NAME == "psram_all_ext_flash_enc" and IDF_TARGET not in ["esp32", "esp32p4", "esp32c5"]
reason: lack of runners
components/mbedtls/test_apps/mbedtls_ut/main/CMakeLists.txt
+2 -1
View File
@@ -12,7 +12,8 @@ set(TEST_CRTS "crts/server_cert_chain.pem"
idf_component_register(
SRC_DIRS "."
PRIV_INCLUDE_DIRS "." "../include"
PRIV_REQUIRES efuse cmock test_utils mbedtls esp_timer unity spi_flash esp_psram esp_security
PRIV_REQUIRES efuse cmock test_utils mbedtls esp_timer unity
spi_flash esp_psram esp_security esp_hw_support
EMBED_TXTFILES ${TEST_CRTS}
WHOLE_ARCHIVE)
components/mbedtls/test_apps/mbedtls_ut/main/test_crypto_pd_top_lightsleep.c
+260
View File
@@ -0,0 +1,260 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*
* Smoke-test crypto accelerators after TOP power-domain light sleep.
* DS / hardware HMAC need efuse keys and are not covered here.
*/
#include "sdkconfig.h"
#include "unity.h"
#include "test_utils.h"
#include "soc/soc_caps.h"
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_LIGHT_SLEEP_SUPPORTED && SOC_PM_SUPPORT_TOP_PD
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include "esp_log.h"
#include "esp_sleep.h"
#include "esp_private/esp_sleep_internal.h"
#include "esp_private/sleep_cpu.h"
#include "esp_private/esp_pmu.h"
#define MBEDTLS_DECLARE_PRIVATE_IDENTIFIERS
#include "mbedtls/bignum.h"
#include "mbedtls/private/ecp.h"
#include "mbedtls/psa_util.h"
#include "psa/crypto.h"
#if CONFIG_MBEDTLS_HARDWARE_SHA
#include "sha/sha_parallel_engine.h"
#endif
#if CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY && SOC_ECDSA_SUPPORTED
#include "hal/ecdsa_ll.h"
#endif
static const char *TAG = "crypto_pd_top";
static void enter_pd_top_lightsleep(void)
{
esp_sleep_context_t sleep_ctx;
TEST_ESP_OK(sleep_cpu_configure(true));
esp_sleep_set_sleep_context(&sleep_ctx);
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(10 * 1000));
fflush(stdout);
fsync(fileno(stdout));
TEST_ESP_OK(esp_light_sleep_start());
TEST_ASSERT_EQUAL(PMU_SLEEP_PD_TOP, sleep_ctx.sleep_flags & PMU_SLEEP_PD_TOP);
TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
esp_sleep_set_sleep_context(NULL);
TEST_ESP_OK(sleep_cpu_configure(false));
}
#if CONFIG_MBEDTLS_HARDWARE_AES
static void verify_aes_ecb(void)
{
/* NIST AES-128-ECB sample */
const uint8_t key[16] = {
0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6,
0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c,
};
const uint8_t plaintext[16] = {
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
};
const uint8_t expected[16] = {
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
};
uint8_t ciphertext[16] = {0};
size_t out_len = 0;
psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT;
psa_key_id_t key_id;
psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_ENCRYPT);
psa_set_key_algorithm(&attributes, PSA_ALG_ECB_NO_PADDING);
psa_set_key_type(&attributes, PSA_KEY_TYPE_AES);
psa_set_key_bits(&attributes, 128);
TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_import_key(&attributes, key, sizeof(key), &key_id));
TEST_ASSERT_EQUAL(PSA_SUCCESS,
psa_cipher_encrypt(key_id, PSA_ALG_ECB_NO_PADDING,
plaintext, sizeof(plaintext),
ciphertext, sizeof(ciphertext), &out_len));
TEST_ASSERT_EQUAL(sizeof(expected), out_len);
TEST_ASSERT_EQUAL_HEX8_ARRAY(expected, ciphertext, sizeof(expected));
psa_destroy_key(key_id);
psa_reset_key_attributes(&attributes);
}
#endif
#if CONFIG_MBEDTLS_HARDWARE_SHA
static void verify_sha1(void)
{
const uint8_t input[] = "abc";
const uint8_t expected[20] = {
0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a, 0xba, 0x3e,
0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c, 0x9c, 0xd0, 0xd8, 0x9d,
};
uint8_t digest[20] = {0};
esp_sha(SHA1, input, sizeof(input) - 1, digest);
TEST_ASSERT_EQUAL_HEX8_ARRAY(expected, digest, sizeof(expected));
}
#endif
#if CONFIG_MBEDTLS_HARDWARE_MPI
static void verify_mpi_mod_mul(void)
{
mbedtls_mpi A, B, M, Z;
mbedtls_mpi_init(&A);
mbedtls_mpi_init(&B);
mbedtls_mpi_init(&M);
mbedtls_mpi_init(&Z);
TEST_ASSERT_EQUAL(0, mbedtls_mpi_lset(&A, 2));
TEST_ASSERT_EQUAL(0, mbedtls_mpi_lset(&B, 3));
/* M = 0xFFFFFFFF (32-bit all-ones) so 2*3 mod M == 6 */
for (int i = 0; i < 32; i++) {
TEST_ASSERT_EQUAL(0, mbedtls_mpi_set_bit(&M, i, 1));
}
TEST_ASSERT_EQUAL(0, esp_mpi_mul_mpi_mod(&Z, &A, &B, &M));
TEST_ASSERT_EQUAL(0, mbedtls_mpi_cmp_int(&Z, 6));
mbedtls_mpi_free(&A);
mbedtls_mpi_free(&B);
mbedtls_mpi_free(&M);
mbedtls_mpi_free(&Z);
}
#endif
#if CONFIG_MBEDTLS_HARDWARE_ECC
static void verify_ecc_mul(void)
{
/* Same flow as test_ecp.c: 127 * G */
const uint8_t exp_x[32] = {
0x53, 0x4D, 0x45, 0xDB, 0x6B, 0xAC, 0xA8, 0xE2,
0xD2, 0xA5, 0xD0, 0xA7, 0x65, 0xF1, 0x60, 0x13,
0xA8, 0xD4, 0xEB, 0x58, 0xC6, 0xAA, 0xAD, 0x35,
0x67, 0xCE, 0xBD, 0xFA, 0xC4, 0x2D, 0x62, 0x3C,
};
const uint8_t exp_y[32] = {
0xFA, 0xD6, 0x69, 0xC8, 0x9A, 0x2A, 0x54, 0xE4,
0x41, 0x54, 0x35, 0x7F, 0x99, 0x2C, 0xCE, 0xC8,
0xEE, 0xF0, 0x93, 0xE0, 0xF2, 0x3A, 0x63, 0x1D,
0x17, 0xFD, 0xF6, 0x64, 0x41, 0x9E, 0x50, 0x0C,
};
mbedtls_ecp_group grp;
mbedtls_ecp_point R;
mbedtls_mpi m;
uint8_t x[32] = {0};
uint8_t y[32] = {0};
mbedtls_ecp_group_init(&grp);
mbedtls_ecp_point_init(&R);
mbedtls_mpi_init(&m);
TEST_ASSERT_EQUAL(0, mbedtls_ecp_group_load(&grp, MBEDTLS_ECP_DP_SECP256R1));
TEST_ASSERT_EQUAL(0, mbedtls_mpi_lset(&m, 127));
TEST_ASSERT_EQUAL(0, mbedtls_ecp_mul(&grp, &R, &m, &grp.G,
mbedtls_psa_get_random, MBEDTLS_PSA_RANDOM_STATE));
TEST_ASSERT_EQUAL(0, mbedtls_mpi_write_binary(&R.MBEDTLS_PRIVATE(X), x, sizeof(x)));
TEST_ASSERT_EQUAL(0, mbedtls_mpi_write_binary(&R.MBEDTLS_PRIVATE(Y), y, sizeof(y)));
TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_x, x, sizeof(exp_x));
TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_y, y, sizeof(exp_y));
mbedtls_ecp_point_free(&R);
mbedtls_mpi_free(&m);
mbedtls_ecp_group_free(&grp);
}
#endif
#if CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY && SOC_ECDSA_SUPPORTED
static void verify_ecdsa(void)
{
if (!ecdsa_ll_is_supported()) {
TEST_IGNORE_MESSAGE("ECDSA is not supported");
}
/* Known SECP256R1 verify vector (same as test_psa_ecdsa.c) */
const uint8_t hash[32] = {
0x98, 0xca, 0xea, 0x85, 0x7b, 0x03, 0x5e, 0xc0,
0xe3, 0xc3, 0x39, 0x29, 0xef, 0xf1, 0xf1, 0x25,
0x00, 0x19, 0xe7, 0x11, 0xc3, 0x3d, 0x84, 0x42,
0x38, 0x79, 0x10, 0xef, 0xb2, 0x9b, 0xd2, 0x63,
};
const uint8_t r[32] = {
0xbf, 0x58, 0x35, 0xf2, 0xf4, 0x4d, 0x49, 0x0e,
0xeb, 0x98, 0x66, 0x7e, 0x0c, 0x25, 0xd1, 0x1b,
0x6a, 0xd0, 0x15, 0xc4, 0x68, 0x8b, 0x9f, 0x83,
0x2f, 0xa1, 0x9e, 0xf2, 0x2f, 0x33, 0xc2, 0xf7,
};
const uint8_t s[32] = {
0x25, 0x63, 0xb1, 0x5f, 0xaa, 0xe4, 0xcf, 0xc1,
0xd0, 0xfe, 0x43, 0xdf, 0xbb, 0x5f, 0xe7, 0x29,
0xdf, 0xb4, 0xf9, 0xfa, 0xe4, 0xb1, 0xc1, 0x7a,
0x7e, 0x0d, 0x73, 0xe2, 0x4b, 0x91, 0x7c, 0x79,
};
const uint8_t pub_x[32] = {
0xa2, 0x8f, 0x52, 0x60, 0x20, 0x9b, 0x54, 0x3c,
0x13, 0x2f, 0x51, 0xb1, 0x89, 0xbf, 0xc7, 0xfa,
0x84, 0x5c, 0x56, 0x96, 0x2a, 0x00, 0x67, 0xdd,
0x7c, 0x8c, 0x0f, 0x63, 0x8b, 0x76, 0x7f, 0xb9,
};
const uint8_t pub_y[32] = {
0xf6, 0x4c, 0x87, 0x5b, 0x5a, 0x9b, 0x59, 0x0a,
0xc4, 0x53, 0x04, 0x72, 0x0d, 0x7c, 0xde, 0xac,
0x7e, 0xad, 0x49, 0x8c, 0xf7, 0x5c, 0xc3, 0x1c,
0x1e, 0x81, 0xf2, 0x47, 0x01, 0x74, 0x05, 0xd5,
};
uint8_t pub[65] = {0x04};
uint8_t signature[64];
psa_key_id_t key_id;
psa_key_attributes_t key_attr = PSA_KEY_ATTRIBUTES_INIT;
memcpy(pub + 1, pub_x, sizeof(pub_x));
memcpy(pub + 1 + sizeof(pub_x), pub_y, sizeof(pub_y));
memcpy(signature, r, sizeof(r));
memcpy(signature + sizeof(r), s, sizeof(s));
psa_set_key_type(&key_attr, PSA_KEY_TYPE_ECC_PUBLIC_KEY(PSA_ECC_FAMILY_SECP_R1));
psa_set_key_usage_flags(&key_attr, PSA_KEY_USAGE_VERIFY_HASH);
psa_set_key_algorithm(&key_attr, PSA_ALG_ECDSA(PSA_ALG_SHA_256));
psa_set_key_bits(&key_attr, 256);
TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_import_key(&key_attr, pub, sizeof(pub), &key_id));
TEST_ASSERT_EQUAL(PSA_SUCCESS,
psa_verify_hash(key_id, PSA_ALG_ECDSA(PSA_ALG_SHA_256),
hash, sizeof(hash), signature, sizeof(signature)));
psa_destroy_key(key_id);
psa_reset_key_attributes(&key_attr);
}
#endif
TEST_CASE("Crypto peripherals work after PD_TOP lightsleep", "[hw_crypto][pd_top]")
{
TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_crypto_init());
for (int i = 0; i < 5; ++i) {
#if CONFIG_MBEDTLS_HARDWARE_AES
verify_aes_ecb();
#endif
#if CONFIG_MBEDTLS_HARDWARE_SHA
verify_sha1();
#endif
#if CONFIG_MBEDTLS_HARDWARE_MPI
verify_mpi_mod_mul();
#endif
#if CONFIG_MBEDTLS_HARDWARE_ECC
verify_ecc_mul();
#endif
#if CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY && SOC_ECDSA_SUPPORTED
verify_ecdsa();
#endif
enter_pd_top_lightsleep();
ESP_LOGI(TAG, "loop %d/5: woke from PD_TOP lightsleep", i + 1);
}
}
#endif /* CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_LIGHT_SLEEP_SUPPORTED && SOC_PM_SUPPORT_TOP_PD */
components/mbedtls/test_apps/mbedtls_ut/pytest_mbedtls_ut.py
+36
View File
@@ -198,3 +198,39 @@ def test_mbedtls_cross_signed(dut: Dut) -> None:
'certificate bundle - expired cert rejected with time-date check',
]
)
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
'pd_top',
],
indirect=True,
)
@idf_parametrize(
'target',
list(
filter(
lambda t: t != 'esp32c5',
soc_filtered_targets('SOC_PM_SUPPORT_TOP_PD == 1 and SOC_PAU_SUPPORTED == 1'),
)
),
indirect=['target'],
)
def test_mbedtls_crypto_pd_top_lightsleep(dut: Dut) -> None:
dut.run_all_single_board_cases(group='pd_top')
@pytest.mark.generic
@pytest.mark.esp32c5_rev1
@pytest.mark.parametrize(
'config',
[
'pd_top',
],
indirect=True,
)
@idf_parametrize('target', ['esp32c5'], indirect=['target'])
def test_mbedtls_crypto_pd_top_lightsleep_esp32c5_eco3(dut: Dut) -> None:
dut.run_all_single_board_cases(group='pd_top')
components/mbedtls/test_apps/mbedtls_ut/sdkconfig.ci.pd_top
+3
View File
@@ -0,0 +1,3 @@
CONFIG_PM_ENABLE=y
CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
CONFIG_ESP_SLEEP_DEBUG=y