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fix(esp_hw_support): wait DS/ECDSA idle before restore its PCR on wakeup

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This commit is contained in:
wuzhenghui
2026-09-07 15:08:56 +08:00
parent 781ecb1a72
commit 061881f90c
6 changed files with 55 additions and 16 deletions
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components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c
+8 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,6 +7,7 @@
#include "esp_private/sleep_clock.h"
#include "soc/pcr_reg.h"
#include "soc/pmu_reg.h"
#include "soc/ds_reg.h"
#include "modem/i2c_ana_mst_reg.h"
#include "modem/modem_lpcon_reg.h"
#include "modem/modem_syscon_reg.h"
@@ -15,7 +16,7 @@ ESP_LOG_ATTR_TAG(TAG, "sleep_clock");
esp_err_t sleep_clock_system_retention_init(void *arg)
{
#define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
#define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
const static sleep_retention_entries_config_t pcr_regs_retention[] = {
/* Enable i2c master clock */
@@ -29,8 +30,12 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
/* Clock configuration retention */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR() - 1, 0, 0,
0xffffffff, 0xfeffffff, 0x7fff, 0x0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
/* TOP PD wake: DS CLK_EN defaults to 1 and starts mem clean; wait idle before restoring DS clock */
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[9] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(9), PCR_DS_CONF_REG, PCR_DS_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c
+6 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include "soc/lp_analog_peri_reg.h"
#include "soc/pcr_reg.h"
#include "soc/pmu_reg.h"
#include "soc/ecdsa_reg.h"
#include "modem/i2c_ana_mst_reg.h"
#include "modem/modem_lpcon_reg.h"
#include "modem/modem_syscon_reg.h"
@@ -34,7 +35,10 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
[9] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(9), LP_ANA_POWER_GLITCH_CNTL_REG, 0, LP_ANA_POWER_GLITCH_RESET_ENA_M,0, 1), .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */
[10] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF, LP_ANA_POWER_GLITCH_RESET_ENA_M,1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
[11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
[11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 62, 0, 0, 0xfd73ffff, 0xfdff7fff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
/* TOP PD wake: ECDSA CLK_EN defaults to 1 and starts mem clean; wait idle before restoring ECDSA clock */
[12] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_PCR_LINK(12), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
[13] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(13), PCR_ECDSA_CONF_REG, PCR_ECDSA_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1) },
#endif
};
components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c
+13 -5
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@@ -1,11 +1,13 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_private/sleep_clock.h"
#include "soc/pcr_reg.h"
#include "soc/ds_reg.h"
#include "soc/ecdsa_reg.h"
#include "modem/i2c_ana_mst_reg.h"
#include "modem/modem_syscon_reg.h"
#include "modem/modem_lpcon_reg.h"
@@ -29,10 +31,16 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
/* Clock configuration retention */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR() - 2, 0, 0,
0xffffffff, 0xfd7fffff, 0x1fffff, 0x0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[11] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(11), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[12] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(12), PCR_DS_CONF_REG, PCR_DS_CONF_REG, 2, 0, 0,
0x5, 0x0, 0x0, 0x0), .owner = ENTRY(0) | ENTRY(2) },
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c
+11 -3
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@@ -6,6 +6,8 @@
#include "esp_private/sleep_clock.h"
#include "soc/pcr_reg.h"
#include "soc/ds_reg.h"
#include "soc/ecdsa_reg.h"
#include "modem/i2c_ana_mst_reg.h"
#include "modem/modem_syscon_reg.h"
#include "modem/modem_lpcon_reg.h"
@@ -29,9 +31,15 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
/* Clock configuration retention */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR() - 2, 0, 0,
0xffffffff, 0xfd7fffff, 0x1fffff, 0x0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), PCR_DS_CONF_REG, PCR_DS_CONF_REG, 2, 0, 0,
0x5, 0x0, 0x0, 0x0), .owner = ENTRY(0) | ENTRY(2) },
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c
+9 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,8 @@
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/pmu_reg.h"
#include "soc/lpperi_reg.h"
#include "soc/ds_reg.h"
#include "soc/ecdsa_reg.h"
#include "pmu_bit_defs.h"
ESP_LOG_ATTR_TAG(TAG, "sleep_clock");
@@ -26,11 +28,16 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
/* Stop SYSPLL self-calibration */
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP, HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) },
/* Clock configuration retention */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) }, /* pcr */
[4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR() - 1, 0, 0,
0xffffffff, 0x0ffffbff, 0x0, 0x0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_M, 1, 0), .owner = ENTRY(0) },
[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_M, 1, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), HP_SYS_CLKRST_PERI_CLK_CTRL02_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), HP_SYS_CLKRST_PERI_CLK_CTRL02_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) },
/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) },
[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) },
[11] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(11), HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, 1, 0, 0), .owner = ENTRY(0) },
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c
+8 -1
View File
@@ -8,6 +8,8 @@
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/pmu_reg.h"
#include "soc/lp_peri_clkrst_reg.h"
#include "soc/ds_reg.h"
#include "soc/ecdsa_reg.h"
#include "pmu_bit_defs.h"
#include "modem/modem_syscon_reg.h"
#include "modem/modem_lpcon_reg.h"
@@ -28,11 +30,16 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
/* Stop SYSPLL self-calibration */
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
/* Clock configuration retention */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(1)}, /* pcr */
[4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR() - 1, 0, 0,
0xffbfffff, 0xffffffff, 0xffffffff, 0x7fffffff), .owner = ENTRY(0) | ENTRY(1)},
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
[11] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(11), HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_CRYPTO_CTRL0_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1)},
};
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);