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Merge branch 'refactor/flash_refactor' into 'master'

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spi_flash: split driver and os driver into `spi_flash` and `esp_mspi` components

Closes IDF-15210

See merge request espressif/esp-idf!45409
This commit is contained in:
Armando (Dou Yiwen)
2026-09-10 07:29:01 +00:00
parent a07ebb7ad8 99b6f5dcd8
commit 496c0b6377
266 changed files with 1558 additions and 1208 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.gitlab/CODEOWNERS
+1
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@@ -114,6 +114,7 @@
/components/esp_libc/ @esp-idf-codeowners/system @esp-idf-codeowners/toolchain
/components/esp_local_ctrl/ @esp-idf-codeowners/app-utilities
/components/esp_mm/ @esp-idf-codeowners/peripherals
/components/esp_mspi/ @esp-idf-codeowners/peripherals
/components/esp_netif/ @esp-idf-codeowners/network
/components/esp_netif_stack/ @esp-idf-codeowners/network
/components/esp_partition/ @esp-idf-codeowners/storage
components/README.md
+9 -5
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@@ -10,7 +10,7 @@ The core components are organized into two groups.
The first group (referred to as `G0`) includes `hal`, `arch` (where `arch` is either `riscv` or `xtensa` depending on the chip), `esp_rom`, `esp_common`, and `soc`. This group contains information about and provides low-level access to the underlying hardware. In the case of `esp_common`, it contains hardware-agnostic code and utilities. These components may have dependencies on each other within the group, but outside dependencies should be minimized. The reason for this approach is that these components are fundamental, and many other components may require them. Ideally, the dependency relationship only goes one way, making it easier for this group to be usable in other projects.
The second group (referred to as `G1`) operates at a higher level than the first group. `G1` includes the components `esp_hw_support`, `esp_system`, `esp_libc`, `spi_flash`, `freertos`, `log`, and `heap`. Like the first group, circular dependencies within this group are allowed, and these components can have dependencies on the first group. G1 components represent essential software mechanisms for building other components.
The second group (referred to as `G1`) operates at a higher level than the first group. `G1` includes the components `esp_hw_support`, `esp_mspi`, `esp_system`, `esp_libc`, `freertos`, `log`, and `heap`. Like the first group, circular dependencies within this group are allowed, and these components can have dependencies on the first group. G1 components represent essential software mechanisms for building other components.
## Descriptions
@@ -69,10 +69,6 @@ Example:
### `G1` Components
#### `spi_flash`
SPI flash device access implementation.
#### `freertos`
FreeRTOS port to targets supported by ESP-IDF.
@@ -131,6 +127,14 @@ merely as facilitator to hardware access. Currently, this encompasses the follow
- CPU utilities
- MAC settings
#### `esp_mspi`
Contains the CPU XiP related MSPI (Memory SPI) implementation for the external SPI flash and PSRAM controller. Currently, this encompasses the following, but not limited to:
- MSPI timing tuning
- MSPI interrupt handling
- XiP on OPI/Octal flash support
### `esp_hw_support` vs `esp_system`
This section details list some implementations and the reason for placing it in either `esp_hw_support` or `esp_system`.
components/app_update/test_apps/test_app_update/main/test_switch_ota.c
+1 -1
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@@ -9,7 +9,7 @@
#include "esp_system.h"
#include "bootloader_common.h"
#include "../bootloader_flash/include/bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_log.h"
#include "esp_ota_ops.h"
#include "unity.h"
components/app_update/test_apps/test_app_update/main/utils_update.c
+1 -1
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@@ -10,7 +10,7 @@
#include "esp_partition.h"
#include "esp_flash_partitions.h"
#include "esp_image_format.h"
#include "../bootloader_flash/include/bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_sleep.h"
#include "esp_ota_ops.h"
#include "esp_err.h"
components/bootloader_support/CMakeLists.txt
+2 -2
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@@ -100,8 +100,8 @@ else()
set(priv_requires spi_flash efuse heap esp_bootloader_format esp_app_format
esptool_py)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer
esp_hal_clock esp_hal_security esp_hal_debug_assist)
list(APPEND priv_requires esp_mspi esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv
esp_hal_rtc_timer esp_hal_clock esp_hal_security esp_hal_debug_assist)
endif()
# src/flash_encrypt.c includes esp_security/esp_key_mgr.h on
components/bootloader_support/bootloader_flash/include/bootloader_flash.h
+3 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,8 +7,7 @@
#include <stdint.h>
#include <esp_err.h>
#include "spi_flash_mmap.h" /* including in bootloader for error values */
#include "esp_private/spi_flash_os.h"
#include "esp_rom_spiflash.h"
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "bootloader_flash_override.h"
@@ -59,6 +58,7 @@ esp_err_t bootloader_flash_reset_chip(void);
*
* @return True if flash is in octal mode, false else
*/
__attribute__((deprecated("in favor of spi_flash_is_octal_mode_enabled")))
bool bootloader_flash_is_octal_mode_enabled(void);
/**
components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h
+21 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,6 +16,26 @@ extern "C" {
typedef unsigned (*bootloader_flash_read_status_fn_t)(void);
typedef void (*bootloader_flash_write_status_fn_t)(unsigned);
/**
* @brief Execute a user command on the flash
*
* @param command The command value to execute.
* @param mosi_data MOSI data to send
* @param mosi_len Length of MOSI data, in bits
* @param miso_len Length of MISO data to receive, in bits
* @return Received MISO data
*/
uint32_t bootloader_execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len);
/**
* @brief Read the SFDP of the flash
*
* @param sfdp_addr Address of the parameter to read
* @param miso_byte_num Bytes to read
* @return The read SFDP, little endian, 4 bytes at most
*/
uint32_t bootloader_flash_read_sfdp(uint32_t sfdp_addr, unsigned int miso_byte_num);
typedef struct __attribute__((packed))
{
const char *manufacturer;
components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
+6 -173
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@@ -1,46 +1,22 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __BOOTLOADER_FLASH_H
#define __BOOTLOADER_FLASH_H
#pragma once
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include <esp_err.h>
#include <spi_flash_mmap.h> /* including in bootloader for error values */
#include "sdkconfig.h"
#include "bootloader_flash.h"
#include "soc/ext_mem_defs.h"
#include "bootloader_flash_override.h"
#ifdef __cplusplus
extern "C" {
#endif
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_BLOCK_SIZE 0x10000
#define MMAP_ALIGNED_MASK (SPI_FLASH_MMU_PAGE_SIZE - 1)
#define MMU_FLASH_MASK (~(SPI_FLASH_MMU_PAGE_SIZE - 1))
#define MMU_FLASH_MASK_FROM_VAL(PAGE_SZ) (~((PAGE_SZ) - 1))
#define MMU_DROM_END_ENTRY_VADDR_FROM_VAL(PAGE_SZ) (SOC_DRAM_FLASH_ADDRESS_HIGH - (PAGE_SZ))
/**
* MMU mapping must always be in the unit of a SPI_FLASH_MMU_PAGE_SIZE
* This macro is a helper for you to get needed page nums to be mapped. e.g.:
* Let's say SPI_FLASH_MMU_PAGE_SIZE is 64KB.
* - v_start = 0x4200_0004
* - size = 4 * 64KB
*
* You should map from 0x4200_0000, then map 5 pages.
/*
* SPI commands
* These are deprecated, use the ones in spi_flash_defs.h instead.
*/
#define GET_REQUIRED_MMU_PAGES(size, v_start) ((size + (v_start - (v_start & MMU_FLASH_MASK)) + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE)
/* SPI commands (actual on-wire commands not SPI controller bitmasks)
Suitable for use with the bootloader_execute_flash_command static function.
*/
#define CMD_RDID 0x9F
#define CMD_WRSR 0x01
#define CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
@@ -62,146 +38,3 @@ extern "C" {
#define CMD_FASTRD_DUAL_4B 0x3C
#define CMD_FASTRD_4B 0x0C
#define CMD_SLOWRD_4B 0x13
/* Provide a Flash API for bootloader_support code,
that can be used from bootloader or app code.
This header is available to source code in the bootloader &
bootloader_support components only.
*/
/**
* @brief Get number of free pages
*
* @return Number of free pages
*/
uint32_t bootloader_mmap_get_free_pages(void);
/**
* @brief Map a region of flash to data memory
*
* @important In bootloader code, only one region can be bootloader_mmaped at once. The previous region must be bootloader_munmapped before another region is mapped.
*
* @important In app code, these functions are not thread safe.
*
* Call bootloader_munmap once for each successful call to bootloader_mmap.
*
* In esp-idf app, this function maps directly to spi_flash_mmap with the @ref
* spi_flash_mmap_flag_t::SPI_FLASH_MMAP_FLAG_BLOCKS_WRITE flag set. When XIP on PSRAM (`CONFIG_SPIRAM_XIP_FROM_PSRAM`) enabled, flash erasing/writing
* will be blocked until unmap.
*
* @param offset - Starting flash offset to map to memory.
* @param length - Length of data to map.
*
* @return Pointer to mapped data memory (at src_addr), or NULL
* if an allocation error occurred.
*/
const void *bootloader_mmap(uint32_t src_addr, uint32_t size);
/**
* @brief Unmap a previously mapped region of flash
*
* Call bootloader_munmap once for each successful call to bootloader_mmap.
*/
void bootloader_munmap(const void *mapping);
/**
* @brief Read data from Flash.
*
*
* @note All of src, dest and size have to be 4-byte aligned.
*
* @param src source address of the data in Flash.
* @param dest pointer to the destination buffer
* @param size length of data
* @param allow_decrypt If true and flash encryption is enabled, data on flash
* will be decrypted transparently as part of the read.
*
* @return ESP_OK on success, ESP_ERR_FLASH_OP_FAIL on SPI failure,
* ESP_ERR_FLASH_OP_TIMEOUT on SPI timeout.
*/
esp_err_t bootloader_flash_read(size_t src_addr, void *dest, size_t size, bool allow_decrypt);
/**
* @brief Write data to Flash.
*
* @note All of dest_addr, src and size have to be 4-byte aligned. If write_encrypted is set, dest_addr and size must be 32-byte aligned.
*
* @note In bootloader, when write_encrypted == true, the src buffer is encrypted in place.
*
* @note [ESP-TEE] Using this API from the TEE will return an error if the dest_addr lies
* within the active TEE partition range.
*
* @param dest_addr Destination address to write in Flash.
* @param src Pointer to the data to write to flash
* @param size Length of data in bytes.
* @param write_encrypted If true, data will be written encrypted on flash.
*
* @return ESP_OK on success, ESP_ERR_FLASH_OP_FAIL on SPI failure,
* ESP_ERR_FLASH_OP_TIMEOUT on SPI timeout.
*/
esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool write_encrypted);
/**
* @brief Erase the Flash sector.
*
* @param sector Sector number, the count starts at sector 0, 4KB per sector.
*
* @return esp_err_t
*/
esp_err_t bootloader_flash_erase_sector(size_t sector);
/**
* @brief Erase the Flash range.
*
* @note [ESP-TEE] Using this API from the TEE will return an error if the start_addr lies
* within the active TEE partition range.
*
* @param start_addr start address of flash offset
* @param size sector aligned size to be erased
*
* @return esp_err_t
*/
esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size);
/**
* @brief Execute a user command on the flash
*
* @param command The command value to execute.
* @param mosi_data MOSI data to send
* @param mosi_len Length of MOSI data, in bits
* @param miso_len Length of MISO data to receive, in bits
* @return Received MISO data
*/
uint32_t bootloader_execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len);
/**
* @brief Read the SFDP of the flash
*
* @param sfdp_addr Address of the parameter to read
* @param miso_byte_num Bytes to read
* @return The read SFDP, little endian, 4 bytes at most
*/
uint32_t bootloader_flash_read_sfdp(uint32_t sfdp_addr, unsigned int miso_byte_num);
/**
* @brief Enable the flash write protect (WEL bit).
*/
void bootloader_enable_wp(void);
/**
* @brief Once this function is called,
* any on-going internal operations will be terminated and the device will return to its default power-on
* state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
* (WEL) status, Program/Erase Suspend status, etc.
*/
void bootloader_spi_flash_reset(void);
#ifdef __cplusplus
}
#endif
#endif
components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h
+147 -2
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@@ -1,17 +1,161 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <esp_err.h>
#include <stddef.h>
#include <stdbool.h>
#include "esp_err.h"
#include "sdkconfig.h"
#include "bootloader_flash.h"
#include "bootloader_flash_override.h"
#include "soc/soc_caps.h"
#include "soc/ext_mem_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
//-------------------------------- Utilities -------------------------------- //
/**
* This file provides a Flash API for bootloader_support code,
* that can be used from bootloader or app code.
* This header is available to source code in the ESP-IDF components only.
*/
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_BLOCK_SIZE 0x10000
#define MMAP_ALIGNED_MASK (CONFIG_MMU_PAGE_SIZE - 1)
#define MMU_FLASH_MASK (~(CONFIG_MMU_PAGE_SIZE - 1))
#define MMU_FLASH_MASK_FROM_VAL(PAGE_SZ) (~((PAGE_SZ) - 1))
#define MMU_DROM_END_ENTRY_VADDR_FROM_VAL(PAGE_SZ) (SOC_DRAM_FLASH_ADDRESS_HIGH - (PAGE_SZ))
/**
* MMU mapping must always be in the unit of a CONFIG_MMU_PAGE_SIZE
* This macro is a helper for you to get needed page nums to be mapped. e.g.:
* Let's say CONFIG_MMU_PAGE_SIZE is 64KB.
* - v_start = 0x4200_0004
* - size = 4 * 64KB
*
* You should map from 0x4200_0000, then map 5 pages.
*/
#define GET_REQUIRED_MMU_PAGES(size, v_start) ((size + (v_start - (v_start & MMU_FLASH_MASK)) + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE)
/**
* @brief Get number of free pages
*
* @return Number of free pages
*/
uint32_t bootloader_mmap_get_free_pages(void);
/**
* @brief Map a region of flash to data memory
*
* @important In bootloader code, only one region can be bootloader_mmaped at once. The previous region must be bootloader_munmapped before another region is mapped.
*
* @important In app code, these functions are not thread safe.
*
* Call bootloader_munmap once for each successful call to bootloader_mmap.
*
* In esp-idf app, this function maps directly to spi_flash_mmap with the @ref
* spi_flash_mmap_flag_t::SPI_FLASH_MMAP_FLAG_BLOCKS_WRITE flag set. When XIP on PSRAM (`CONFIG_SPIRAM_XIP_FROM_PSRAM`) enabled, flash erasing/writing
* will be blocked until unmap.
*
* @param offset - Starting flash offset to map to memory.
* @param length - Length of data to map.
*
* @return Pointer to mapped data memory (at src_addr), or NULL
* if an allocation error occurred.
*/
const void *bootloader_mmap(uint32_t src_addr, uint32_t size);
/**
* @brief Unmap a previously mapped region of flash
*
* Call bootloader_munmap once for each successful call to bootloader_mmap.
*/
void bootloader_munmap(const void *mapping);
/**
* @brief Read data from Flash.
*
*
* @note All of src, dest and size have to be 4-byte aligned.
*
* @param src source address of the data in Flash.
* @param dest pointer to the destination buffer
* @param size length of data
* @param allow_decrypt If true and flash encryption is enabled, data on flash
* will be decrypted transparently as part of the read.
*
* @return ESP_OK on success, ESP_ERR_FLASH_OP_FAIL on SPI failure,
* ESP_ERR_FLASH_OP_TIMEOUT on SPI timeout.
*/
esp_err_t bootloader_flash_read(size_t src_addr, void *dest, size_t size, bool allow_decrypt);
/**
* @brief Write data to Flash.
*
* @note All of dest_addr, src and size have to be 4-byte aligned. If write_encrypted is set, dest_addr and size must be 32-byte aligned.
*
* @note In bootloader, when write_encrypted == true, the src buffer is encrypted in place.
*
* @note [ESP-TEE] Using this API from the TEE will return an error if the dest_addr lies
* within the active TEE partition range.
*
* @param dest_addr Destination address to write in Flash.
* @param src Pointer to the data to write to flash
* @param size Length of data in bytes.
* @param write_encrypted If true, data will be written encrypted on flash.
*
* @return ESP_OK on success, ESP_ERR_FLASH_OP_FAIL on SPI failure,
* ESP_ERR_FLASH_OP_TIMEOUT on SPI timeout.
*/
esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool write_encrypted);
/**
* @brief Erase the Flash sector.
*
* @param sector Sector number, the count starts at sector 0, 4KB per sector.
*
* @return esp_err_t
*/
esp_err_t bootloader_flash_erase_sector(size_t sector);
/**
* @brief Erase the Flash range.
*
* @note [ESP-TEE] Using this API from the TEE will return an error if the start_addr lies
* within the active TEE partition range.
*
* @param start_addr start address of flash offset
* @param size sector aligned size to be erased
*
* @return esp_err_t
*/
esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size);
/**
* @brief Enable the flash write protect (WEL bit).
*/
void bootloader_enable_wp(void);
/**
* @brief Once this function is called,
* any on-going internal operations will be terminated and the device will return to its default power-on
* state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
* (WEL) status, Program/Erase Suspend status, etc.
*/
void bootloader_spi_flash_reset(void);
//-------------------------------- Init APIs -------------------------------- //
//For SDK usage only
/**
* @brief Initialize spi_flash in bootloader and print flash info
*
@@ -33,6 +177,7 @@ void bootloader_flash_hardware_init(void);
*/
void bootloader_init_mspi_clock(void);
#ifdef __cplusplus
}
#endif
components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+14 -22
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@@ -4,17 +4,22 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include <bootloader_flash_priv.h>
#include <esp_log.h>
#include "esp_efuse.h"
#include "sdkconfig.h"
#include "esp_efuse.h"
#include "esp_log.h"
#include "esp_flash_encrypt.h"
#include "esp_private/bootloader_flash_internal.h"
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
#include "hal/spi_flash_types.h"
#include "spi_flash_defs.h"
#include "spi_flash_err.h"
#if !NON_OS_BUILD
#include "spi_flash_mmap.h"
// This dependency will be removed in the future. IDF-5025
#include "esp_flash.h"
#endif
#include "hal/spi_flash_ll.h"
#include "rom/spi_flash.h"
@@ -23,9 +28,6 @@
#include "hal/spimem_flash_ll.h"
#endif
// This dependency will be removed in the future. IDF-5025
#include "esp_flash.h"
#include "esp_rom_spiflash.h"
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
@@ -64,7 +66,7 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
return NULL; /* existing mapping in use... */
}
const void *result = NULL;
uint32_t src_page = src_addr & ~(SPI_FLASH_MMU_PAGE_SIZE - 1);
uint32_t src_page = src_addr & ~(CONFIG_MMU_PAGE_SIZE - 1);
size += (src_addr - src_page);
esp_err_t err = spi_flash_mmap(src_page, size, SPI_FLASH_MMAP_FLAG_DATA | SPI_FLASH_MMAP_FLAG_BLOCKS_WRITE, &result, &map);
if (err != ESP_OK) {
@@ -123,7 +125,6 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "esp_flash_chips/spi_flash_defs.h"
#if ESP_TEE_BUILD
#include "esp_fault.h"
@@ -362,7 +363,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
#if CONFIG_IDF_TARGET_ESP32
uint32_t count = GET_REQUIRED_MMU_PAGES(size, src_paddr);
int e = cache_flash_mmu_set(0, 0, FLASH_MMAP_VADDR, src_paddr_aligned, 64, count);
ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", src_paddr_aligned, (uint32_t)FLASH_MMAP_VADDR, count * SPI_FLASH_MMU_PAGE_SIZE);
ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", src_paddr_aligned, (uint32_t)FLASH_MMAP_VADDR, count * CONFIG_MMU_PAGE_SIZE);
if (e != 0) {
ESP_EARLY_LOGE(TAG, "cache_flash_mmu_set failed: %d", e);
Cache_Read_Enable(0);
@@ -491,20 +492,20 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
#else
cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
//---------------Invalidating entries at to-be-mapped v_addr------------------------
cache_hal_invalidate_addr(FLASH_READ_VADDR, SPI_FLASH_MMU_PAGE_SIZE);
cache_hal_invalidate_addr(FLASH_READ_VADDR, CONFIG_MMU_PAGE_SIZE);
#endif
#endif
//---------------Do mapping------------------------
ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08" PRIx32 " (was 0x%08" PRIx32 ")", map_at, current_read_mapping);
#if CONFIG_IDF_TARGET_ESP32
//Should never fail if we only map a SPI_FLASH_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
//Should never fail if we only map a CONFIG_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
// Return value unused if asserts are disabled
int e __attribute__((unused)) = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
assert(e == 0);
#else
uint32_t actual_mapped_len = 0;
mmu_hal_map_region(0, MMU_TARGET_FLASH0, FLASH_READ_VADDR, map_at, SPI_FLASH_MMU_PAGE_SIZE - 1, &actual_mapped_len);
mmu_hal_map_region(0, MMU_TARGET_FLASH0, FLASH_READ_VADDR, map_at, CONFIG_MMU_PAGE_SIZE - 1, &actual_mapped_len);
#endif
current_read_mapping = map_at;
@@ -1017,15 +1018,6 @@ esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
return ESP_OK;
}
bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
{
#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
return efuse_ll_get_flash_type();
#else
return false;
#endif
}
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
{
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c
+2 -1
View File
@@ -25,7 +25,8 @@
#include "flash_qio_mode.h"
#include "bootloader_common.h"
#include "bootloader_flash_config.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c
+2 -1
View File
@@ -17,7 +17,8 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#include "soc/spi_pins.h"
#include "hal/mmu_hal.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
+2 -1
View File
@@ -19,7 +19,8 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+2 -1
View File
@@ -22,7 +22,8 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c
+2 -1
View File
@@ -18,7 +18,8 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+2 -1
View File
@@ -18,7 +18,8 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
+2 -1
View File
@@ -18,7 +18,8 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c
+2 -1
View File
@@ -12,7 +12,8 @@
#include "esp_rom_gpio.h"
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c
+2 -1
View File
@@ -20,7 +20,8 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+2 -1
View File
@@ -16,7 +16,7 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
@@ -24,6 +24,7 @@
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
void IRAM_ATTR bootloader_flash_update_id(void)
{
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c
+2 -1
View File
@@ -20,7 +20,8 @@
#include "soc/soc_caps.h"
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
+6 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,7 +20,8 @@
#include "soc/soc_caps.h"
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
#include "bootloader_common.h"
#include "bootloader_flash.h"
#include "bootloader_init.h"
@@ -28,6 +29,7 @@
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/efuse_ll.h"
#define FLASH_IO_MATRIX_DUMMY_40M 0
#define FLASH_IO_MATRIX_DUMMY_80M 0
@@ -50,7 +52,7 @@ void bootloader_flash_update_size(uint32_t size)
void IRAM_ATTR bootloader_flash_cs_timing_config()
{
//SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time, cs_hold_delay registers for FLASH, so we only need to set SPI0 related registers here
if (bootloader_flash_is_octal_mode_enabled()) {
if (efuse_ll_get_flash_type()) {
SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, FLASH_CS_HOLD_TIME, SPI_MEM_CS_HOLD_TIME_S);
@@ -286,7 +288,7 @@ esp_err_t bootloader_init_spi_flash(void)
bootloader_flash_unlock();
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
if (!bootloader_flash_is_octal_mode_enabled()) {
if (!efuse_ll_get_flash_type()) {
bootloader_enable_qio_mode();
}
#endif
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c
+2 -1
View File
@@ -16,7 +16,7 @@
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
@@ -25,6 +25,7 @@
#include "hal/cache_ll.h"
#include "hal/clk_tree_ll.h"
#include "esp_private/bootloader_flash_internal.h"
#include "spi_flash_defs.h"
void IRAM_ATTR bootloader_flash_update_id(void)
{
components/bootloader_support/bootloader_flash/src/flash_qio_mode.c
+2 -1
View File
@@ -8,7 +8,7 @@
#include "bootloader_flash_config.h"
#include "flash_qio_mode.h"
#include "sdkconfig.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_log.h"
#include "esp_err.h"
#include "esp_attr.h"
@@ -19,6 +19,7 @@
#include "soc/io_mux_reg.h"
#include "esp_private/spi_flash_os.h"
#include "bootloader_flash_override.h"
#include "spi_flash_defs.h"
ESP_LOG_ATTR_TAG(TAG, "qio_mode");
components/bootloader_support/src/bootloader_common.c
+1 -1
View File
@@ -15,7 +15,7 @@
#include "esp_rom_sys.h"
#include "esp_flash_partitions.h"
#include "esp_image_format.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_common.h"
#include "bootloader_utility.h"
#include "bootloader_sha_flash.h"
components/bootloader_support/src/bootloader_common_loader.c
+2 -1
View File
@@ -19,9 +19,10 @@
#include "soc/efuse_reg.h"
#include "soc/chip_revision.h"
#include "hal/efuse_hal.h"
#include "hal/misc.h"
#include "esp_image_format.h"
#include "sys/param.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_rom_caps.h"
#include "esp_macros.h"
components/bootloader_support/src/bootloader_init.c
+1 -1
View File
@@ -9,7 +9,7 @@
#include "esp_attr.h"
#include "esp_log.h"
#include "bootloader_init.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_flash_config.h"
#include "bootloader_random.h"
#include "bootloader_clock.h"
components/bootloader_support/src/bootloader_utility.c
+5 -5
View File
@@ -38,7 +38,7 @@
#include "esp_secure_boot.h"
#include "esp_flash_encrypt.h"
#include "esp_flash_partitions.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_random.h"
#include "bootloader_config.h"
#include "bootloader_common.h"
@@ -1067,12 +1067,12 @@ static void set_cache_and_start_app(
//The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
drom_size = (drom_load_addr - drom_load_addr_aligned) + drom_size;
#if CONFIG_IDF_TARGET_ESP32
uint32_t drom_page_count = (drom_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE;
uint32_t drom_page_count = (drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE;
rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * CONFIG_MMU_PAGE_SIZE);
#else
uint32_t actual_mapped_len = 0;
if (s_flash_seg_needs_map(drom_load_addr_aligned)) {
@@ -1091,12 +1091,12 @@ static void set_cache_and_start_app(
//The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
irom_size = (irom_load_addr - irom_load_addr_aligned) + irom_size;
#if CONFIG_IDF_TARGET_ESP32
uint32_t irom_page_count = (irom_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE;
uint32_t irom_page_count = (irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE;
rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
ESP_LOGV(TAG, "rc=%d", rc);
ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * CONFIG_MMU_PAGE_SIZE);
#else
if (s_flash_seg_needs_map(irom_load_addr_aligned)) {
mmu_hal_map_region(0, MMU_TARGET_FLASH0, irom_load_addr_aligned, irom_addr_aligned, irom_size, &actual_mapped_len);
components/bootloader_support/src/bootloader_utility_tee.c
+1 -1
View File
@@ -16,7 +16,7 @@
#include "esp_image_format.h"
#include "bootloader_config.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_utility.h"
#include "bootloader_utility_tee.h"
components/bootloader_support/src/esp32/bootloader_esp32.c
-1
View File
@@ -16,7 +16,6 @@
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_cpu.h"
#include "soc/dport_reg.h"
components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
+1 -1
View File
@@ -30,7 +30,7 @@
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
-1
View File
@@ -34,7 +34,6 @@
#include "soc/regi2c_lp_bias.h"
#include "soc/regi2c_bias.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
+1 -1
View File
@@ -31,7 +31,7 @@
#include "bootloader_mem.h"
#include "esp_private/regi2c_ctrl.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
+1 -1
View File
@@ -33,7 +33,7 @@
#include "soc/regi2c_lp_bias.h"
#include "soc/regi2c_bias.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
+1 -1
View File
@@ -33,7 +33,7 @@
#include "soc/regi2c_lp_bias.h"
#include "soc/regi2c_bias.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
+1 -1
View File
@@ -32,7 +32,7 @@
#include "soc/regi2c_lp_bias.h"
#include "soc/regi2c_bias.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32h21/bootloader_esp32h21.c
+1 -1
View File
@@ -32,7 +32,7 @@
#include "soc/regi2c_lp_bias.h"
#include "soc/regi2c_bias.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
+1 -1
View File
@@ -30,7 +30,7 @@
#include "esp_private/regi2c_ctrl.h"
#include "soc/hp_system_reg.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+1 -1
View File
@@ -33,7 +33,7 @@
#include "soc/regi2c_lp_bias.h"
#include "soc/regi2c_bias.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
-1
View File
@@ -16,7 +16,6 @@
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
+1 -1
View File
@@ -33,7 +33,7 @@
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
+2 -1
View File
@@ -16,7 +16,7 @@
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_soc.h"
#include "esp_efuse.h"
#include "esp_private/bootloader_flash_internal.h"
@@ -33,6 +33,7 @@
#include "hal/assist_debug_ll.h"
#include "esp_rom_sys.h"
#include "soc/regi2c_bias.h"
#include "soc/regi2c_mpll.h"
#include "hal/regi2c_ctrl.h"
#include "hal/psram_ctrlr_ll.h"
components/bootloader_support/src/flash_encryption/flash_encrypt.c
+1 -1
View File
@@ -5,7 +5,7 @@
*/
#include <strings.h>
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_random.h"
#include "esp_image_format.h"
#include "esp_flash_encrypt.h"
components/efuse/CMakeLists.txt
+3 -3
View File
@@ -32,15 +32,15 @@ list(APPEND srcs "src/esp_efuse_api.c"
if(non_os_build)
idf_component_register(SRCS "${srcs}"
PRIV_REQUIRES bootloader_support soc spi_flash esp_hal_security
PRIV_REQUIRES bootloader_support soc esp_hal_security
INCLUDE_DIRS "${include_dirs}"
PRIV_INCLUDE_DIRS "${private_include}")
else()
list(APPEND srcs "src/esp_efuse_startup.c")
if(${target} STREQUAL "linux")
set(priv_requires soc spi_flash esp_system esp_partition esp_hal_security)
set(priv_requires soc esp_system esp_partition esp_hal_security)
else()
set(priv_requires bootloader_support soc spi_flash esp_system esp_partition esp_app_format esp_hal_security)
set(priv_requires bootloader_support soc esp_system esp_partition esp_app_format esp_hal_security)
endif()
idf_component_register(SRCS "${srcs}"
PRIV_REQUIRES "${priv_requires}"
components/efuse/src/esp_efuse_utility.c
+1 -1
View File
@@ -390,7 +390,7 @@ void esp_efuse_init_virtual_mode_in_ram(void)
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
#include "../bootloader_flash/include/bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
static uint32_t esp_efuse_flash_offset = 0;
static uint32_t esp_efuse_flash_size = 0;
components/esp_asrc_adapter/CMakeLists.txt
+1 -1
View File
@@ -17,4 +17,4 @@ idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
PRIV_INCLUDE_DIRS "."
REQUIRES esp_hal_asrc esp_driver_dma esp_mm
PRIV_REQUIRES esp_hw_support esp_pm)
PRIV_REQUIRES esp_hw_support esp_pm esp_mspi)
components/esp_driver_dma/CMakeLists.txt
+1 -1
View File
@@ -50,6 +50,6 @@ idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${public_include}
PRIV_INCLUDE_DIRS "src"
REQUIRES ${requires}
PRIV_REQUIRES esp_mm efuse
PRIV_REQUIRES esp_mm efuse esp_mspi
LDFRAGMENTS "linker.lf"
)
components/esp_driver_dma/test_apps/dma/main/CMakeLists.txt
+1 -1
View File
@@ -23,7 +23,7 @@ endif()
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
# the component can be registered as WHOLE_ARCHIVE
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_mm esp_driver_gpio esp_psram esp_driver_dma efuse
PRIV_REQUIRES unity esp_mm esp_driver_gpio esp_psram esp_driver_dma efuse esp_mspi
WHOLE_ARCHIVE)
idf_component_get_property(lib_name esp_driver_dma COMPONENT_LIB)
components/esp_driver_i2s/CMakeLists.txt
+1 -1
View File
@@ -6,7 +6,7 @@ endif()
set(srcs)
set(include "include")
set(priv_requires esp_driver_gpio esp_driver_dma esp_pm esp_mm esp_hal_clock)
set(priv_requires esp_driver_gpio esp_driver_dma esp_pm esp_mm esp_hal_clock esp_mspi)
# TODO(IDF-15984): potentially remove __ULP_BUILDV2 handling from esp_driver_i2s
if(__ULP_BUILDV2)
components/esp_driver_i2s/test_apps/i2s/main/CMakeLists.txt
+2 -2
View File
@@ -11,6 +11,6 @@ if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED)
endif()
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_driver_pcnt spi_flash
esp_driver_gpio esp_driver_i2s esp_driver_uart esp_psram esp_driver_gptimer
PRIV_REQUIRES unity esp_driver_pcnt esp_driver_gpio esp_driver_i2s esp_driver_uart
esp_psram esp_mspi esp_driver_gptimer
WHOLE_ARCHIVE)
components/esp_driver_spi/CMakeLists.txt
+1 -1
View File
@@ -30,6 +30,6 @@ idf_component_register(
SRCS ${srcs}
INCLUDE_DIRS ${public_include}
REQUIRES esp_pm esp_hal_gpspi esp_driver_dma
PRIV_REQUIRES esp_timer esp_mm esp_driver_gpio spi_flash
PRIV_REQUIRES esp_timer esp_mm esp_driver_gpio spi_flash esp_mspi
LDFRAGMENTS "linker.lf"
)
components/esp_driver_spi/test_apps/slave/main/CMakeLists.txt
+1 -1
View File
@@ -11,6 +11,6 @@ set(srcs
idf_component_register(
SRCS ${srcs}
# esp_psram is required for CONFIG_SPIRAM, used by the release configs
PRIV_REQUIRES esp_driver_spi spi_flash esp_driver_gpio esp_psram
PRIV_REQUIRES esp_driver_spi esp_driver_gpio esp_mspi esp_psram
WHOLE_ARCHIVE
)
components/esp_driver_uart/CMakeLists.txt
+1 -1
View File
@@ -35,7 +35,7 @@ endif()
if(${target} STREQUAL "linux")
set(priv_requires esp_ringbuf)
else()
set(priv_requires esp_pm esp_driver_gpio esp_driver_dma esp_ringbuf esp_mm)
set(priv_requires esp_pm esp_driver_gpio esp_driver_dma esp_ringbuf esp_mm esp_mspi)
endif()
idf_component_register(
components/esp_hal_dma/CMakeLists.txt
-3
View File
@@ -1,7 +1,4 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
set(srcs)
set(public_include "include")
components/esp_hal_mspi/CMakeLists.txt
+13 -8
View File
@@ -1,14 +1,19 @@
idf_build_get_property(target IDF_TARGET)
idf_build_get_property(esp_tee_build ESP_TEE_BUILD)
if(${target} STREQUAL "linux")
idf_component_register(INCLUDE_DIRS "include"
REQUIRES soc hal)
return()
set(srcs)
set(includes "include")
set(requires soc hal esp_hal_gpspi)
set(priv_requires esp_hal_gpio)
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
set(srcs)
set(includes "include" "${target}/include")
if(NOT "${target}" STREQUAL "linux")
# TODO: IDF-15106 remove esp_hal_clock dependency
list(APPEND requires "esp_hal_clock")
endif()
if(esp_tee_build)
if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1)
@@ -35,6 +40,6 @@ list(APPEND srcs "${target}/mspi_periph.c")
idf_component_register(
SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES soc hal esp_hal_gpspi esp_hal_clock # TODO: IDF-15106 remove esp_hal_clock dependency
PRIV_REQUIRES esp_hal_gpio
REQUIRES ${requires}
PRIV_REQUIRES ${priv_requires}
)
components/esp_hal_mspi/esp32c2/include/hal/spimem_flash_ll.h
+3
View File
@@ -58,6 +58,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -325,6 +326,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -335,6 +337,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32c3/include/hal/spimem_flash_ll.h
+3
View File
@@ -58,6 +58,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -325,6 +326,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -335,6 +337,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32c5/include/hal/spimem_flash_ll.h
+3
View File
@@ -62,6 +62,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -361,6 +362,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -371,6 +373,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32c6/include/hal/spimem_flash_ll.h
+3
View File
@@ -59,6 +59,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -326,6 +327,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -336,6 +338,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32c61/include/hal/spimem_flash_ll.h
+3
View File
@@ -62,6 +62,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -356,6 +357,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -366,6 +368,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32h2/include/hal/spimem_flash_ll.h
+3
View File
@@ -60,6 +60,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -327,6 +328,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -337,6 +339,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32h21/include/hal/mspi_ll.h
+1
View File
@@ -25,6 +25,7 @@
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/spi_mem_c_reg.h"
#ifdef __cplusplus
extern "C" {
components/esp_hal_mspi/esp32h21/include/hal/spimem_flash_ll.h
+3
View File
@@ -60,6 +60,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -355,6 +356,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -365,6 +367,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32h4/include/hal/spimem_flash_ll.h
+2
View File
@@ -356,6 +356,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -366,6 +367,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32p4/include/hal/spimem_flash_ll.h
+3
View File
@@ -65,6 +65,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -367,6 +368,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -377,6 +379,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32s2/include/hal/spimem_flash_ll.h
+3
View File
@@ -55,6 +55,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -262,6 +263,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -272,6 +274,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32s3/include/hal/spimem_flash_ll.h
+3
View File
@@ -59,6 +59,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
*
* @return true if last command is done, otherwise false.
*/
__attribute__((always_inline))
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
{
return (dev->cmd.val == 0);
@@ -329,6 +330,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -339,6 +341,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h
+2
View File
@@ -366,6 +366,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_dp = 1;
@@ -376,6 +377,7 @@ static inline void spimem_flash_ll_enter_dpd(spi_mem_dev_t *dev)
*
* @param dev Beginning address of the peripheral registers.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
{
dev->cmd.flash_res = 1;
components/esp_hal_mspi/include/hal/spi_flash_types.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
components/esp_hal_mspi/linux/include/hal/.gitkeep
View File
components/esp_hal_mspi/linux/mspi_periph.c
+5
View File
@@ -0,0 +1,5 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
components/esp_hw_support/CMakeLists.txt
+3 -47
View File
@@ -14,10 +14,6 @@ endif()
set(public_include_dirs "include" "include/soc"
"ldo/include" "debug_probe/include" "etm/include"
"mspi/mspi_timing_tuning/include" "mspi/mspi_timing_tuning/tuning_scheme_impl/include"
"mspi/mspi_intr/include"
"mspi/esp_mspi_align/include"
"mspi/mspi_mem_barrier/include"
"power_supply/include" "modem/include")
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/include/soc/${target}")
@@ -44,7 +40,7 @@ endif()
set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_regi2c esp_hal_uart esp_hal_debug_assist)
set(priv_requires efuse # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
spi_flash
esp_mspi
bootloader_support
esp_hal_wdt
esp_hal_rtc_timer
@@ -55,9 +51,6 @@ set(priv_requires efuse # only esp_hw_support/adc_share_hw_ctrl.
)
set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "mspi/esp_mspi_align/esp_mspi_align.c")
endif()
if(NOT non_os_build)
list(APPEND srcs "esp_clk.c"
"clk_ctrl_os.c"
@@ -76,8 +69,7 @@ if(NOT non_os_build)
"port/${target}/esp_clk_tree.c"
"spi_bus_lock.c"
"heap_align_hw.c"
"clk_utils.c"
"mspi/mspi_mem_barrier/mspi_mem_barrier.c")
"clk_utils.c")
if(CONFIG_SOC_USB_OTG_SUPPORTED)
list(APPEND srcs "usb_phy/usb_phy.c")
endif()
@@ -156,27 +148,6 @@ if(NOT non_os_build)
"port/regdma_link.c")
endif()
if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
list(APPEND srcs "mspi/mspi_timing_tuning/mspi_timing_tuning.c")
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY AND NOT CONFIG_IDF_TARGET_ESP32S3)
set(mspi_delay_file
"${CMAKE_CURRENT_LIST_DIR}/mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c"
)
if(EXISTS "${mspi_delay_file}")
list(APPEND srcs "mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c")
endif()
endif()
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_DQS)
list(APPEND srcs "mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_dqs.c")
endif()
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY)
list(APPEND srcs "mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c")
endif()
list(APPEND srcs "mspi/mspi_intr/mspi_intr.c")
endif()
if(CONFIG_SOC_RTC_FAST_MEM_SUPPORTED AND CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB)
list(APPEND srcs "sleep_wake_stub.c")
endif()
@@ -196,18 +167,6 @@ if(NOT non_os_build)
else()
if(ESP_TEE_BUILD)
list(APPEND srcs "esp_clk.c" "hw_random.c")
if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1)
list(APPEND srcs "mspi/mspi_timing_tuning/mspi_timing_tuning.c")
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY)
list(APPEND srcs "mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c")
endif()
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_DQS)
list(APPEND srcs "mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_dqs.c")
endif()
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY)
list(APPEND srcs "mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c")
endif()
endif()
endif()
# Requires "_esp_error_check_failed()" function
@@ -224,15 +183,12 @@ idf_component_register(SRCS ${srcs}
PRIV_INCLUDE_DIRS port/include include/esp_private
REQUIRES ${requires}
PRIV_REQUIRES "${priv_requires}"
LDFRAGMENTS linker.lf ldo/linker.lf mspi/linker.lf)
LDFRAGMENTS linker.lf ldo/linker.lf)
idf_define_esp_err_codes(HEADERS include/esp_memprot_err.h)
idf_build_get_property(target IDF_TARGET)
add_subdirectory(port/${target})
if(CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING)
add_subdirectory(mspi/mspi_timing_tuning/port/${target})
endif()
add_subdirectory(lowpower)
add_subdirectory(modem)
components/esp_hw_support/README.md
+1 -1
View File
@@ -86,7 +86,7 @@ This document describes the implementation differences of MSPI interrupt handlin
| File | Description |
|------|-------------|
| `components/esp_hw_support/mspi/mspi_intr/mspi_intr.c` | Shared MSPI interrupt management |
| `components/esp_mspi/mspi_intr/mspi_intr.c` | Shared MSPI interrupt management |
| `components/esp_psram/system_layer/esp_psram_mspi.c` | PSRAM specific interrupt handling |
---
components/esp_hw_support/mspi/linker.lf
-22
View File
@@ -1,22 +0,0 @@
[mapping:esp_mspi_align]
archive: libesp_hw_support.a
entries:
if APP_BUILD_TYPE_PURE_RAM_APP = n:
esp_mspi_align:esp_mspi_get_alignment (noflash)
esp_mspi_align:esp_mspi_buffer_alignment_satisfied (noflash)
[mapping:mspi_timing_tuning_driver]
archive: libesp_hw_support.a
entries:
if APP_BUILD_TYPE_PURE_RAM_APP = n:
mspi_timing_tuning (noflash)
if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY = y:
mspi_timing_by_mspi_delay (noflash)
mspi_timing_config (noflash)
if SOC_MEMSPI_TIMING_TUNING_BY_DQS = y:
mspi_timing_by_dqs (noflash)
if SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY = y:
mspi_timing_by_flash_delay (noflash)
if SOC_MEMSPI_TIMING_TUNING_BY_DQS = y || SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY = y:
mspi_timing_config (noflash)
components/esp_hw_support/sleep_gpio.c
+1 -2
View File
@@ -40,7 +40,6 @@
#include "esp_private/sleep_gpio.h"
#include "esp_private/spi_flash_os.h"
#include "esp_private/startup_internal.h"
#include "bootloader_flash.h"
ESP_LOG_ATTR_TAG(TAG, "sleep_gpio");
@@ -152,7 +151,7 @@ void esp_sleep_config_gpio_isolate(void)
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_HD), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_WP), GPIO_PULLUP_ONLY);
#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
bool octal_mspi_required = bootloader_flash_is_octal_mode_enabled();
bool octal_mspi_required = spi_flash_is_octal_mode_enabled();
#if CONFIG_SPIRAM_MODE_OCT
octal_mspi_required |= true;
#endif // CONFIG_SPIRAM_MODE_OCT
components/esp_hw_support/test_apps/.build-test-rules.yml
-12
View File
@@ -22,18 +22,6 @@ components/esp_hw_support/test_apps/host_test_linux:
depends_components:
- esp_hw_support
components/esp_hw_support/test_apps/mspi:
depends_components:
- esp_hw_support
- spi_flash
- esp_partition
- esp_hal_mspi
- soc
disable:
- if: IDF_TARGET not in ["esp32s3", "esp32p4", "esp32c61", "esp32c5", "esp32s31"]
- if: CONFIG_NAME in ["generic_timing_tuning_log_safe", "generic_timing_tuning_xip"] and IDF_TARGET in ["esp32s31"]
- if: CONFIG_NAME == "120sdr_120sdr" and IDF_TARGET in ["esp32s3", "esp32p4", "esp32s31"]
components/esp_hw_support/test_apps/mspi_psram_with_dfs:
depends_components:
- esp_hw_support
components/esp_image_verify/src/bootloader_sha_flash.c
+2 -2
View File
@@ -5,7 +5,7 @@
*/
#include <sys/param.h>
#include "esp_log.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_sha.h"
#include "bootloader_sha_flash.h"
#include "spi_flash_mmap.h"
@@ -57,7 +57,7 @@ static esp_err_t bootloader_sha_flash_contents(esp_sha_type type, uint32_t flash
return ESP_ERR_NO_MEM;
}
uint32_t max_image_len;
if (__builtin_mul_overflow(max_pages, SPI_FLASH_MMU_PAGE_SIZE, &max_image_len)) {
if (__builtin_mul_overflow(max_pages, CONFIG_MMU_PAGE_SIZE, &max_image_len)) {
max_image_len = UINT32_MAX;
}
uint32_t partial_image_len = MIN(len, max_image_len); /* Read the image that fits in the free MMU pages */
components/esp_image_verify/src/esp_image_format.c
+7 -8
View File
@@ -10,7 +10,7 @@
#include <esp_fault.h>
#include <esp_log.h>
#include <esp_attr.h>
#include <bootloader_flash_priv.h>
#include <esp_private/bootloader_flash_internal.h>
#include <bootloader_random.h>
#include <bootloader_sha.h>
#include "bootloader_util.h"
@@ -22,7 +22,6 @@
#include "soc/soc_caps.h"
#include "hal/mmu_types.h"
#include "hal/cache_ll.h"
#include "spi_flash_mmap.h"
#include "hal/efuse_hal.h"
#include "sdkconfig.h"
#include "esp_macros.h"
@@ -688,7 +687,7 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme
return ESP_ERR_NO_MEM;
}
uint32_t max_image_len;
if (__builtin_mul_overflow(max_pages, SPI_FLASH_MMU_PAGE_SIZE, &max_image_len)) {
if (__builtin_mul_overflow(max_pages, CONFIG_MMU_PAGE_SIZE, &max_image_len)) {
max_image_len = UINT32_MAX;
}
segment_data.data_len = MIN(data_len_remain, max_image_len);
@@ -899,18 +898,18 @@ static esp_err_t verify_segment_header(int index, const esp_image_segment_header
metadata->mmu_page_size = (1UL << mmu_page_size);
} else {
// Fall back to default MMU page size
metadata->mmu_page_size = SPI_FLASH_MMU_PAGE_SIZE;
metadata->mmu_page_size = CONFIG_MMU_PAGE_SIZE;
}
if (metadata->mmu_page_size != SPI_FLASH_MMU_PAGE_SIZE) {
ESP_LOGI(TAG, "MMU page size mismatch, configured: 0x%x, found: 0x%"PRIx32, SPI_FLASH_MMU_PAGE_SIZE, metadata->mmu_page_size);
if (metadata->mmu_page_size != CONFIG_MMU_PAGE_SIZE) {
ESP_LOGI(TAG, "MMU page size mismatch, configured: 0x%x, found: 0x%"PRIx32, CONFIG_MMU_PAGE_SIZE, metadata->mmu_page_size);
}
} else if (index == 0 && is_bootloader(metadata->start_addr)) {
// Bootloader always uses the default MMU page size
metadata->mmu_page_size = SPI_FLASH_MMU_PAGE_SIZE;
metadata->mmu_page_size = CONFIG_MMU_PAGE_SIZE;
}
#else // SOC_MMU_PAGE_SIZE_CONFIGURABLE
metadata->mmu_page_size = SPI_FLASH_MMU_PAGE_SIZE;
metadata->mmu_page_size = CONFIG_MMU_PAGE_SIZE;
#endif // !SOC_MMU_PAGE_SIZE_CONFIGURABLE
const int mmu_page_size = metadata->mmu_page_size;
components/esp_image_verify/src/secure_boot_v1/secure_boot.c
+1 -1
View File
@@ -17,7 +17,7 @@
#include "sdkconfig.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_random.h"
#include "esp_image_format.h"
#include "esp_secure_boot.h"
components/esp_image_verify/src/secure_boot_v1/secure_boot_signatures_app.c
+1 -1
View File
@@ -5,7 +5,7 @@
*/
#include "sdkconfig.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_sha.h"
#include "bootloader_sha_flash.h"
#include "esp_log.h"
components/esp_image_verify/src/secure_boot_v1/secure_boot_signatures_bootloader.c
+1 -1
View File
@@ -5,7 +5,7 @@
*/
#include "sdkconfig.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_sha.h"
#include "bootloader_sha_flash.h"
#include "esp_log.h"
components/esp_image_verify/src/secure_boot_v2/secure_boot.c
+1 -1
View File
@@ -8,7 +8,7 @@
#include "sdkconfig.h"
#include "esp_log.h"
#include "esp_secure_boot.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_sha.h"
#include "bootloader_sha_flash.h"
#include "esp_image_format.h"
components/esp_image_verify/src/secure_boot_v2/secure_boot_signatures_app.c
+1 -1
View File
@@ -5,7 +5,7 @@
*/
#include "sdkconfig.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_sha.h"
#include "bootloader_sha_flash.h"
#include "bootloader_signature.h"
components/esp_image_verify/src/secure_boot_v2/secure_boot_signatures_bootloader.c
+1 -1
View File
@@ -7,7 +7,7 @@
#include <string.h>
#include "esp_fault.h"
#include "bootloader_flash_priv.h"
#include "esp_private/bootloader_flash_internal.h"
#include "bootloader_sha.h"
#include "bootloader_sha_flash.h"
#include "bootloader_signature.h"
components/esp_lcd/test_apps/rgb_lcd/main/CMakeLists.txt
+1 -1
View File
@@ -5,5 +5,5 @@ set(srcs "test_app_main.c"
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
# the component can be registered as WHOLE_ARCHIVE
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES esp_lcd unity esp_timer spi_flash esp_driver_ppa efuse
PRIV_REQUIRES esp_lcd unity esp_timer esp_mspi esp_driver_ppa efuse
WHOLE_ARCHIVE)
components/esp_libc/CMakeLists.txt
+1 -1
View File
@@ -82,7 +82,7 @@ else()
list(APPEND ldfragments src/picolibc/libc.lf)
endif()
set(priv_reqs soc spi_flash)
set(priv_reqs soc esp_mspi)
if(IDF_BUILD_V2)
if(CONFIG_VFS_SUPPORT_IO)
components/esp_libc/test_apps/newlib/main/CMakeLists.txt
+1 -1
View File
@@ -21,5 +21,5 @@ if(CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS)
endif()
idf_component_register(SRCS "${srcs}"
PRIV_REQUIRES unity vfs cmock esp_timer spi_flash test_utils pthread esp_psram
PRIV_REQUIRES unity vfs cmock esp_timer esp_mspi test_utils pthread esp_psram
WHOLE_ARCHIVE)
components/esp_mm/CMakeLists.txt
+2 -2
View File
@@ -6,8 +6,8 @@ endif()
set(includes "include")
# Note: requires spi_flash for cache_utils, will be refactored
set(priv_requires heap spi_flash esp_hal_dma)
# Note: requires esp_mspi for cache_utils
set(priv_requires heap esp_hal_dma esp_mspi)
set(srcs)
components/esp_mspi/CMakeLists.txt
+112
View File
@@ -0,0 +1,112 @@
idf_build_get_property(target IDF_TARGET)
idf_build_get_property(non_os_build NON_OS_BUILD)
if(${target} STREQUAL "linux")
idf_component_register(SRCS "linux/cache_utils.c"
INCLUDE_DIRS include
REQUIRES esp_hal_mspi)
return()
endif()
if(non_os_build OR CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
# efuse is required by esp_mspi_align.c to query the flash encryption state
set(priv_requires bootloader_support soc esp_hal_gpio efuse)
set(requires hal esp_hal_mspi)
set(srcs "spi_flash_wrap.c" "spi_flash_os_tee_stub.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "esp_mspi_align/esp_mspi_align.c")
endif()
if(ESP_TEE_BUILD)
if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1)
list(APPEND srcs "mspi_timing_tuning/mspi_timing_tuning.c")
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY)
list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c")
endif()
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_DQS)
list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_dqs.c")
endif()
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY)
list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c")
endif()
endif()
endif()
else()
# efuse is required by esp_mspi_align.c to query the flash encryption state
set(priv_requires bootloader_support soc esp_hal_gpio esp_mm efuse)
set(requires hal esp_hal_mspi)
set(srcs "flash_brownout_hook.c" "cache_utils.c" "flash_ops.c" "spi_flash_wrap.c"
"esp_mspi_align/esp_mspi_align.c"
"mspi_mem_barrier/mspi_mem_barrier.c")
# MSPI0 Octal flash init
if(CONFIG_SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE)
list(APPEND srcs "${target}/spi_flash_oct_flash_init.c")
endif()
if(CONFIG_SPI_FLASH_HPM_ON)
list(APPEND srcs "spi_flash_hpm_enable.c")
endif()
if(CONFIG_ESP_SLEEP_SET_FLASH_DPD)
list(APPEND srcs "spi_flash_dpd_enable.c")
endif()
# MSPI timing tuning
list(APPEND srcs "mspi_timing_tuning/mspi_timing_tuning.c")
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY AND NOT CONFIG_IDF_TARGET_ESP32S3)
set(mspi_delay_file
"${CMAKE_CURRENT_LIST_DIR}/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c"
)
if(EXISTS "${mspi_delay_file}")
list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c")
endif()
endif()
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_DQS)
list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_dqs.c")
endif()
if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY)
list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c")
endif()
# MSPI intr
list(APPEND srcs "mspi_intr/mspi_intr.c")
endif()
set(include_dirs include
"mspi_timing_tuning/include"
"mspi_timing_tuning/tuning_scheme_impl/include"
"mspi_intr/include"
"esp_mspi_align/include"
"mspi_mem_barrier/include")
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND include_dirs "${target}/include")
endif()
set(ldfragments "")
if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
list(APPEND ldfragments linker.lf)
endif()
idf_component_register(SRCS "${srcs}"
REQUIRES ${requires}
PRIV_REQUIRES "${priv_requires}"
INCLUDE_DIRS ${include_dirs}
LDFRAGMENTS ${ldfragments})
idf_define_esp_err_codes(HEADERS include/spi_flash_err.h)
if(NOT non_os_build AND NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
if(CONFIG_SPIRAM)
# esp_mspi_get_io() queries esp_psram_io_get_cs_io() for the PSRAM CS pin
idf_component_optional_requires(PRIVATE esp_psram)
endif()
# Force linking init_flash_dpd ESP_SYSTEM_INIT_FN to ensure it's not discarded by linker
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_mspi_flash_ops_include_func")
endif()
idf_build_get_property(target IDF_TARGET)
if(CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING)
add_subdirectory(mspi_timing_tuning/port/${target})
endif()
components/esp_mspi/Kconfig
+85
View File
@@ -0,0 +1,85 @@
menu "MSPI Flash configuration"
depends on !APP_BUILD_TYPE_PURE_RAM_APP
menu "SPI Flash behavior when brownout"
config SPI_FLASH_BROWNOUT_RESET_XMC
bool "Enable sending reset when brownout for XMC flash chips"
default y
select SPI_FLASH_BROWNOUT_RESET
help
When this option is selected, the patch will be enabled for XMC.
Follow the recommended flow by XMC for better stability.
DO NOT DISABLE UNLESS YOU KNOW WHAT YOU ARE DOING.
config SPI_FLASH_BROWNOUT_RESET
bool
default y
select ESP_BROWNOUT_USE_INTR
help
When brownout happens during flash erase/write operations,
send reset command to stop the flash operations to improve stability.
endmenu
menu "Optional and Experimental MSPI Features (READ DOCS FIRST)"
comment "Features here require specific hardware (READ DOCS FIRST!)"
config SPI_FLASH_UNDER_HIGH_FREQ
bool
default y if ESPTOOLPY_FLASHFREQ_120M
help
This is a helper config for HPM. Invisible for users.
choice SPI_FLASH_HPM
prompt "High Performance Mode (READ DOCS FIRST, > 80MHz)"
depends on SOC_SPI_MEM_FLASH_SUPPORT_HPM && !ESPTOOLPY_OCT_FLASH
default SPI_FLASH_HPM_AUTO
help
Whether the High Performance Mode of Flash is enabled. As an optional feature, user needs to manually
enable this option as a confirmation. To be back-compatible with earlier IDF version, this option is
automatically enabled with warning when Flash running > 80Mhz.
config SPI_FLASH_HPM_ENA
# Not using name of SPI_FLASH_HPM_ENABLE because it was used as an invisible option and we don't want
# to inherit the value of that one
bool "Enable"
config SPI_FLASH_HPM_AUTO
bool "Auto (Not recommended)"
config SPI_FLASH_HPM_DIS
bool "Disabled"
endchoice
config SPI_FLASH_HPM_ON
bool
# For ESP32-S3, it's enabled by default. For later chips it should be disabled by default
default y if (IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4) && ((SPI_FLASH_HPM_ENA || SPI_FLASH_HPM_AUTO)) || \
(!IDF_TARGET_ESP32S3 && SPI_FLASH_HPM_ENA)
help
This option is invisible, and will be selected automatically
when ``ESPTOOLPY_FLASHFREQ_120M`` is selected.
choice SPI_FLASH_HPM_DC
prompt "Support HPM using DC (READ DOCS FIRST)"
depends on SPI_FLASH_HPM_ON
default SPI_FLASH_HPM_DC_AUTO
help
This feature needs your bootloader to be compiled DC-aware (BOOTLOADER_FLASH_DC_AWARE=y). Otherwise the
chip will not be able to boot after a reset.
config SPI_FLASH_HPM_DC_AUTO
bool "Auto (Enable when bootloader support enabled (BOOTLOADER_FLASH_DC_AWARE))"
config SPI_FLASH_HPM_DC_DISABLE
bool "Disable (READ DOCS FIRST)"
endchoice
config SPI_FLASH_HPM_DC_ON
bool
default y if SPI_FLASH_HPM_DC_AUTO && BOOTLOADER_FLASH_DC_AWARE
help
This is a helper config for HPM. Whether HPM-DC is enabled is also determined by bootloader.
Invisible for users.
endmenu
endmenu
components/esp_mspi/README.md
+8
View File
@@ -0,0 +1,8 @@
# `esp_mspi`
The `esp_mspi` component provides shared low-level support for flash and PSRAM connected through the MSPI peripheral.
- Coordinates flash operations, cache handling, and memory access.
- Provides MSPI timing tuning, high-performance mode, and power management support.
- Provides shared alignment and memory-barrier utilities.
- Serves as the common MSPI layer used by `spi_flash` for flash access and by `esp_psram` for external RAM support.
components/spi_flash/cache_utils.c → components/esp_mspi/cache_utils.c
-3
View File
@@ -305,7 +305,6 @@ void spi_flash_op_unlock(void)
#endif // #if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
}
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
{
spi_flash_op_lock();
@@ -350,7 +349,6 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void)
#endif // CONFIG_FREERTOS_UNICORE
void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
{
#if CONFIG_IDF_TARGET_ESP32
@@ -851,7 +849,6 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap.");
#endif
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
extern bool psram_support_wrap_size(uint32_t wrap_size);
if (!psram_support_wrap_size(spiram_wrap_size)) {
components/spi_flash/esp32s3/opi_flash_private.h → components/esp_mspi/esp32s3/include/esp_private/opi_flash_private.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
components/spi_flash/esp32s3/opi_flash_cmd_format_mxic.h → components/esp_mspi/esp32s3/opi_flash_cmd_format_mxic.h
+3 -3
View File
@@ -1,14 +1,14 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "esp_flash_chips/spi_flash_defs.h"
#include "spi_flash_defs.h"
//MXIC OPI mode needs two bytes of command - 2nd byte is the inversion of the command (1st) byte. S3 HW send LSB first
#define MXIC_CMD16(cmd8) ( (uint8_t)(cmd8) | ((uint8_t)(~(cmd8)) << 8) )
#define MXIC_CMD16(cmd8) ( (uint8_t)(cmd8) | ((uint8_t)(~(cmd8)) << 8) )
#define OPI_CMD_FORMAT_MXIC_STR() { \
.rdid = { \
components/spi_flash/esp32s3/spi_flash_oct_flash_init.c → components/esp_mspi/esp32s3/spi_flash_oct_flash_init.c
+2 -5
View File
@@ -10,7 +10,7 @@
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#include "esp_private/spi_flash_os.h"
#include "opi_flash_private.h"
#include "esp_private/opi_flash_private.h"
#include "soc/spi_mem_reg.h"
#include "soc/io_mux_reg.h"
#include "opi_flash_cmd_format_mxic.h"
@@ -31,11 +31,9 @@ const static char *TAG = "Octal Flash";
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
static uint32_t s_chip_id;
static void s_register_rom_function(void)
{
static spiflash_legacy_funcs_t rom_func =
{
static spiflash_legacy_funcs_t rom_func = {
.read_sub_len = 32,
.write_sub_len = 32,
.unlock = esp_rom_opiflash_wait_idle,
@@ -233,7 +231,6 @@ static void s_mxic_set_required_regs(uint32_t chip_id)
}
#endif
/*----------------------------------------------------------------------------------------------------
General Functions
-----------------------------------------------------------------------------------------------------*/
components/esp_hw_support/mspi/esp_mspi_align/esp_mspi_align.c → components/esp_mspi/esp_mspi_align/esp_mspi_align.c
View File
components/esp_hw_support/mspi/esp_mspi_align/include/esp_private/esp_mspi_align.h → components/esp_mspi/esp_mspi_align/include/esp_private/esp_mspi_align.h
View File
components/spi_flash/flash_brownout_hook.c → components/esp_mspi/flash_brownout_hook.c
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
components/spi_flash/flash_ops.c → components/esp_mspi/flash_ops.c
+57 -47
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,10 +9,6 @@
#include <string.h>
#include <stdio.h>
#include <sys/param.h> // For MIN/MAX(a, b)
#include <freertos/FreeRTOS.h>
#include <freertos/task.h>
#include <freertos/semphr.h>
#include <soc/soc.h>
#include <soc/soc_memory_layout.h>
#include "soc/io_mux_reg.h"
@@ -20,9 +16,9 @@
#include "sdkconfig.h"
#include "esp_attr.h"
#include "esp_cpu.h"
#include "spi_flash_mmap.h"
#include "esp_log.h"
#include "esp_private/system_internal.h"
#include "esp_private/startup_internal.h"
#include "esp_private/spi_flash_os.h"
#include "esp_private/esp_clk.h"
#include "esp_private/esp_gpio_reserve.h"
@@ -35,7 +31,7 @@
#include "soc/spi_mem_reg.h"
#include "esp32s3/rom/opi_flash.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/opi_flash_private.h"
#include "esp_private/opi_flash_private.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C2
@@ -46,10 +42,8 @@
#include "esp32c61/rom/cache.h"
#endif
#include "esp_rom_spiflash.h"
#include "esp_flash_partitions.h"
#include "esp_private/mspi_timing_tuning.h"
#include "esp_private/cache_utils.h"
#include "esp_flash.h"
#include "esp_attr.h"
#include "bootloader_flash.h"
#include "bootloader_flash_config.h"
@@ -103,28 +97,12 @@ const spi_flash_guard_funcs_t *IRAM_ATTR spi_flash_guard_get(void)
return s_flash_guard_ops;
}
#ifdef CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
#define UNSAFE_WRITE_ADDRESS abort()
#else
#define UNSAFE_WRITE_ADDRESS return false
#endif
static __attribute__((unused)) bool is_safe_write_address(size_t addr, size_t size)
{
if (!esp_partition_main_flash_region_safe(addr, size)) {
UNSAFE_WRITE_ADDRESS;
}
return true;
}
#if CONFIG_SPI_FLASH_ROM_IMPL
#include "esp_heap_caps.h"
void IRAM_ATTR *spi_flash_malloc_internal(size_t size)
{
return heap_caps_malloc(size, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
return heap_caps_malloc(size, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
}
void IRAM_ATTR spi_flash_rom_impl_init(void)
@@ -142,10 +120,19 @@ void IRAM_ATTR spi_flash_rom_impl_init(void)
}
#endif
bool IRAM_ATTR spi_flash_is_octal_mode_enabled(void)
{
#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
return efuse_ll_get_flash_type();
#else
return false;
#endif
}
void IRAM_ATTR esp_mspi_pin_init(void)
{
#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
bool octal_mspi_required = bootloader_flash_is_octal_mode_enabled();
bool octal_mspi_required = spi_flash_is_octal_mode_enabled();
#if CONFIG_SPIRAM_MODE_OCT
octal_mspi_required |= true;
#endif
@@ -164,8 +151,8 @@ void esp_mspi_pin_reserve(void)
uint8_t mspi_io;
for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
if (!bootloader_flash_is_octal_mode_enabled()
&& i >= ESP_MSPI_IO_DQS && i <= ESP_MSPI_IO_D7) {
if (!spi_flash_is_octal_mode_enabled()
&& i >= ESP_MSPI_IO_DQS && i <= ESP_MSPI_IO_D7) {
continue;
}
#endif
@@ -180,12 +167,12 @@ void esp_mspi_pin_reserve(void)
esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)
{
#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
if (bootloader_flash_is_octal_mode_enabled()) {
if (spi_flash_is_octal_mode_enabled()) {
return esp_opiflash_init(rom_spiflash_legacy_data->chip.device_id);
}
#endif
#if CONFIG_SPI_FLASH_HPM_ON
return spi_flash_enable_high_performance_mode();
return spi_flash_enable_high_performance_mode();
#endif // CONFIG_SPI_FLASH_HPM_ON
return ESP_OK;
}
@@ -193,7 +180,7 @@ esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)
void IRAM_ATTR spi_flash_set_rom_required_regs(void)
{
#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
if (bootloader_flash_is_octal_mode_enabled()) {
if (spi_flash_is_octal_mode_enabled()) {
//Disable the variable dummy mode when doing timing tuning
CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
/**
@@ -205,21 +192,6 @@ void IRAM_ATTR spi_flash_set_rom_required_regs(void)
#endif
}
#if CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM_MODE_OCT
// This function will only be called when Octal PSRAM enabled.
void IRAM_ATTR spi_flash_set_vendor_required_regs(void)
{
if (bootloader_flash_is_octal_mode_enabled()) {
esp_opiflash_set_required_regs();
SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 1, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
} else {
//Flash chip requires MSPI specifically, call this function to set them
// Set back MSPI registers after Octal PSRAM initialization.
SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 0, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
}
}
#endif
static const uint8_t s_mspi_io_num_default[] = {
MSPI_IOMUX_PIN_NUM_CLK,
MSPI_IOMUX_PIN_NUM_MISO,
@@ -323,3 +295,41 @@ esp_err_t IRAM_ATTR esp_mspi_32bit_address_flash_feature_check(void)
return ESP_OK;
}
#endif // !CONFIG_IDF_TARGET_ESP32P4 || !CONFIG_APP_BUILD_TYPE_RAM
#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
static esp_err_t dpd_enter_func(void)
{
spi_flash_ll_enter_dpd(&SPIMEM_LL_APB);
while (!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
//nop
}
return ESP_OK;
}
static esp_err_t dpd_exit_func(void)
{
spi_flash_ll_exit_dpd(&SPIMEM_LL_APB);
while (!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
//nop
}
return ESP_OK;
}
ESP_SYSTEM_INIT_FN(init_flash_dpd, CORE, BIT(0), 125)
{
// Register DPD function pointers
static spi_flash_dpd_funcs_t dpd_funcs = {
.enter_dpd = dpd_enter_func,
.exit_dpd = dpd_exit_func,
};
spi_flash_dpd_register_funcs(&dpd_funcs);
return ESP_OK;
}
#endif // CONFIG_ESP_SLEEP_SET_FLASH_DPD
void esp_mspi_flash_ops_include_func(void)
{
// Linker hook function, exists to make the linker examine this file so that
// the init_flash_dpd ESP_SYSTEM_INIT_FN above is not discarded.
}
components/spi_flash/include/esp_flash_chips/spi_flash_override.h → components/esp_mspi/include/esp_flash_chips/spi_flash_override.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

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