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https://github.com/espressif/esp-idf.git
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fix(esp_hw_support): wait pll ready before modem clock retention for s31
This commit is contained in:
wuzhenghui
BOT
@@ -6,6 +6,7 @@
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#include "esp_private/sleep_clock.h"
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#include "soc/hp_sys_clkrst_reg.h"
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#include "soc/hp_alive_sys_reg.h"
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#include "soc/pmu_reg.h"
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#include "soc/lp_peri_clkrst_reg.h"
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#include "soc/ds_reg.h"
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@@ -16,30 +17,47 @@
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ESP_LOG_ATTR_TAG(TAG, "sleep_clock");
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static esp_err_t sleep_clock_pll_source_retention_init(void *arg)
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{
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/* Modem/system clock retention restore always powers BBPLL and runs calibration here. */
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const static sleep_retention_entries_config_t pll_source_regs_retention[] = {
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/* Force BBPLL on (same effects as clk_ll_bbpll_enable) */
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[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(0), PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C, PMU_TIE_HIGH_XPD_BBPLL_M | PMU_TIE_HIGH_XPD_BBPLL_I2C_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(1), PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(2), HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN, HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(3), PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_BBPLL_I2C | PMU_HP_ACTIVE_XPD_BBPLL, PMU_HP_ACTIVE_XPD_BBPLL_I2C_M | PMU_HP_ACTIVE_XPD_BBPLL_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* Enable i2c master clock */
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[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(4), LP_PERICLKRST_I2CMST_CTRL_REG, LP_PERICLKRST_LP_I2CMST_CLK_EN, LP_PERICLKRST_LP_I2CMST_CLK_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* Start SYSPLL self-calibration */
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[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(5), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, 0, HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* Wait calibration done */
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[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PLL_LINK(6), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_BBPLL_CAL_END, HP_SYS_CLKRST_REG_BBPLL_CAL_END_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* Stop SYSPLL self-calibration */
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[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(7), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_BBPLL_CAL_STOP, HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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};
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esp_err_t err = sleep_retention_entries_create(pll_source_regs_retention, ARRAY_SIZE(pll_source_regs_retention), REGDMA_LINK_PRI_PLL_SOURCE, SLEEP_RETENTION_MODULE_PLL_SOURCE);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for PLL source retention");
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ESP_LOGI(TAG, "PLL source sleep retention initialization");
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return ESP_OK;
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}
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esp_err_t sleep_clock_system_retention_init(void *arg)
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{
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#define N_REGS_PCR() (((HP_SYS_CLKRST_CLK_EN0_REG - DR_REG_HP_SYS_CLKRST_BASE) / 4) + 1)
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const static sleep_retention_entries_config_t pcr_regs_retention[] = {
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/* Enable i2c master clock */
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[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), LP_PERICLKRST_I2CMST_CTRL_REG, LP_PERICLKRST_LP_I2CMST_CLK_EN, LP_PERICLKRST_LP_I2CMST_CLK_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* Start SYSPLL self-calibration */
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[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, 0, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* Wait calibration done */
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[2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(2), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* Stop SYSPLL self-calibration */
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[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* Clock configuration retention */
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[4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR() - 1, 0, 0,
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR() - 1, 0, 0,
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0xffbfffff, 0xffffffff, 0xffffffff, 0x7fffffff), .owner = ENTRY(0) | ENTRY(1)},
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[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(2), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[4] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(4), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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/* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */
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[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[11] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(11), HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_CRYPTO_CTRL0_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1)},
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[5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(5), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)},
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[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_CRYPTO_CTRL0_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1)},
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};
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esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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@@ -56,13 +74,11 @@ esp_err_t sleep_clock_modem_retention_init(void *arg)
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#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
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#define N_REGS_LPCON() (((MODEM_LPCON_MODEM_INTR_STATUS_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1)
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const static sleep_retention_entries_config_t modem_regs_retention[] = {
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/* Workaround: on the restore path, issue a dummy write (value 0xf) to
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* MODEM_SYSCON_DATE_REG (a benign date/version register) as the first
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* REGDMA node to avoid an APB access timeout during the subsequent
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* REGDMA operations. This is a hardware issue workaround; whether it
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* can be removed on a future chip revision is still TODO/to be
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* confirmed, so do not delete this node without verifying. */
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[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_DATE_REG, 0xf, 0xffffffff, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
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/* !!! pll_source_regs_retention link above does not above guarantee that the PMU has released the clock gate for the PLL.
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* And due to hardware limitations, REGDMA is also unable to obtain the PMU's PLL gate status when the chip is in PD_TOP mode.
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* So WORKAROUND with issue a dummy write to MODEM_SYSCON_DATE_REG as the first REGDMA node to avoid an APB access timeout
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* during the subsequent REGDMA operations. */
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[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_DATE_REG, MODEM_SYSCON_DATE, MODEM_SYSCON_DATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
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[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(1), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
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[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
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[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(0), HP_SYS_CLKRST_REF_160M_CTRL0_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN, HP_SYS_CLKRST_REG_REF_160M_CLK_EN_M, 1, 0), .owner = ENTRY(1)},
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@@ -108,12 +124,14 @@ bool clock_domain_pd_allowed(void)
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sleep_retention_module_bitmap_t mask = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } };
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const sleep_retention_module_bitmap_t system_modules = sleep_retention_module_bitmap_and(inited_modules, sys_clk_dep_modules);
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if (!sleep_retention_module_bitmap_eq(system_modules, null_module)) {
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mask.bitmap[SLEEP_RETENTION_MODULE_PLL_SOURCE >> 5] |= BIT(SLEEP_RETENTION_MODULE_PLL_SOURCE % 32);
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mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_SYSTEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM % 32);
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}
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#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
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const sleep_retention_module_bitmap_t modem_modules = sleep_retention_module_bitmap_and(inited_modules, modem_clk_dep_modules);
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if (!sleep_retention_module_bitmap_eq(modem_modules, null_module)) {
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mask.bitmap[SLEEP_RETENTION_MODULE_PLL_SOURCE >> 5] |= BIT(SLEEP_RETENTION_MODULE_PLL_SOURCE % 32);
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mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32);
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}
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#endif
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@@ -129,7 +147,14 @@ bool clock_domain_pd_allowed(void)
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ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
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{
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sleep_retention_module_init_param_t init_param = {
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.cbs = { .create = { .handle = sleep_clock_pll_source_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_PLL_SOURCE, &init_param);
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init_param = (sleep_retention_module_init_param_t) {
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.cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
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.depends = RETENTION_MODULE_BITMAP_INIT(PLL_SOURCE),
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
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@@ -137,6 +162,7 @@ ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
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#if CONFIG_MAC_BB_PD || CONFIG_BT_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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init_param = (sleep_retention_module_init_param_t) {
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.cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
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.depends = RETENTION_MODULE_BITMAP_INIT(PLL_SOURCE),
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
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@@ -243,68 +243,6 @@ static int16_t s_root_pll_power_ref_cnt[SOC_ROOT_CIRCUIT_CLK_MAX] = { 0 };
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static bool s_clk_tree_initialized = false;
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static int16_t esp_clk_tree_root_pll_power_acquire(soc_root_clk_circuit_t clk_circuit)
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{
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int16_t prev;
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assert(clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL || clk_circuit == SOC_ROOT_CIRCUIT_CLK_CPLL
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|| clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2);
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esp_os_enter_critical(&s_clk_tree_spinlock);
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prev = s_root_pll_power_ref_cnt[clk_circuit]++;
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if (prev == 0) {
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switch (clk_circuit) {
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case SOC_ROOT_CIRCUIT_CLK_BBPLL:
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clk_ll_bbpll_enable();
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break;
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case SOC_ROOT_CIRCUIT_CLK_CPLL:
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clk_ll_cpll_enable();
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break;
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case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
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clk_ll_xtalx2_enable();
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break;
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default:
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break;
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}
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}
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esp_os_exit_critical(&s_clk_tree_spinlock);
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return prev;
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}
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static int16_t esp_clk_tree_root_pll_power_release(soc_root_clk_circuit_t clk_circuit)
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{
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int16_t prev;
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assert(clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL || clk_circuit == SOC_ROOT_CIRCUIT_CLK_CPLL
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|| clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2);
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esp_os_enter_critical(&s_clk_tree_spinlock);
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prev = s_root_pll_power_ref_cnt[clk_circuit];
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if (prev <= 0) {
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esp_os_exit_critical(&s_clk_tree_spinlock);
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ESP_EARLY_LOGW(TAG, "soc_root_clk_circuit_t %d disabled multiple times!!", clk_circuit);
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return prev;
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}
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s_root_pll_power_ref_cnt[clk_circuit] = prev - 1;
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if (prev == 1) {
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switch (clk_circuit) {
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case SOC_ROOT_CIRCUIT_CLK_BBPLL:
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clk_ll_bbpll_disable();
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break;
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case SOC_ROOT_CIRCUIT_CLK_CPLL:
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clk_ll_cpll_disable();
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break;
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case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
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clk_ll_xtalx2_disable();
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break;
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default:
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break;
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}
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}
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esp_os_exit_critical(&s_clk_tree_spinlock);
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return prev;
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}
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static uint32_t esp_clk_tree_ref_500m_pll_get_freq_hz(uint32_t div_num)
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{
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uint32_t up_hz;
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@@ -476,25 +414,41 @@ void esp_clk_tree_initialize(void)
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bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
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{
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if (clk_circuit >= SOC_ROOT_CIRCUIT_CLK_MAX) {
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if (clk_circuit != SOC_ROOT_CIRCUIT_CLK_BBPLL
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&& clk_circuit != SOC_ROOT_CIRCUIT_CLK_CPLL
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&& clk_circuit != SOC_ROOT_CIRCUIT_CLK_XTAL_X2) {
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return false;
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}
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bool toggled = false;
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switch (clk_circuit) {
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case SOC_ROOT_CIRCUIT_CLK_CPLL:
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case SOC_ROOT_CIRCUIT_CLK_BBPLL:
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case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: {
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if (enable) {
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toggled = (esp_clk_tree_root_pll_power_acquire(clk_circuit) == 0);
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} else {
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toggled = (esp_clk_tree_root_pll_power_release(clk_circuit) == 1);
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esp_os_enter_critical(&s_clk_tree_spinlock);
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if (enable) {
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s_root_pll_power_ref_cnt[clk_circuit]++;
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} else if (s_root_pll_power_ref_cnt[clk_circuit] <= 0) {
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esp_os_exit_critical(&s_clk_tree_spinlock);
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ESP_EARLY_LOGW(TAG, "soc_root_clk_circuit_t %d disabled multiple times!!", clk_circuit);
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return false;
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}
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if (s_root_pll_power_ref_cnt[clk_circuit] == 1) {
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switch (clk_circuit) {
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case SOC_ROOT_CIRCUIT_CLK_BBPLL:
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enable ? clk_ll_bbpll_enable() : clk_ll_bbpll_disable();
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break;
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case SOC_ROOT_CIRCUIT_CLK_CPLL:
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enable ? clk_ll_cpll_enable() : clk_ll_cpll_disable();
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break;
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||||
case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
|
||||
enable ? clk_ll_xtalx2_enable() : clk_ll_xtalx2_disable();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
toggled = true;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
if (!enable) {
|
||||
s_root_pll_power_ref_cnt[clk_circuit]--;
|
||||
}
|
||||
esp_os_exit_critical(&s_clk_tree_spinlock);
|
||||
return toggled;
|
||||
}
|
||||
|
||||
|
||||
@@ -15,76 +15,78 @@ extern "C" {
|
||||
typedef enum periph_retention_module {
|
||||
SLEEP_RETENTION_MODULE_MIN = 0,
|
||||
SLEEP_RETENTION_MODULE_NULL = 1, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */
|
||||
/* PLL source (I2C master clock + SYSPLL self-calibration) */
|
||||
SLEEP_RETENTION_MODULE_PLL_SOURCE = 2,
|
||||
/* clock module, which includes system and modem */
|
||||
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 2,
|
||||
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 3,
|
||||
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
|
||||
* TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
|
||||
SLEEP_RETENTION_MODULE_SYS_PERIPH = 3,
|
||||
SLEEP_RETENTION_MODULE_SYS_PERIPH = 4,
|
||||
/* Timer Group by target*/
|
||||
SLEEP_RETENTION_MODULE_TG0_WDT = 4,
|
||||
SLEEP_RETENTION_MODULE_TG1_WDT = 5,
|
||||
SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6,
|
||||
SLEEP_RETENTION_MODULE_TG0_TIMER1 = 7,
|
||||
SLEEP_RETENTION_MODULE_TG1_TIMER0 = 8,
|
||||
SLEEP_RETENTION_MODULE_TG1_TIMER1 = 9,
|
||||
SLEEP_RETENTION_MODULE_TG0_WDT = 5,
|
||||
SLEEP_RETENTION_MODULE_TG1_WDT = 6,
|
||||
SLEEP_RETENTION_MODULE_TG0_TIMER0 = 7,
|
||||
SLEEP_RETENTION_MODULE_TG0_TIMER1 = 8,
|
||||
SLEEP_RETENTION_MODULE_TG1_TIMER0 = 9,
|
||||
SLEEP_RETENTION_MODULE_TG1_TIMER1 = 10,
|
||||
|
||||
/* AHB_DMA by channel */
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 10,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 11,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 12,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH3 = 13,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH4 = 14,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 11,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 12,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 13,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH3 = 14,
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH4 = 15,
|
||||
/* AXI_DMA by channel */
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 15,
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 16,
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 17,
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 16,
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 17,
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 18,
|
||||
/* LP_AHB_DMA by channel */
|
||||
SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0 = 18,
|
||||
SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1 = 19,
|
||||
SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0 = 19,
|
||||
SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1 = 20,
|
||||
/* MISC Peripherals */
|
||||
SLEEP_RETENTION_MODULE_UART0 = 20,
|
||||
SLEEP_RETENTION_MODULE_UART1 = 21,
|
||||
SLEEP_RETENTION_MODULE_UART2 = 22,
|
||||
SLEEP_RETENTION_MODULE_UART3 = 23,
|
||||
SLEEP_RETENTION_MODULE_RMT0 = 24,
|
||||
SLEEP_RETENTION_MODULE_I2S0 = 25,
|
||||
SLEEP_RETENTION_MODULE_I2S1 = 26,
|
||||
SLEEP_RETENTION_MODULE_I2C0 = 27,
|
||||
SLEEP_RETENTION_MODULE_I2C1 = 28,
|
||||
SLEEP_RETENTION_MODULE_ETM0 = 29,
|
||||
SLEEP_RETENTION_MODULE_TWAI0 = 30,
|
||||
SLEEP_RETENTION_MODULE_TWAI1 = 31,
|
||||
SLEEP_RETENTION_MODULE_PARLIO0 = 32,
|
||||
SLEEP_RETENTION_MODULE_GPSPI2 = 33,
|
||||
SLEEP_RETENTION_MODULE_GPSPI3 = 34,
|
||||
SLEEP_RETENTION_MODULE_LEDC0 = 35,
|
||||
SLEEP_RETENTION_MODULE_LEDC1 = 36,
|
||||
SLEEP_RETENTION_MODULE_MCPWM0 = 37,
|
||||
SLEEP_RETENTION_MODULE_MCPWM1 = 38,
|
||||
SLEEP_RETENTION_MODULE_MCPWM2 = 39,
|
||||
SLEEP_RETENTION_MODULE_MCPWM3 = 40,
|
||||
SLEEP_RETENTION_MODULE_SDM0 = 41,
|
||||
SLEEP_RETENTION_MODULE_LCDCAM = 42,
|
||||
SLEEP_RETENTION_MODULE_JPEG = 43,
|
||||
SLEEP_RETENTION_MODULE_DMA2D = 44,
|
||||
SLEEP_RETENTION_MODULE_PPA = 45,
|
||||
SLEEP_RETENTION_MODULE_UART0 = 21,
|
||||
SLEEP_RETENTION_MODULE_UART1 = 22,
|
||||
SLEEP_RETENTION_MODULE_UART2 = 23,
|
||||
SLEEP_RETENTION_MODULE_UART3 = 24,
|
||||
SLEEP_RETENTION_MODULE_RMT0 = 25,
|
||||
SLEEP_RETENTION_MODULE_I2S0 = 26,
|
||||
SLEEP_RETENTION_MODULE_I2S1 = 27,
|
||||
SLEEP_RETENTION_MODULE_I2C0 = 28,
|
||||
SLEEP_RETENTION_MODULE_I2C1 = 29,
|
||||
SLEEP_RETENTION_MODULE_ETM0 = 30,
|
||||
SLEEP_RETENTION_MODULE_TWAI0 = 31,
|
||||
SLEEP_RETENTION_MODULE_TWAI1 = 32,
|
||||
SLEEP_RETENTION_MODULE_PARLIO0 = 33,
|
||||
SLEEP_RETENTION_MODULE_GPSPI2 = 34,
|
||||
SLEEP_RETENTION_MODULE_GPSPI3 = 35,
|
||||
SLEEP_RETENTION_MODULE_LEDC0 = 36,
|
||||
SLEEP_RETENTION_MODULE_LEDC1 = 37,
|
||||
SLEEP_RETENTION_MODULE_MCPWM0 = 38,
|
||||
SLEEP_RETENTION_MODULE_MCPWM1 = 39,
|
||||
SLEEP_RETENTION_MODULE_MCPWM2 = 40,
|
||||
SLEEP_RETENTION_MODULE_MCPWM3 = 41,
|
||||
SLEEP_RETENTION_MODULE_SDM0 = 42,
|
||||
SLEEP_RETENTION_MODULE_LCDCAM = 43,
|
||||
SLEEP_RETENTION_MODULE_JPEG = 44,
|
||||
SLEEP_RETENTION_MODULE_DMA2D = 45,
|
||||
SLEEP_RETENTION_MODULE_PPA = 46,
|
||||
|
||||
/* Modem module, which includes WiFi, BLE and 802.15.4 */
|
||||
SLEEP_RETENTION_MODULE_WIFI_MAC = 46,
|
||||
SLEEP_RETENTION_MODULE_WIFI_BB = 47,
|
||||
SLEEP_RETENTION_MODULE_BLE_MAC = 48,
|
||||
SLEEP_RETENTION_MODULE_BT_BB = 49,
|
||||
SLEEP_RETENTION_MODULE_802154_MAC = 50,
|
||||
SLEEP_RETENTION_MODULE_CLOCK_MODEM = 51,
|
||||
SLEEP_RETENTION_MODULE_MODEM_PHY = 52,
|
||||
SLEEP_RETENTION_MODULE_PHY_FE = 53,
|
||||
SLEEP_RETENTION_MODULE_WIFI_MAC = 47,
|
||||
SLEEP_RETENTION_MODULE_WIFI_BB = 48,
|
||||
SLEEP_RETENTION_MODULE_BLE_MAC = 49,
|
||||
SLEEP_RETENTION_MODULE_BT_BB = 50,
|
||||
SLEEP_RETENTION_MODULE_802154_MAC = 51,
|
||||
SLEEP_RETENTION_MODULE_CLOCK_MODEM = 52,
|
||||
SLEEP_RETENTION_MODULE_MODEM_PHY = 53,
|
||||
SLEEP_RETENTION_MODULE_PHY_FE = 54,
|
||||
|
||||
SLEEP_RETENTION_MODULE_ASRC = 53,
|
||||
SLEEP_RETENTION_MODULE_ASRC = 55,
|
||||
|
||||
SLEEP_RETENTION_MODULE_MAX,
|
||||
} periph_retention_module_t;
|
||||
|
||||
#define is_top_domain_module(m) ((m >= SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) && ((m <= SLEEP_RETENTION_MODULE_PPA)))
|
||||
#define is_top_domain_module(m) ((m >= SLEEP_RETENTION_MODULE_PLL_SOURCE) && ((m <= SLEEP_RETENTION_MODULE_PPA)))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -37,6 +37,7 @@ extern "C" {
|
||||
#define REGDMA_MODEMLPCON_LINK(_pri) ((0x03 << 8) | _pri)
|
||||
#define REGDMA_PAU_LINK(_pri) ((0x04 << 8) | _pri)
|
||||
#define REGDMA_PVT_LINK(_pri) ((0x05 << 8) | _pri)
|
||||
#define REGDMA_PLL_LINK(_pri) ((0x06 << 8) | _pri)
|
||||
|
||||
#define REGDMA_CACHE_LINK(_pri) ((0x0c << 8) | _pri)
|
||||
#define REGDMA_INTMTX_LINK(_pri) ((0x0d << 8) | _pri)
|
||||
@@ -79,9 +80,10 @@ extern "C" {
|
||||
|
||||
#define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri)
|
||||
|
||||
#define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_0
|
||||
#define REGDMA_LINK_PRI_MODEM_CLK REGDMA_LINK_PRI_1
|
||||
#define REGDMA_LINK_PRI_CLOCK_ICG REGDMA_LINK_PRI_1
|
||||
#define REGDMA_LINK_PRI_PLL_SOURCE REGDMA_LINK_PRI_0
|
||||
#define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_1
|
||||
#define REGDMA_LINK_PRI_MODEM_CLK REGDMA_LINK_PRI_2
|
||||
#define REGDMA_LINK_PRI_CLOCK_ICG REGDMA_LINK_PRI_2
|
||||
#define REGDMA_LINK_PRI_CRITICAL_TEE_APM REGDMA_LINK_PRI_2
|
||||
#define REGDMA_LINK_PRI_WIFI_MAC_BB REGDMA_LINK_PRI_3
|
||||
#define REGDMA_LINK_PRI_NON_CRITICAL_TEE_APM REGDMA_LINK_PRI_4
|
||||
|
||||
Reference in New Issue
Block a user