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1bbd9ee09a3cd57204dfd4b8cbc063df079db5a1
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431 Commits
Author SHA1 Message Date
Tomas Rezucha 1bbd9ee09a refactor(console): Use esp_hal_usb APIs in USB console 
Also remove unused usb_reg.h and usb_struct.h

Closes https://github.com/espressif/esp-idf/issues/12710
Preparation for https://github.com/espressif/esp-idf/issues/18992
 2026-09-10 14:30:18 +08:00
Marius Vikhammer f5e06de75f Merge branch 'bugfix/h4_touch_caps' into 'master' 
fix(soc): use standard touch wakeup cap name on ESP32-H4

See merge request espressif/esp-idf!52093
 2026-09-09 20:43:42 +08:00
Mahavir Jain 84a6967aa1 Merge branch 'feat/add_sm3_hash_support_and_testcases' into 'master' 
add SM3 hash support and testcases

See merge request espressif/esp-idf!44830
 2026-09-08 09:02:41 +05:30
morris df2192b38f Merge branch 'trace_encoder_hw_params' into 'master' 
Trace encoder hw params

See merge request espressif/esp-idf!52338
 2026-09-04 13:42:31 +08:00
nilesh.kale 7f413c914d feat(sha): add SM3 hardware support 
Enable hardware SM3 digest support on ESP32-H4, ESP32-S31 and ESP32-C5
via the SHA peripheral (mode 14).
 2026-09-04 11:24:39 +08:00
Jiang Jiang Jian 4b2669edde Merge branch 'feat/pm_components_ram_optimize' into 'master' 
feat(pm): pm components ram optimize

Closes PM-840

See merge request espressif/esp-idf!51672
 2026-09-04 10:32:26 +08:00
Erhan KurubasandCursor 5b4a90da6e feat(soc): Add RISC-V trace ecause width and packet format caps 
Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-03 08:20:11 +02:00
Mahavir Jain a3192567d5 Merge branch 'feat/cpu_region_protection_h4' into 'master' 
Memory region protection for ESP32-H4

Closes IDF-12588

See merge request espressif/esp-idf!47070
 2026-08-31 17:41:52 +05:30
wuzhenghui 11c590c053 change(esp_hw_support): optimize retention driver RAM cost 2026-08-31 15:26:18 +08:00
Marius Vikhammer 01582e0f12 fix(soc): use standard touch wakeup cap name on ESP32-H4 
The H4-only spelling was unread, so touch wakeup never compiled in.
 2026-08-26 16:43:53 +08:00
harshal.patil a7f4dbf35a fix(soc): make SOC_RAM_ICACHE1_HIGH an exclusive bound on ESP32-H4 
Every other SOC_*_HIGH macro in soc.h is an exclusive region end;
SOC_RAM_ICACHE1_HIGH was the inclusive last byte (0x40867fff). This
also made the reclaimed ICache1 heap region in single core mode
(components/heap/port/esp32h4/memory_layout.c, sized as HIGH - LOW)
one byte short. Change the value to the exclusive end 0x40868000 and
drop the +1 compensation at the SOC_HP_RAM_HIGH definition.
 2026-08-25 10:40:28 +05:30
harshal.patil 07debe6edc feat(esp_hw_support): Memory region protection for ESP32-H4 2026-08-25 10:40:28 +05:30
morris cd356d592d refactor(adc): move channel count to adc LL 2026-08-25 12:30:52 +08:00
wanckl 4cf27f5e88 fix(driver_spi): ci enable h4 generic test 2026-08-21 19:39:57 +08:00
hebinglin 27fe024e30 fix(esp_hw_support): pmu_icg_mapping define mistake 2026-08-20 17:23:26 +08:00
Erhan Kurubas cde1da8fe6 feat(riscv_trace): add trace support for ESP32-H4 2026-08-11 13:06:45 +02:00
He Binglin dce537e00e Merge branch 'feat/esp_idf_h4_retention_clk_icg' into 'master' 
feat(esp_hw_support): refactor PMU sleep icg and support retention ICG

See merge request espressif/esp-idf!48915
 2026-07-31 10:35:19 +08:00
Wang Meng Yang 5203199852 Merge branch 'docs/update_coexist_docs' into 'master' 
docs(coex): enable coexist docs for c61 h21 h4 s31

See merge request espressif/esp-idf!51105
 2026-07-29 20:14:35 +08:00
hebinglin 57daf0a8f7 feat(esp_hw_support): add backup clk icg support 2026-07-29 17:09:34 +08:00
hebinglin a4889bd73d change(esp_hw_support): refactor pmu/esp_sleep param struct 2026-07-29 15:23:09 +08:00
Erhan Kurubas e21ab7e724 feat(system): add OCD stub bin support for more targets 
Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4,
esp32h21, esp32p4, and esp32s31. Update TEE linker scripts with
correct esp_tee_app_config offsets for the 0x3000 stub reservation
 2026-07-28 08:34:02 +03:00
linruihao 52c9ff43f7 docs(coex): enable coexist docs for c61 h21 h4 s31 2026-07-23 17:18:07 +08:00
cjin 9c432f41b5 feat(modem_clock): added bt_apb module and separete bt_apb from bt_mac module 2026-07-20 10:48:26 +08:00
Ma Jing Jing 93b5dc8eba feat(asrc): Add sleep retention 2026-07-16 19:56:17 +08:00
hebinglin 7d6c54996a feat(esp_hw_support): support esp32h4 esp32s31 bus hw low power 2026-07-14 18:14:07 +08:00
muhaidong e7b8677fa2 fix(coex): remove unsupported external coex soc caps 2026-06-24 13:56:22 +08:00
wuzhenghui 61be47b739 feat(esp_hw_support): support PMU clock ICG management for esp32s31 2026-06-17 11:34:37 +08:00
wuzhenghui f2d3448fa2 refactor(esp_hw_support): move system_periph_retention from soc to esp_hw_support 2026-06-15 17:09:58 +08:00
Aditya Patwardhan ebc4806085 Merge branch 'fix/disable_secure_boot_v2_ecdsa' into 'master' 
Fix/disable secure boot v2 ecdsa

See merge request espressif/esp-idf!48834
 2026-06-09 23:46:11 +05:30
Aditya Patwardhan 67e10e2b56 change(secure_boot): mark ECDSA based Secure Boot V2 as insecure on affected SoCs 
ECDSA based Secure Boot V2 is not functional for certain input vectors on
ESP32-C5/C61/H2/P4 and on the preview targets ESP32-H4/H21. RSA based Secure
Boot V2 is the recommended scheme where the SoC supports it. This issue will be
fixed in a future hardware ECO revision; more details will be shared through the
hardware errata document.

A new hidden Kconfig option SECURE_BOOT_V2_ECDSA_INSECURE marks the affected
mass-production SoCs (ESP32-C5/C61/H2/P4). On these SoCs, when hardware Secure
Boot V2 is enabled, the ECDSA (V2) signing scheme is no longer offered by
default; it must be turned on explicitly via SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
under "Allow potentially insecure options" (CONFIG_SECURE_BOOT_INSECURE). App
signing without hardware Secure Boot is not affected. Note that ESP32-C61 has no
RSA based Secure Boot V2, so it has no Secure Boot scheme enabled by default.

The preview targets ESP32-H4 and ESP32-H21 mark ECDSA Secure Boot V2 as not
supported in their SoC capabilities instead of using the option above. As
ESP32-H4 has no other Secure Boot V2 scheme, Secure Boot is disabled entirely on
it; ESP32-H21 retains RSA based Secure Boot V2.

The security documentation keeps the ECDSA Secure Boot V2 content visible and
adds a warning describing the limitation (including that ECDSA Secure Boot V2 on
ESP32-C61 is not recommended for production). CI apps that exercise ECDSA Secure
Boot V2 on the affected SoCs set CONFIG_SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
accordingly.
 2026-06-09 16:55:57 +05:30
Song Ruo Jing f6449f926b fix(spi_flash): gpspi flash clock could reach higher frequency 2026-06-08 17:56:17 +08:00
Song Ruo Jing 545b31e6b9 feat(spi_flash): Add exclusive support for ESP32H4 
Add 32bit addr support for esp32s31 as well
 2026-06-08 17:56:09 +08:00
C.S.M 2acd9b9a7c fix(spi_flash): Fix suspend issue on esp32s31, and add trs timing on other target 2026-06-08 11:15:13 +08:00
gaoxu 7dfc685010 refactor(adc): move some ADC soc_caps to adc_ll.h 2026-06-01 19:05:33 +08:00
C.S.M b2784ccc39 Merge branch 'feat/tsens_slp_esp32h4' into 'master' 
feat(temperature_sensor): Add temperature sensor sleep retention support on esp32h4

Closes IDF-12405, IDF-15617, and IDF-15648

See merge request espressif/esp-idf!48703
 2026-05-29 16:37:52 +08:00
C.S.M 38ce3f6e18 feat(temperature_sensor): Add temperature sensor sleep retention support on esp32h4 2026-05-27 16:16:31 +08:00
Gao Xu db3d01d412 Merge branch 'feat/basic_rng_support_h4' into 'master' 
RNG support and refactor on ESP32-H4

Closes IDF-12265

See merge request espressif/esp-idf!45361
 2026-05-27 11:14:38 +08:00
gaoxu 43317018d1 refactor(rng): use adc_ll apis for ESP32-h4 and refactor rng_ll_enable/disable 2026-05-26 19:02:41 +08:00
He Binglin f3ee69582e Merge branch 'change/esp_idf_h4h21_modem_clock_retention_passive' into 'master' 
Change/esp idf h4h21 modem clock retention passive

Closes IDFCI-11613, IDFCI-11628, and IDFCI-11614

See merge request espressif/esp-idf!48557
 2026-05-22 18:02:24 +08:00
hebinglin 23f6b5985a change(esp_hw_support): disable flash pd in h4 h21 c5 c61 2026-05-22 12:30:44 +08:00
hebinglin 64bf345683 revert(esp_hw_support): esp32h4 beta5 i2c config retention when pd modem refer to PM-487 2026-05-22 11:09:33 +08:00
hebinglin 1c279178fa feat(esp_hw_support): support bbpll pd in modem state 2026-05-21 20:03:45 +08:00
hebinglin 5710783a89 feat(esp_hw_support): support entry 2 xtalx2 power pu in esp32h4 2026-05-21 19:55:37 +08:00
hebinglin 312076e955 feat(esp_hw_support): decrease retention current and duration 2026-05-21 19:53:51 +08:00
morris 2b9b065c82 feat(ana_cmpr): enable ana_cmpr driver support on esp32h4 2026-05-21 10:30:43 +08:00
Wu Zheng Hui 91e66a8d19 Merge branch 'feat/support_io_edge_wakeup' into 'master' 
feat(esp_hw_support): support rtc io edge wakeup sleep

Closes FCS-1880 and IDF-11812

See merge request espressif/esp-idf!48410
 2026-05-20 19:37:35 +08:00
Nilesh Kale 2fa9fba978 Merge branch 'feat/add_flash_encryption_support_for_esp32h4' into 'master' 
feat: enable flash encryption support in ESP32H4

Closes IDF-12261, IDF-12969, and IDF-12506

See merge request espressif/esp-idf!45613
 2026-05-20 17:45:13 +08:00
Aditya PatwardhanandNilesh Kale e1d429ba30 feat(hal): add ECDSA low-level driver for esp32s31 
Co-authored-by: Nilesh Kale <nilesh.kale@espressif.com>
 2026-05-20 10:17:34 +05:30
nilesh.kale 36fdf38ad4 fix: cleanup xts_aes_reg.h dependency for H21, C61 and H4 2026-05-20 09:29:20 +05:30
nilesh.kale cae147af08 feat: enable flash encryption for ESP32-H4 2026-05-20 09:29:20 +05:30