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refactor(console): Use esp_hal_usb APIs in USB console

Browse Source 
Also remove unused usb_reg.h and usb_struct.h

Closes https://github.com/espressif/esp-idf/issues/12710
Preparation for https://github.com/espressif/esp-idf/issues/18992
This commit is contained in:
Tomas Rezucha
2026-08-18 12:19:03 +02:00
committed by BOT
parent a7cb4cc709
commit 1bbd9ee09a
12 changed files with 74 additions and 21299 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h
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@@ -319,6 +319,17 @@ static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t in
hw->gintsts_reg.val = intr_msk;
}
/**
* @brief Reads the pending interrupts, i.e. those which are both asserted and unmasked
*
* @param hw Start address of the DWC_OTG registers
* @return uint32_t Mask of pending interrupts
*/
static inline uint32_t usb_dwc_ll_gintsts_read_pending_intrs(usb_dwc_dev_t *hw)
{
return hw->gintsts_reg.val & hw->gintmsk_reg.val;
}
// --------------------------- GINTMSK Register --------------------------------
static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)

11
components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h
View File

@@ -337,6 +337,17 @@ static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t in
hw->gintsts_reg.val = intr_msk;
}
/**
* @brief Reads the pending interrupts, i.e. those which are both asserted and unmasked
*
* @param hw Start address of the DWC_OTG registers
* @return uint32_t Mask of pending interrupts
*/
static inline uint32_t usb_dwc_ll_gintsts_read_pending_intrs(usb_dwc_dev_t *hw)
{
return hw->gintsts_reg.val & hw->gintmsk_reg.val;
}
// --------------------------- GINTMSK Register --------------------------------
static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)

11
components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h
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@@ -317,6 +317,17 @@ static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t in
hw->gintsts_reg.val = intr_msk;
}
/**
* @brief Reads the pending interrupts, i.e. those which are both asserted and unmasked
*
* @param hw Start address of the DWC_OTG registers
* @return uint32_t Mask of pending interrupts
*/
static inline uint32_t usb_dwc_ll_gintsts_read_pending_intrs(usb_dwc_dev_t *hw)
{
return hw->gintsts_reg.val & hw->gintmsk_reg.val;
}
// --------------------------- GINTMSK Register --------------------------------
static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)

11
components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h
View File

@@ -317,6 +317,17 @@ static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t in
hw->gintsts_reg.val = intr_msk;
}
/**
* @brief Reads the pending interrupts, i.e. those which are both asserted and unmasked
*
* @param hw Start address of the DWC_OTG registers
* @return uint32_t Mask of pending interrupts
*/
static inline uint32_t usb_dwc_ll_gintsts_read_pending_intrs(usb_dwc_dev_t *hw)
{
return hw->gintsts_reg.val & hw->gintmsk_reg.val;
}
// --------------------------- GINTMSK Register --------------------------------
static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)

11
components/esp_hal_usb/esp32s31/include/hal/usb_dwc_ll.h
View File

@@ -326,6 +326,17 @@ static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t in
hw->gintsts_reg.val = intr_msk;
}
/**
* @brief Reads the pending interrupts, i.e. those which are both asserted and unmasked
*
* @param hw Start address of the DWC_OTG registers
* @return uint32_t Mask of pending interrupts
*/
static inline uint32_t usb_dwc_ll_gintsts_read_pending_intrs(usb_dwc_dev_t *hw)
{
return hw->gintsts_reg.val & hw->gintmsk_reg.val;
}
// --------------------------- GINTMSK Register --------------------------------
static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)

2
components/esp_usb_cdc_rom_console/CMakeLists.txt
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@@ -8,7 +8,7 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS include
PRIV_REQUIRES esp_timer
PRIV_REQUIRES esp_timer esp_hal_usb
LDFRAGMENTS linker.lf
)

42
components/esp_usb_cdc_rom_console/usb_console.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,36 +20,28 @@
#include "esp_private/usb_console.h"
#include "esp_private/system_internal.h"
#include "esp_private/startup_internal.h"
#include "soc/periph_defs.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/usb_struct.h"
#include "soc/usb_reg.h"
#include "soc/usb_periph.h"
#include "hal/soc_hal.h"
#include "hal/usb_dwc_ll.h"
#include "esp_rom_serial_output.h"
#include "esp_rom_sys.h"
#include "esp_rom_caps.h"
#ifdef CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/usb/usb_dc.h"
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_dfu.h"
#include "esp32s2/rom/usb/usb_device.h"
#include "esp32s2/rom/usb/usb_os_glue.h"
#include "esp32s2/rom/usb/usb_persist.h"
#include "esp32s2/rom/usb/chip_usb_dw_wrapper.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/usb/usb_dc.h"
#include "esp32s3/rom/usb/cdc_acm.h"
#include "esp32s3/rom/usb/usb_dfu.h"
#include "esp32s3/rom/usb/usb_device.h"
#include "esp32s3/rom/usb/usb_os_glue.h"
#include "esp32s3/rom/usb/usb_persist.h"
#include "esp32s3/rom/usb/chip_usb_dw_wrapper.h"
#endif
#include "rom/usb/usb_dc.h"
#include "rom/usb/cdc_acm.h"
#include "rom/usb/usb_dfu.h"
#include "rom/usb/usb_device.h"
#include "rom/usb/usb_os_glue.h"
#include "rom/usb/usb_persist.h"
#include "rom/usb/chip_usb_dw_wrapper.h"
#include "esp_private/esp_vfs_cdcacm_select.h"
#define CDC_WORK_BUF_SIZE (ESP_ROM_CDC_ACM_WORK_BUF_MIN + CONFIG_ESP_CONSOLE_USB_CDC_RX_BUF_SIZE)
/* The ROM CDC ACM driver only ever drives the first USB-DWC controller */
#define USB_CONSOLE_DWC_CTRL_IDX 0
typedef enum {
REBOOT_NONE,
REBOOT_NORMAL,
@@ -241,7 +233,8 @@ void esp_usb_console_on_restart_timeout(void *arg)
void esp_usb_console_poll_interrupts(void)
{
const int max_poll_count = 10;
for (int i = 0; (USB0.gintsts & USB0.gintmsk) != 0 && i < max_poll_count; i++) {
usb_dwc_dev_t *hw = USB_DWC_LL_GET_HW(USB_CONSOLE_DWC_CTRL_IDX);
for (int i = 0; usb_dwc_ll_gintsts_read_pending_intrs(hw) != 0 && i < max_poll_count; i++) {
usb_dc_check_poll_for_interrupts();
}
}
@@ -301,7 +294,8 @@ esp_err_t esp_usb_console_init(void)
* Since the handler function is in IRAM, we can register the interrupt as IRAM capable.
* It is not because we actually need the interrupt to work with cache disabled!
*/
err = esp_intr_alloc(ETS_USB_INTR_SOURCE, ISR_FLAG | ESP_INTR_FLAG_INTRDISABLED,
err = esp_intr_alloc(usb_dwc_info.controllers[USB_CONSOLE_DWC_CTRL_IDX].irq,
ISR_FLAG | ESP_INTR_FLAG_INTRDISABLED,
esp_usb_console_interrupt, NULL, &s_usb_int_handle);
if (err != ESP_OK) {
esp_unregister_shutdown_handler(esp_usb_console_before_restart);
@@ -320,7 +314,7 @@ esp_err_t esp_usb_console_init(void)
usb_dfu_set_detach_cb(esp_usb_console_dfu_detach_cb);
/* Enable interrupts on USB peripheral side */
USB0.gahbcfg |= USB_GLBLLNTRMSK_M;
usb_dwc_ll_gahbcfg_en_global_intr(USB_DWC_LL_GET_HW(USB_CONSOLE_DWC_CTRL_IDX));
/* Enable the interrupt handler */
esp_intr_enable(s_usb_int_handle);

109
components/soc/esp32h4/include/soc/usb_struct.h
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@@ -1,109 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* USB IN EP Register block type */
typedef struct usb_in_ep_reg {
volatile uint32_t diepctl;
uint32_t reserved;
volatile uint32_t diepint;
uint32_t reserved1;
volatile uint32_t dieptsiz;
volatile uint32_t diepdma;
volatile uint32_t dtxfsts;
uint32_t reserved2;
} usb_in_endpoint_t;
/* USB OUT EP Register block type */
typedef struct usb_out_ep_reg {
volatile uint32_t doepctl;
uint32_t reserved;
volatile uint32_t doepint;
uint32_t reserved1;
volatile uint32_t doeptsiz;
volatile uint32_t doepdma;
uint32_t reserved2;
uint32_t reserved3;
} usb_out_endpoint_t;
typedef struct usb_dev_t {
volatile uint32_t gotgctl;
volatile uint32_t gotgint;
volatile uint32_t gahbcfg;
volatile uint32_t gusbcfg;
volatile uint32_t grstctl;
volatile uint32_t gintsts;
volatile uint32_t gintmsk;
volatile uint32_t grxstsr;
volatile uint32_t grxstsp;
volatile uint32_t grxfsiz;
volatile uint32_t gnptxfsiz;
volatile uint32_t gnptxsts;
uint32_t reserved_0x0030_0x0040[4];
volatile uint32_t gsnpsid;
volatile uint32_t ghwcfg1;
volatile uint32_t ghwcfg2;
volatile uint32_t ghwcfg3;
volatile uint32_t ghwcfg4;
uint32_t reserved_0x0054_0x005c[2];
volatile uint32_t gdfifocfg;
uint32_t reserved_0x0060_0x0100[40];
volatile uint32_t hptxfsiz;
volatile uint32_t dieptxf[4];
uint32_t reserved_0x0114_0x0140[11];
uint32_t reserved_0x0140_0x0400[176];
volatile uint32_t hcfg;
volatile uint32_t hfir;
volatile uint32_t hfnum;
uint32_t reserved0x40C;
volatile uint32_t hptxsts;
volatile uint32_t haint;
volatile uint32_t haintmsk;
volatile uint32_t hflbaddr;
uint32_t reserved0x0420_0x0440[8];
volatile uint32_t hprt;
uint32_t reserved_0x0444_0x0500[47];
volatile uint32_t host_chan_regs[128];
uint32_t reserved_0x0700_0x0800[64];
volatile uint32_t dcfg;
volatile uint32_t dctl;
volatile uint32_t dsts;
uint32_t reserved0x80c;
volatile uint32_t diepmsk;
volatile uint32_t doepmsk;
volatile uint32_t daint;
volatile uint32_t daintmsk;
uint32_t reserved_0x0820_0x0828[2];
volatile uint32_t dvbusdis;
volatile uint32_t dvbuspulse;
volatile uint32_t dthrctl;
volatile uint32_t dtknqr4_fifoemptymsk;
uint32_t reserved_0x0838_0x0900[50];
usb_in_endpoint_t in_ep_reg[7];
uint32_t reserved_0x09e0_0x0b00[72];
usb_out_endpoint_t out_ep_reg[7];
uint32_t reserved_0x0be0_0x0d00[72];
uint32_t reserved_0x0d00_0x0e00[64];
uint32_t pcgctrl;
uint32_t reserved_0x0e04;
uint8_t reserved8[0x1000 - 0xe08];
uint32_t fifo[16][0x400];
uint8_t reserved0x11000[0x20000 - 0x11000];
uint32_t dbg_fifo[0x20000];
} usb_dev_t;
extern usb_dev_t USB0;
#ifdef __cplusplus
}
#endif

10461
components/soc/esp32s2/register/soc/usb_reg.h
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File diff suppressed because it is too large Load Diff

121
components/soc/esp32s2/register/soc/usb_struct.h
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@@ -1,121 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* USB IN EP Register block type */
typedef struct usb_in_ep_reg {
volatile uint32_t diepctl;
uint32_t reserved;
volatile uint32_t diepint;
uint32_t reserved1;
volatile uint32_t dieptsiz;
volatile uint32_t diepdma;
volatile uint32_t dtxfsts;
uint32_t reserved2;
} usb_in_endpoint_t;
/* USB OUT EP Register block type */
typedef struct usb_out_ep_reg {
volatile uint32_t doepctl;
uint32_t reserved;
volatile uint32_t doepint;
uint32_t reserved1;
volatile uint32_t doeptsiz;
volatile uint32_t doepdma;
uint32_t reserved2;
uint32_t reserved3;
} usb_out_endpoint_t;
typedef struct usb_reg {
volatile uint32_t gotgctl; // 0x0000 OTG Control and Status Register
volatile uint32_t gotgint; // 0x0004 OTG Interrupt Register
volatile uint32_t gahbcfg; // 0x0008 AHB Configuration Register
volatile uint32_t gusbcfg; // 0x000c USB Configuration Register
volatile uint32_t grstctl; // 0x0010 Reset Register
volatile uint32_t gintsts; // 0x0014 Interrupt Register
volatile uint32_t gintmsk; // 0x0018 Interrupt Mask Register
volatile uint32_t grxstsr; // 0x001c Receive Status Debug Read Register
volatile uint32_t grxstsp; // 0x0020 Receive Status Read/Pop Register
volatile uint32_t grxfsiz; // 0x0024 Receive FIFO Size Register
volatile uint32_t gnptxfsiz; // 0x0028 Non-periodic Transmit FIFO Size Register
volatile uint32_t gnptxsts; // 0x002c Non-periodic Transmit FIFO/Queue Status Register
uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040
volatile uint32_t gsnpsid; // 0x0040 ID Register
volatile uint32_t ghwcfg1; // 0x0044 User Hardware Configuration 1 Register
volatile uint32_t ghwcfg2; // 0x0048 User Hardware Configuration 2 Register
volatile uint32_t ghwcfg3; // 0x004c User Hardware Configuration 3 Register
volatile uint32_t ghwcfg4; // 0x0050 User Hardware Configuration 4 Register
uint32_t reserved_0x0054_0x005c[2]; // 0x0054 to 0x005c
volatile uint32_t gdfifocfg; // 0x005c Global DFIFO Configuration Register
uint32_t reserved_0x0060_0x0100[40]; // 0x0060 to 0x0100
volatile uint32_t hptxfsiz; // 0x0100 Host Periodic Transmit FIFO Size Register
volatile uint32_t dieptxf[4]; // 0x0104 to 0x0114 Device IN Endpoint Transmit FIFO Size Register i
uint32_t reserved_0x0114_0x0140[11]; // 0x0114 to 0x0140
uint32_t reserved_0x0140_0x0400[176]; // 0x0140 to 0x0400
/**
* Host mode registers offsets from 0x0400 to 0x07FF
*/
volatile uint32_t hcfg; // 0x0400 Host Configuration Register
volatile uint32_t hfir; // 0x0404 Host Frame Interval Register
volatile uint32_t hfnum; // 0x0408 Host Frame Number/Frame Remaining Register
uint32_t reserved0x40C; // 0x040c Reserved
volatile uint32_t hptxsts; // 0x0410 Host Periodic Transmit FIFO/ Queue Status Register
volatile uint32_t haint; // 0x0414 Host All Channels Interrupt Register
volatile uint32_t haintmsk; // 0x0418 Host All Channels Interrupt Mask Register
volatile uint32_t hflbaddr; // 0x041c Host Frame List Base Address Register
uint32_t reserved0x0420_0x0440[8]; // 0x0420 to 0x0440
volatile uint32_t hprt; // 0x0440 Host Port Control and Status Register
uint32_t reserved_0x0444_0x0500[47]; // 0x0444 to 0x0500
//Skip over the host channel registers
volatile uint32_t host_chan_regs[128]; // 0x0500 to 0x0700
uint32_t reserved_0x0700_0x0800[64]; // 0x0700 to 0x0800
/**
* Device mode registers offsets from
*/
volatile uint32_t dcfg; // 0x0800 Device Configuration Register
volatile uint32_t dctl; // 0x0804 Device Control Register
volatile uint32_t dsts; // 0x0808 Device Status Register (Read Only)
uint32_t reserved0x80c; // 0x080c
volatile uint32_t diepmsk; // 0x0810 Device IN Endpoint Common Interrupt Mask Register
volatile uint32_t doepmsk; // 0x0814 Device OUT Endpoint Common Interrupt Mask Register
volatile uint32_t daint; // 0x0818 Device All Endpoints Interrupt Register
volatile uint32_t daintmsk; // 0x081c Device All Endpoints Interrupt Mask Register
uint32_t reserved_0x0820_0x0828[2]; // 0x0820 to 0x0828
volatile uint32_t dvbusdis; // 0x0828 Device VBUS discharge Register
volatile uint32_t dvbuspulse; // 0x082c Device VBUS Pulse Register
volatile uint32_t dthrctl; // 0x0830 Device Thresholding control register (Read/Write)
volatile uint32_t dtknqr4_fifoemptymsk; // 0x0834 Device IN Endpoint FIFO Empty Interrupt Mask register
uint32_t reserved_0x0838_0x0900[50]; // 0x0838 to 0x0900
// Input Endpoints
usb_in_endpoint_t in_ep_reg[7]; // 0x0900 to 0x09e0 IN EP registers
uint32_t reserved_0x09e0_0x0b00[72]; // 0x09e0 to 0x0b00
// Output Endpoints
usb_out_endpoint_t out_ep_reg[7]; // 0x0b00 to 0x0be0 OUT EP registers
uint32_t reserved_0x0be0_0x0d00[72]; // 0x0be0 to 0x0d00
uint32_t reserved_0x0d00_0x0e00[64]; // 0x0d00 to 0x0e00
/**
* Power Control and direct FIFO access
*/
uint32_t pcgctrl; // 0x0e00 Power and Clock Gating Control Register
uint32_t reserved_0x0e04; // 0x0e04
uint8_t reserved8[0x1000 - 0xe08]; // 0x0d00 to 0x1000
uint32_t fifo[16][0x400]; // 0x1000 to 0x2000 Device EP i/Host Channel i FIFO
uint8_t reserved0x11000[0x20000 - 0x11000];
uint32_t dbg_fifo[0x20000]; // 0x2000 to 0x22000 Direct Access to Data FIFO RAM for Debugging
} usb_dev_t;
extern usb_dev_t USB0;
#ifdef __cplusplus
}
#endif

10462
components/soc/esp32s3/register/soc/usb_reg.h
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File diff suppressed because it is too large Load Diff

121
components/soc/esp32s3/register/soc/usb_struct.h
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@@ -1,121 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* USB IN EP Register block type */
typedef struct usb_in_ep_reg {
volatile uint32_t diepctl;
uint32_t reserved;
volatile uint32_t diepint;
uint32_t reserved1;
volatile uint32_t dieptsiz;
volatile uint32_t diepdma;
volatile uint32_t dtxfsts;
uint32_t reserved2;
} usb_in_endpoint_t;
/* USB OUT EP Register block type */
typedef struct usb_out_ep_reg {
volatile uint32_t doepctl;
uint32_t reserved;
volatile uint32_t doepint;
uint32_t reserved1;
volatile uint32_t doeptsiz;
volatile uint32_t doepdma;
uint32_t reserved2;
uint32_t reserved3;
} usb_out_endpoint_t;
typedef struct usb_reg {
volatile uint32_t gotgctl; // 0x0000 OTG Control and Status Register
volatile uint32_t gotgint; // 0x0004 OTG Interrupt Register
volatile uint32_t gahbcfg; // 0x0008 AHB Configuration Register
volatile uint32_t gusbcfg; // 0x000c USB Configuration Register
volatile uint32_t grstctl; // 0x0010 Reset Register
volatile uint32_t gintsts; // 0x0014 Interrupt Register
volatile uint32_t gintmsk; // 0x0018 Interrupt Mask Register
volatile uint32_t grxstsr; // 0x001c Receive Status Debug Read Register
volatile uint32_t grxstsp; // 0x0020 Receive Status Read/Pop Register
volatile uint32_t grxfsiz; // 0x0024 Receive FIFO Size Register
volatile uint32_t gnptxfsiz; // 0x0028 Non-periodic Transmit FIFO Size Register
volatile uint32_t gnptxsts; // 0x002c Non-periodic Transmit FIFO/Queue Status Register
uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040
volatile uint32_t gsnpsid; // 0x0040 ID Register
volatile uint32_t ghwcfg1; // 0x0044 User Hardware Configuration 1 Register
volatile uint32_t ghwcfg2; // 0x0048 User Hardware Configuration 2 Register
volatile uint32_t ghwcfg3; // 0x004c User Hardware Configuration 3 Register
volatile uint32_t ghwcfg4; // 0x0050 User Hardware Configuration 4 Register
uint32_t reserved_0x0054_0x005c[2]; // 0x0054 to 0x005c
volatile uint32_t gdfifocfg; // 0x005c Global DFIFO Configuration Register
uint32_t reserved_0x0060_0x0100[40]; // 0x0060 to 0x0100
volatile uint32_t hptxfsiz; // 0x0100 Host Periodic Transmit FIFO Size Register
volatile uint32_t dieptxf[4]; // 0x0104 to 0x0114 Device IN Endpoint Transmit FIFO Size Register i
uint32_t reserved_0x0114_0x0140[11]; // 0x0114 to 0x0140
uint32_t reserved_0x0140_0x0400[176]; // 0x0140 to 0x0400
/**
* Host mode registers offsets from 0x0400 to 0x07FF
*/
volatile uint32_t hcfg; // 0x0400 Host Configuration Register
volatile uint32_t hfir; // 0x0404 Host Frame Interval Register
volatile uint32_t hfnum; // 0x0408 Host Frame Number/Frame Remaining Register
uint32_t reserved0x40C; // 0x040c Reserved
volatile uint32_t hptxsts; // 0x0410 Host Periodic Transmit FIFO/ Queue Status Register
volatile uint32_t haint; // 0x0414 Host All Channels Interrupt Register
volatile uint32_t haintmsk; // 0x0418 Host All Channels Interrupt Mask Register
volatile uint32_t hflbaddr; // 0x041c Host Frame List Base Address Register
uint32_t reserved0x0420_0x0440[8]; // 0x0420 to 0x0440
volatile uint32_t hprt; // 0x0440 Host Port Control and Status Register
uint32_t reserved_0x0444_0x0500[47]; // 0x0444 to 0x0500
//Skip over the host channel registers
volatile uint32_t host_chan_regs[128]; // 0x0500 to 0x0700
uint32_t reserved_0x0700_0x0800[64]; // 0x0700 to 0x0800
/**
* Device mode registers offsets from
*/
volatile uint32_t dcfg; // 0x0800 Device Configuration Register
volatile uint32_t dctl; // 0x0804 Device Control Register
volatile uint32_t dsts; // 0x0808 Device Status Register (Read Only)
uint32_t reserved0x80c; // 0x080c
volatile uint32_t diepmsk; // 0x0810 Device IN Endpoint Common Interrupt Mask Register
volatile uint32_t doepmsk; // 0x0814 Device OUT Endpoint Common Interrupt Mask Register
volatile uint32_t daint; // 0x0818 Device All Endpoints Interrupt Register
volatile uint32_t daintmsk; // 0x081c Device All Endpoints Interrupt Mask Register
uint32_t reserved_0x0820_0x0828[2]; // 0x0820 to 0x0828
volatile uint32_t dvbusdis; // 0x0828 Device VBUS discharge Register
volatile uint32_t dvbuspulse; // 0x082c Device VBUS Pulse Register
volatile uint32_t dthrctl; // 0x0830 Device Thresholding control register (Read/Write)
volatile uint32_t dtknqr4_fifoemptymsk; // 0x0834 Device IN Endpoint FIFO Empty Interrupt Mask register
uint32_t reserved_0x0838_0x0900[50]; // 0x0838 to 0x0900
// Input Endpoints
usb_in_endpoint_t in_ep_reg[7]; // 0x0900 to 0x09e0 IN EP registers
uint32_t reserved_0x09e0_0x0b00[72]; // 0x09e0 to 0x0b00
// Output Endpoints
usb_out_endpoint_t out_ep_reg[7]; // 0x0b00 to 0x0be0 OUT EP registers
uint32_t reserved_0x0be0_0x0d00[72]; // 0x0be0 to 0x0d00
uint32_t reserved_0x0d00_0x0e00[64]; // 0x0d00 to 0x0e00
/**
* Power Control and direct FIFO access
*/
uint32_t pcgctrl; // 0x0e00 Power and Clock Gating Control Register
uint32_t reserved_0x0e04; // 0x0e04
uint8_t reserved8[0x1000 - 0xe08]; // 0x0d00 to 0x1000
uint32_t fifo[16][0x400]; // 0x1000 to 0x2000 Device EP i/Host Channel i FIFO
uint8_t reserved0x11000[0x20000 - 0x11000];
uint32_t dbg_fifo[0x20000]; // 0x2000 to 0x22000 Direct Access to Data FIFO RAM for Debugging
} usb_dev_t;
extern usb_dev_t USB0;
#ifdef __cplusplus
}
#endif