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feat(esp_hw_support): decrease retention current and duration

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This commit is contained in:
hebinglin
2026-05-09 16:01:14 +08:00
parent b46b72cf19
commit 312076e955
4 changed files with 77 additions and 38 deletions
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22
components/esp_hw_support/port/esp32h4/pmu_param.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,7 +17,13 @@
#include "esp_hw_log.h"
#include "soc/clk_tree_defs.h"
static __attribute__((unused)) const char *TAG = "pmu_param";
#define PMU_CLK_SRC_VAL(src) \
(((uint32_t)src == (uint32_t)SOC_MOD_CLK_XTAL) ? 0 : \
((uint32_t)src == (uint32_t)SOC_MOD_CLK_RC_FAST) ? 1 : \
((uint32_t)src == (uint32_t)SOC_MOD_CLK_XTAL_X2_F64M) ? 2 : \
((uint32_t)src == (uint32_t)SOC_MOD_CLK_PLL_F96M) ? 3 : 0)
ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param");
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
@@ -130,7 +136,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod
}
#define PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT() { \
.icg_func = 0, \
.icg_func = BIT(PMU_ICG_FUNC_ENA_REGDMA) | BIT(PMU_ICG_FUNC_ENA_HPBUS), \
.icg_apb = 0, \
.icg_modem = { \
.code = PMU_HP_ICG_MODEM_CODE_MODEM \
@@ -319,8 +325,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.retention = { \
.hp_sleep2active_backup_modem_clk_code = 2, \
.hp_modem2active_backup_modem_clk_code = 2, \
.hp_sleep2active_backup_clk_sel = 0, \
.hp_modem2active_backup_clk_sel = 1, \
.hp_sleep2active_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \
.hp_modem2active_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \
.hp_sleep2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 0), \
.hp_modem2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 2), \
.hp_sleep2active_backup_en = 0, \
@@ -332,7 +338,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \
.retention = { \
.hp_sleep2modem_backup_modem_clk_code = 1, \
.hp_sleep2modem_backup_clk_sel = 0, \
.hp_sleep2modem_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \
.hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
.hp_sleep2modem_backup_en = 0, \
}, \
@@ -343,8 +349,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.retention = { \
.hp_modem2sleep_backup_modem_clk_code = 0, \
.hp_active2sleep_backup_modem_clk_code = 2, \
.hp_modem2sleep_backup_clk_sel = 0, \
.hp_active2sleep_backup_clk_sel = 0, \
.hp_modem2sleep_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \
.hp_active2sleep_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \
.hp_modem2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 1), \
.hp_active2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 0), \
.hp_modem2sleep_backup_en = 0, \

25
components/soc/esp32h4/include/soc/pmu_icg_mapping.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -14,7 +14,7 @@
#define PMU_ICG_APB_ENA_MSPI 5
#define PMU_ICG_APB_ENA_UART0 6
#define PMU_ICG_APB_ENA_UART1 7
#define PMU_ICG_APB_ENA_SPI3 8
#define PMU_ICG_APB_ENA_UHCI 8
#define PMU_ICG_APB_ENA_SARADC 9
#define PMU_ICG_APB_ENA_TG0 11
#define PMU_ICG_APB_ENA_TG1 12
@@ -23,8 +23,8 @@
#define PMU_ICG_APB_ENA_RMT 15
#define PMU_ICG_APB_ENA_SYSTIMER 16
#define PMU_ICG_APB_ENA_USB_DEVICE 17
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_PWM1 19
#define PMU_ICG_APB_ENA_TWAI0 18
#define PMU_ICG_APB_ENA_TWAI1 19
#define PMU_ICG_APB_ENA_PCNT 20
#define PMU_ICG_APB_ENA_PWM 21
#define PMU_ICG_APB_ENA_SOC_ETM 22
@@ -33,19 +33,18 @@
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
#define PMU_ICG_APB_ENA_IOMUX 26
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_APB_ENA_BS 28
#define PMU_ICG_FUNC_ENA_GDMA 0
#define PMU_ICG_FUNC_ENA_SPI2 1
#define PMU_ICG_FUNC_ENA_I2S_RX 2
#define PMU_ICG_FUNC_ENA_UART0 3
#define PMU_ICG_FUNC_ENA_UART1 4
#define PMU_ICG_FUNC_ENA_PCNT 5
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_ASRC 8
#define PMU_ICG_FUNC_ENA_USB_OTG11 9
#define PMU_ICG_FUNC_ENA_DEBUG 10
#define PMU_ICG_FUNC_ENA_SPI3 11
#define PMU_ICG_FUNC_ENA_REGDMA 8
#define PMU_ICG_FUNC_ENA_RETENTION 9
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
#define PMU_ICG_FUNC_ENA_TSENS 12
#define PMU_ICG_FUNC_ENA_TG1 13
#define PMU_ICG_FUNC_ENA_TG0 14
@@ -58,11 +57,11 @@
#define PMU_ICG_FUNC_ENA_RMT 21
#define PMU_ICG_FUNC_ENA_PWM 22
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_PWM1 24
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_PARL_TX 30
#define PMU_ICG_FUNC_ENA_CAN0 31
#define PMU_ICG_FUNC_ENA_TWAI1 30
#define PMU_ICG_FUNC_ENA_TWAI0 31

2
components/soc/esp32h4/include/soc/system_periph_retention.h
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@@ -54,7 +54,7 @@ extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
*/
#define IOMUX_RETENTION_LINK_LEN 7
#define IOMUX_RETENTION_LINK_LEN 6
extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN];
/**

66
components/soc/esp32h4/system_retention_periph.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -19,10 +19,10 @@
#include "soc/clic_reg.h"
/* Interrupt Matrix Registers Context */
#define N_REGS_INTR_MATRIX(i) (((INTERRUPT_CORE0_CLOCK_GATE_REG(i) - (DR_REG_INTERRUPT_CORE0_BASE + (i) * 0x1000)) / 4) + 1)
#define N_REGS_INTR_MATRIX(i) (((INTERRUPT_CORE0_CLOCK_GATE_REG(i) - INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG(i)) / 4) + 1)
const regdma_entries_config_t intr_matrix_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_CORE0_BASE, DR_REG_INTERRUPT_CORE0_BASE, N_REGS_INTR_MATRIX(0), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* intr matrix */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(1), DR_REG_INTERRUPT_CORE1_BASE, DR_REG_INTERRUPT_CORE1_BASE, N_REGS_INTR_MATRIX(1), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG(0), INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG(0), N_REGS_INTR_MATRIX(0), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* intr matrix */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(1), INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG(1), INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG(1), N_REGS_INTR_MATRIX(1), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */
};
_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions");
@@ -51,19 +51,53 @@ const regdma_entries_config_t tee_apm_highpri_regs_retention[] = {
_Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions");
/* IO MUX Registers Context */
#define N_REGS_IOMUX_0() (((PERIPHS_IO_MUX_U_PAD_GPIO39 - REG_IO_MUX_BASE) / 4) + 1)
#define N_REGS_IOMUX_1() (((GPIO_FUNC39_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
#define N_REGS_IOMUX_2() (((GPIO_FUNC189_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1)
#define N_REGS_IOMUX_3() (((GPIO_PIN39_REG - GPIO_PIN0_REG) / 4) + 1)
#define N_REGS_IOMUX_4() (((GPIO_STATUS1_REG - GPIO_OUT_REG) / 4) + 1)
#define N_REGS_IOMUX_0() (SOC_GPIO_PIN_COUNT)
#define N_REGS_IOMUX_1() (SOC_GPIO_PIN_COUNT)
#define N_REGS_IOMUX_2() (SOC_GPIO_PIN_COUNT)
/*
* (1) Backup 87 x FUNCx_IN_SEL_CFG from GPIO_FUNC0_IN_SEL_CFG_REG (FUNC0, FUNC8..FUNC19, FUNC29..FUNC37, FUNC43..FUNC47, FUNC49..FUNC69, FUNC75..FUNC93, FUNC97..FUNC100, FUNC102..FUNC117).
* Restore 87 x FUNCx_IN_SEL_CFG from GPIO_FUNC0_IN_SEL_CFG_REG (FUNC0, FUNC8..FUNC19, FUNC29..FUNC37, FUNC43..FUNC47, FUNC49..FUNC69, FUNC75..FUNC93, FUNC97..FUNC100, FUNC102..FUNC117).
*/
#define GPIO_IN_SEL_CFG_RETENTION_REGS_CNT0 87
#define GPIO_IN_SEL_CFG_RETENTION_MAP_BASE0 GPIO_FUNC0_IN_SEL_CFG_REG
static const uint32_t gpio_in_sel_cfg_regs_map0[4] = {0xE00FFF01, 0xFFFEF83F, 0x3FFFF83F, 0x003FFFDE};
/*
* (2) Backup 25 x FUNCx_IN_SEL_CFG from GPIO_FUNC155_IN_SEL_CFG_REG (FUNC155..FUNC171, FUNC182..FUNC189).
* Restore 25 x FUNCx_IN_SEL_CFG from GPIO_FUNC155_IN_SEL_CFG_REG (FUNC155..FUNC171, FUNC182..FUNC189).
* gpio_in_sel_cfg_regs_map1 = 128-bit retention mask for this slice.
*/
#define GPIO_IN_SEL_CFG_RETENTION_REGS_CNT1 25
#define GPIO_IN_SEL_CFG_RETENTION_MAP_BASE1 GPIO_FUNC155_IN_SEL_CFG_REG
static const uint32_t gpio_in_sel_cfg_regs_map1[4] = {0xF801FFFF, 0x00000007, 0x0, 0x0};
/*
* (3) Backup 6 words from GPIO_OUT_REG, GPIO_OUT1_REG, GPIO_ENABLE_REG, GPIO_ENABLE1_REG, GPIO_STATUS_REG, GPIO_STATUS_REG(GPIO0-31 and GPIO32-43).
* Restore 6 words from GPIO_OUT_W1TS_REG, GPIO_OUT1_W1TS_REG, GPIO_ENABLE_W1TS_REG, GPIO_ENABLE1_W1TS_REG, GPIO_STATUS_W1TS_REG, GPIO_STATUS1_W1TS_REG.
*/
#define GPIO_RETENTION_REGS_CNT 6
#define GPIO_BACKUP_MAP_BASE GPIO_OUT_REG
#define GPIO_RETENTION_MAP_BASE GPIO_OUT_W1TS_REG
static const uint32_t gpio_regs_map[4] = {0x90009009, 0x0, 0x0, 0x0};
const regdma_entries_config_t iomux_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_OUT_REG, GPIO_OUT_W1TS_REG, N_REGS_IOMUX_4(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x05), GPIO_ENABLE_REG, GPIO_ENABLE_W1TS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x06), GPIO_ENABLE1_REG, GPIO_ENABLE1_W1TS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), IO_MUX_GPIO0_REG, IO_MUX_GPIO0_REG, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_IN_SEL_CFG_RETENTION_MAP_BASE0, GPIO_IN_SEL_CFG_RETENTION_MAP_BASE0, GPIO_IN_SEL_CFG_RETENTION_REGS_CNT0, 0, 0,
gpio_in_sel_cfg_regs_map0[0], gpio_in_sel_cfg_regs_map0[1], gpio_in_sel_cfg_regs_map0[2], gpio_in_sel_cfg_regs_map0[3]), .owner = ENTRY(0) | ENTRY(2)
},
[4] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_IN_SEL_CFG_RETENTION_MAP_BASE1, GPIO_IN_SEL_CFG_RETENTION_MAP_BASE1, GPIO_IN_SEL_CFG_RETENTION_REGS_CNT1, 0, 0,
gpio_in_sel_cfg_regs_map1[0], gpio_in_sel_cfg_regs_map1[1], gpio_in_sel_cfg_regs_map1[2], gpio_in_sel_cfg_regs_map1[3]), .owner = ENTRY(0) | ENTRY(2)
},
[5] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_IOMUX_LINK(0x05), GPIO_BACKUP_MAP_BASE, GPIO_RETENTION_MAP_BASE, GPIO_RETENTION_REGS_CNT, 0, 0,
gpio_regs_map[0], gpio_regs_map[1], gpio_regs_map[2], gpio_regs_map[3]), .owner = ENTRY(0) | ENTRY(2)
}
};
_Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions");