mirror of
https://github.com/espressif/esp-idf.git
synced 2026-05-28 16:46:31 +03:00
change(esp_hw_support): disable flash pd in h4 h21 c5 c61
This commit is contained in:
hebinglin
@@ -84,6 +84,7 @@ menu "Hardware Settings"
|
||||
select ESP_REGI2C_CTRL_FUNC_IN_IRAM
|
||||
depends on !SPIRAM || ESP_LDO_RESERVE_PSRAM || SOC_PSRAM_HAS_DEDICATED_LDO
|
||||
depends on !(IDF_TARGET_ESP32P4 && (ESP32P4_REV_MIN_FULL < 100))
|
||||
depends on !SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
default n
|
||||
help
|
||||
If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs
|
||||
@@ -227,7 +228,7 @@ menu "Hardware Settings"
|
||||
config ESP_SLEEP_SET_FLASH_DPD
|
||||
bool "Set SPI flash to deep power-down mode in light sleep"
|
||||
depends on (!APP_BUILD_TYPE_PURE_RAM_APP && !ESP_SLEEP_POWER_DOWN_FLASH && !SPI_FLASH_ROM_IMPL)
|
||||
default y if (IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H21)
|
||||
default y if SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
default y if (IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3)
|
||||
default n
|
||||
help
|
||||
@@ -237,11 +238,10 @@ menu "Hardware Settings"
|
||||
which will reduce the sleep current by about 10uA. And you can also use this option to reduce power
|
||||
consumption when using PSRAM
|
||||
|
||||
NOTE: We have conducted sufficient testing on ESP32H21, ESP32H4 and ESP32P4(less v3). If you plan to
|
||||
use a customized flash chip, or if you are working with other ESP32-series chips, please make sure to
|
||||
check the corresponding flash datasheet or consult us directly. This is to ensure that using the B9h
|
||||
command to enter Deep Power-Down mode and ABh to exit Deep Power-Down mode will not introduce any
|
||||
potential issues.
|
||||
NOTE: We have conducted sufficient testing on ESP32-C5, ESP32-C61, ESP32-H21, ESP32-H4 and
|
||||
ESP32-P4 (less v3). If you plan to use a customized flash chip, or if you are working with other
|
||||
ESP32-series chips, please make sure to check the corresponding flash datasheet or consult us
|
||||
directly. This is to ensure that using the B9h command to enter Deep Power-Down mode and ABh to exit.
|
||||
|
||||
config ESP_SLEEP_SPI_FLASH_ENTER_DPD_MODE_DELAY
|
||||
int "SPI Flash enter deep power-down time delay (in us)"
|
||||
|
||||
@@ -1574,6 +1574,7 @@ esp_err_t esp_light_sleep_start(void)
|
||||
* will be set in `sleep_flags`.
|
||||
*/
|
||||
if (sleep_flags & RTC_SLEEP_PD_VDDSDIO) {
|
||||
#if !SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
/*
|
||||
* When VDD_SDIO power domain has to be turned off, the minimum sleep time of the
|
||||
* system needs to meet the sum below:
|
||||
@@ -1609,8 +1610,13 @@ esp_err_t esp_light_sleep_start(void)
|
||||
s_config.sleep_time_adjustment -= flash_enable_time_us;
|
||||
}
|
||||
}
|
||||
} else if (!(sleep_flags & RTC_SLEEP_PD_VDDSDIO)) {
|
||||
#else
|
||||
sleep_flags &= ~RTC_SLEEP_PD_VDDSDIO;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
|
||||
if (!(sleep_flags & RTC_SLEEP_PD_VDDSDIO) && (sleep_flags & RTC_SLEEP_FLASH_DPD)) {
|
||||
const uint32_t flash_enable_dpd_us = spi_flash_dpd_get_enter_duration() + spi_flash_dpd_get_exit_duration();
|
||||
if (s_config.sleep_duration > flash_enable_dpd_us) {
|
||||
if (s_config.sleep_time_overhead_out < flash_enable_dpd_us) {
|
||||
@@ -1625,8 +1631,8 @@ esp_err_t esp_light_sleep_start(void)
|
||||
s_config.sleep_time_adjustment -= flash_enable_dpd_us;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
periph_inform_out_light_sleep_overhead(s_config.sleep_time_adjustment - sleep_time_overhead_in);
|
||||
|
||||
@@ -2954,9 +2960,20 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
|
||||
#endif
|
||||
|
||||
#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
|
||||
if (!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
|
||||
// Flash power domain will disable DPD mode.
|
||||
pd_flags |= RTC_SLEEP_FLASH_DPD;
|
||||
{
|
||||
uint32_t pd_flags_for_dpd = pd_flags;
|
||||
#if SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
/* Light sleep never powers down the flash supply on these targets; an app may still set VDDSDIO
|
||||
* domain to OFF manually, and we later strip RTC_SLEEP_PD_VDDSDIO.
|
||||
* Mask the bit when deriving DPD so flash deep power-down is not suppressed. */
|
||||
pd_flags_for_dpd &= ~RTC_SLEEP_PD_VDDSDIO;
|
||||
#endif
|
||||
if (!(pd_flags_for_dpd & RTC_SLEEP_PD_VDDSDIO)) {
|
||||
// Flash power domain will disable DPD mode.
|
||||
pd_flags |= RTC_SLEEP_FLASH_DPD;
|
||||
} else {
|
||||
ESP_LOGW(TAG, "Flash DPD mode cannot be enabled when VDDSDIO is configured to power down.");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -1463,6 +1463,10 @@ config SOC_PM_RETENTION_MODULE_NUM
|
||||
int
|
||||
default 32
|
||||
|
||||
config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -593,6 +593,8 @@
|
||||
|
||||
#define SOC_PM_RETENTION_MODULE_NUM (32)
|
||||
|
||||
#define SOC_PM_FLASH_KEEP_POWER_IN_LSLP (1) /*!<Keep flash on in light sleep to reduce wake latency and current leakage*/
|
||||
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
|
||||
|
||||
@@ -1103,6 +1103,10 @@ config SOC_PM_RETENTION_MODULE_NUM
|
||||
int
|
||||
default 32
|
||||
|
||||
config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -456,6 +456,8 @@
|
||||
|
||||
#define SOC_PM_RETENTION_MODULE_NUM (32)
|
||||
|
||||
#define SOC_PM_FLASH_KEEP_POWER_IN_LSLP (1) /*!<Keep flash on in light sleep to reduce wake latency and current leakage*/
|
||||
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
|
||||
|
||||
@@ -1023,6 +1023,10 @@ config SOC_PM_SUPPORT_PMU_CLK_ICG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -468,6 +468,8 @@
|
||||
|
||||
#define SOC_PM_SUPPORT_PMU_CLK_ICG (1)
|
||||
|
||||
#define SOC_PM_FLASH_KEEP_POWER_IN_LSLP (1) /*!<Keep flash on in light sleep to reduce wake latency*/
|
||||
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
|
||||
|
||||
@@ -1231,6 +1231,10 @@ config SOC_PM_MODEM_LOCK_CLK_WORKAROUND
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -518,6 +518,8 @@
|
||||
#define SOC_PM_BBPLL_PD_IN_MODEM_STATE (1)
|
||||
#define SOC_PM_MODEM_LOCK_CLK_WORKAROUND (1) // In ESP32H4, the modem lock will lock the xtalx2, bbpll and other xpd state during modem2active.
|
||||
|
||||
#define SOC_PM_FLASH_KEEP_POWER_IN_LSLP (1) /*!<Keep flash on in light sleep to reduce wake latency*/
|
||||
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
|
||||
|
||||
@@ -282,15 +282,17 @@ This section introduces the recommended configuration and configuration steps fo
|
||||
|
||||
.. only:: SOC_PM_SUPPORT_VDDSDIO_PD
|
||||
|
||||
- Power down flash in light sleep (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
|
||||
.. only:: SOC_PM_SUPPORT_VDDSDIO_PD and not SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
|
||||
.. only:: SOC_SPIRAM_SUPPORTED
|
||||
- Power down flash in light sleep (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
|
||||
|
||||
Due to the shared power pins between flash and PSRAM, cutting power to PSRAM would result in data loss. Therefore, to ensure light sleep does not disrupt program execution, enabling this option requires that the system does not utilize PSRAM.
|
||||
.. only:: SOC_SPIRAM_SUPPORTED
|
||||
|
||||
Due to the shared power pins between flash and PSRAM, cutting power to PSRAM would result in data loss. Therefore, to ensure light sleep does not disrupt program execution, enabling this option requires that the system does not utilize PSRAM.
|
||||
|
||||
.. only:: SOC_PM_SUPPORT_TOP_PD
|
||||
|
||||
- Power down Digital Peripheral modules and all child power domains under the TOP power domain in light sleep (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
|
||||
- Power down Digital Peripheral modules and all child power domains under the TOP power domain in light sleep (:ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`)
|
||||
|
||||
.. only:: SOC_PM_SUPPORT_RTC_PERIPH_PD
|
||||
|
||||
@@ -343,7 +345,7 @@ Configuration Steps:
|
||||
Recommended Configuration
|
||||
+++++++++++++++++++++++++++++
|
||||
|
||||
.. only:: esp32c6 or esp32c5
|
||||
.. only:: esp32c6
|
||||
|
||||
.. list-table::
|
||||
:header-rows: 1
|
||||
@@ -400,6 +402,63 @@ Recommended Configuration
|
||||
.. note::
|
||||
Configurations not mentioned in the above table are set to default.
|
||||
|
||||
.. only:: esp32c5
|
||||
|
||||
.. list-table::
|
||||
:header-rows: 1
|
||||
:widths: 30 15
|
||||
|
||||
* - Configuration Name
|
||||
- Configuration Status
|
||||
|
||||
* - Enable power management component (:ref:`CONFIG_PM_ENABLE`)
|
||||
- ON
|
||||
|
||||
* - Enable RTOS Tickless IDLE mode (:ref:`CONFIG_FREERTOS_USE_TICKLESS_IDLE`)
|
||||
- ON
|
||||
|
||||
* - RTOS Tick rate (Hz) (:ref:`CONFIG_FREERTOS_HZ`)
|
||||
- 1000
|
||||
|
||||
* - Minimum IDLE Tick count before entering sleep mode (:ref:`CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP`)
|
||||
- 3
|
||||
|
||||
* - Put light sleep related codes in IRAM (:ref:`CONFIG_PM_SLP_IRAM_OPT`)
|
||||
- ON
|
||||
|
||||
* - Put RTOS IDLE related codes in IRAM (:ref:`CONFIG_PM_RTOS_IDLE_OPT`)
|
||||
- OFF
|
||||
|
||||
* - RTC slow clock source (:ref:`CONFIG_RTC_CLK_SRC`)
|
||||
- Internal 150 kHz OSC
|
||||
|
||||
* - Disable all GPIO when chip at sleep (:ref:`CONFIG_PM_SLP_DISABLE_GPIO`)
|
||||
- ON
|
||||
|
||||
* - Power down MAC and baseband (:ref:`CONFIG_ESP_PHY_MAC_BB_PD`)
|
||||
- ON
|
||||
|
||||
* - Power down CPU (:ref:`CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP`)
|
||||
- ON
|
||||
|
||||
* - Set flash into deep power-down mode in light sleep (:ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`)
|
||||
- ON
|
||||
|
||||
* - ``max_freq_mhz``
|
||||
- The maximum CPU frequency supported by {IDF_TARGET_NAME}
|
||||
|
||||
* - ``min_freq_mhz``
|
||||
- {CONFIG_XTAL_FREQ}
|
||||
|
||||
* - ``light_sleep_enable``
|
||||
- true
|
||||
|
||||
.. note::
|
||||
Configurations not mentioned in the above table are set to default.
|
||||
|
||||
.. note::
|
||||
On {IDF_TARGET_NAME}, SPI flash need remains powered during light sleep and :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` is not available.
|
||||
|
||||
.. only:: esp32s3
|
||||
|
||||
.. list-table::
|
||||
|
||||
@@ -491,10 +491,26 @@ By default, :cpp:func:`esp_deep_sleep_start` and :cpp:func:`esp_light_sleep_star
|
||||
|
||||
In {IDF_TARGET_NAME}, there is only RTC FAST memory, so if some variables in the program are marked by ``RTC_DATA_ATTR``, ``RTC_SLOW_ATTR`` or ``RTC_FAST_ATTR`` attributes, all of them go to RTC FAST memory. It will be kept powered on by default. This can be overridden using :cpp:func:`esp_sleep_pd_config` function, if desired.
|
||||
|
||||
.. _spi_flash_power_down_dpd:
|
||||
|
||||
Flash Entering Deep Power-Down Mode
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
For Light-sleep, ESP-IDF recommends lowering SPI Flash sleep current using **Deep Power-Down (DPD)** first: enable :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD` so the SPI Flash enters its deep power-down command mode while the supply rail remains on. Current draw is typically very low (often below 1 µA for many SPI Flash devices), without the wake-up delay of fully cycling the SPI Flash supply.
|
||||
|
||||
In almost all use cases, DPD offers better overall trade-offs than cutting SPI Flash supply power—both safer for execution and still very low power.
|
||||
|
||||
.. note::
|
||||
**Mutually exclusive strategies:** Power-down SPI Flash during Light-sleep (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` or ``esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_OFF)``) **cannot be combined** with DPD. Kconfig exposes :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD` only when :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` is disabled.
|
||||
|
||||
.. warning::
|
||||
|
||||
Before using this feature, check the datasheet of the SPI Flash device used on your chip to ensure it supports the Deep Power-Down mode.
|
||||
|
||||
.. _spi_flash_power_down:
|
||||
|
||||
Power-down of Flash
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
By default, to avoid potential issues, :cpp:func:`esp_light_sleep_start` function does **not** power down SPI Flash. To be more specific, it takes time to power down the SPI Flash and during this period the system may be woken up, which then actually powers up the SPI Flash before this SPI Flash could be powered down completely. As a result, there is a chance that the SPI Flash may not work properly.
|
||||
|
||||
@@ -524,26 +540,15 @@ However, for those who have fully understood the risk and are still willing to p
|
||||
- ESP-IDF does not provide any mechanism that can power down the SPI Flash in all conditions when Light-sleep.
|
||||
- :cpp:func:`esp_deep_sleep_start` function forces power down SPI Flash regardless of user configuration.
|
||||
|
||||
.. _spi_flash_power_down_dpd:
|
||||
|
||||
Flash Entering Deep Power-Down Mode
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
In addition to reducing power consumption by completely powering off the SPI Flash, you can further lower SPI Flash power usage during sleep by enabling the Kconfig option :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`. Compared with fully cutting off the SPI Flash power, this feature avoids the extra delay caused by re-powering the SPI Flash when the chip wakes up from sleep, while still achieving extremely low power consumption. Most SPI Flash draw less than 1 µA when entering Deep Power-Down (DPD) mode.
|
||||
|
||||
In almost all use cases, using DPD mode provides better overall benefits than fully powering off the SPI Flash, offering both improved safety and lower power consumption.
|
||||
|
||||
.. warning::
|
||||
|
||||
Before using this feature, check the datasheet of the SPI Flash device used on your chip to ensure it supports the Deep Power-Down mode.
|
||||
.. _spi_flash_sleep_strategy_recommendations:
|
||||
|
||||
Flash Sleep Strategy Recommendations
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
In sleep scenarios, the SPI Flash handling method directly affects system safety, and power consumption. Different application scenarios prioritize these factors differently, so it is important to choose an appropriate SPI Flash sleep strategy.
|
||||
|
||||
Keep Flash Powered On
|
||||
"""""""""""""""""""""
|
||||
"""""""""""""""""""""""""""""
|
||||
|
||||
The standby power consumption of different SPI Flash varies. In ESP series chips, the standby power consumption of SPI Flash is typically below 30 µA. In the following scenarios, it is recommended to keep the SPI Flash powered on:
|
||||
|
||||
@@ -555,27 +560,12 @@ The standby power consumption of different SPI Flash varies. In ESP series chips
|
||||
|
||||
In the above cases, keeping the SPI Flash powered on is the most conservative and safest choice, but note that its standby power consumption is relatively high (about 10-30 µA).
|
||||
|
||||
Power Down Flash
|
||||
""""""""""""""""
|
||||
|
||||
You can refer to :ref:`spi_flash_power_down` to power down the SPI Flash during sleep. After the following conditions are met or after thorough evaluation, you may consider this strategy:
|
||||
|
||||
1. The application has strict requirements for extremely low power consumption.
|
||||
|
||||
2. Wake-up sources are controllable, typically only RTC timer wake-up sources are enabled.
|
||||
|
||||
3. It can be ensured that the actual sleep time is greater than the time required for the SPI Flash to completely power down. For ESP series chips other than ESP32-C5 and ESP32-C61, the time required for the SPI Flash to completely power down may be greater than 300ms; while for ESP32-C5 and ESP32-C61, due to the fast discharge feature, the time required is greater than 5ms. If parallel capacitors exist in the SPI Flash power supply circuit, longer sleep time may be required.
|
||||
|
||||
4. If the sleep time is too short, the power consumption during the SPI Flash power-on and power-down processes may exceed the power consumption when keeping it powered on.
|
||||
|
||||
5. There is sufficient control over SPI Flash power supply and IO states to avoid SPI Flash leakage due to pin pull-up during sleep.
|
||||
|
||||
Since the SPI Flash power-down process is greatly affected by hardware design, IO impedance characteristics, power supply, and environmental factors, ESP-IDF cannot guarantee that the SPI Flash will be safely powered down in Light-sleep mode. Therefore, this method is only suitable for scenarios with controllable risks and thorough verification.
|
||||
|
||||
Flash Entering Deep Power-Down (DPD) Mode
|
||||
""""""""""""""""""""""""""""""""""""""""""
|
||||
"""""""""""""""""""""""""""""""""""""""""
|
||||
|
||||
In the vast majority of application scenarios, it is recommended to prioritize using the Deep Power-Down (DPD) mode of the SPI Flash to reduce sleep power consumption. For power figures, timings, and how to enable this feature, see :ref:`spi_flash_power_down_dpd` above instead of duplicating them here. DPD mode is suitable for the following scenarios:
|
||||
When standby power is still too high, prefer **Deep Power-Down** via :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`; see :ref:`spi_flash_power_down_dpd` for figures, timings, and how to enable it.
|
||||
|
||||
DPD mode is suitable for the following scenarios:
|
||||
|
||||
1. Significant reduction in SPI Flash power consumption during sleep is needed, but the risk of SPI Flash re-powering should be avoided.
|
||||
|
||||
@@ -583,6 +573,25 @@ In the vast majority of application scenarios, it is recommended to prioritize u
|
||||
|
||||
3. SPI Flash chip used explicitly supports Deep Power-Down mode.
|
||||
|
||||
.. only:: not SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
|
||||
Power Down Flash
|
||||
""""""""""""""""""""
|
||||
|
||||
You can refer to :ref:`spi_flash_power_down` to power down the SPI Flash during sleep. After the following conditions are met or after thorough evaluation, you may consider this strategy:
|
||||
|
||||
1. The application has strict requirements for extremely low power consumption.
|
||||
|
||||
2. Wake-up sources are controllable, typically only RTC timer wake-up sources are enabled.
|
||||
|
||||
3. It can be ensured that the actual sleep time is greater than the time required for the SPI Flash to completely power down. For ESP series chips, the time required for the SPI Flash to completely power down may be greater than 300ms. If parallel capacitors exist in the SPI Flash power supply circuit, longer sleep time may be required.
|
||||
|
||||
4. If the sleep time is too short, the power consumption during the SPI Flash power-on and power-down processes may exceed the power consumption when keeping it powered on.
|
||||
|
||||
5. There is sufficient control over SPI Flash power supply and IO states to avoid SPI Flash leakage due to pin pull-up during sleep.
|
||||
|
||||
Since the SPI Flash power-down process is greatly affected by hardware design, IO impedance characteristics, power supply, and environmental factors, ESP-IDF cannot guarantee that the SPI Flash will be safely powered down in Light-sleep mode. Therefore, this method is only suitable for scenarios with controllable risks and thorough verification.
|
||||
|
||||
Configuring IOs (Deep-sleep Only)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
|
||||
@@ -282,11 +282,13 @@ Light-sleep 模式配置
|
||||
|
||||
.. only:: SOC_PM_SUPPORT_VDDSDIO_PD
|
||||
|
||||
- 在 light sleep 状态关闭 flash 供电 (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
|
||||
.. only:: SOC_PM_SUPPORT_VDDSDIO_PD and not SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
|
||||
.. only:: SOC_SPIRAM_SUPPORTED
|
||||
- 在 light sleep 状态关闭 flash 供电 (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
|
||||
|
||||
由于 flash 和 PSRAM 共用供电管脚，PSRAM 关闭供电将会导致数据丢失，因此，为保证 light sleep 不破坏程序运行状态，启用该选项的前提是系统没有使用 PSRAM。
|
||||
.. only:: SOC_SPIRAM_SUPPORTED
|
||||
|
||||
由于 flash 和 PSRAM 共用供电管脚，PSRAM 关闭供电将会导致数据丢失，因此，为保证 light sleep 不破坏程序运行状态，启用该选项的前提是系统没有使用 PSRAM。
|
||||
|
||||
.. only:: SOC_PM_SUPPORT_TOP_PD
|
||||
|
||||
@@ -343,7 +345,7 @@ Light-sleep 模式配置
|
||||
推荐配置
|
||||
+++++++++
|
||||
|
||||
.. only:: esp32c6 or esp32c5
|
||||
.. only:: esp32c6
|
||||
|
||||
.. list-table::
|
||||
:header-rows: 1
|
||||
@@ -400,6 +402,63 @@ Light-sleep 模式配置
|
||||
.. note::
|
||||
上表中不涉及的配置均是默认。
|
||||
|
||||
.. only:: esp32c5
|
||||
|
||||
.. list-table::
|
||||
:header-rows: 1
|
||||
:widths: 30 15
|
||||
|
||||
* - 配置名称
|
||||
- 设置情况
|
||||
|
||||
* - 启用电源管理组件 (:ref:`CONFIG_PM_ENABLE`)
|
||||
- ON
|
||||
|
||||
* - 启用 Tickless IDLE 模式 (:ref:`CONFIG_FREERTOS_USE_TICKLESS_IDLE`)
|
||||
- ON
|
||||
|
||||
* - RTOS Tick rate (Hz) (:ref:`CONFIG_FREERTOS_HZ`)
|
||||
- 1000
|
||||
|
||||
* - 进入睡眠模式前最小 IDLE Tick 数 (:ref:`CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP`)
|
||||
- 3
|
||||
|
||||
* - 将 light sleep 相关代码放置在片内 RAM 中 (:ref:`CONFIG_PM_SLP_IRAM_OPT`)
|
||||
- ON
|
||||
|
||||
* - 将 RTOS IDLE 相关代码放置在片内 RAM 中 (:ref:`CONFIG_PM_RTOS_IDLE_OPT`)
|
||||
- OFF
|
||||
|
||||
* - RTC 慢速时钟源 (:ref:`CONFIG_RTC_CLK_SRC`)
|
||||
- 内部 150 kHz 振荡器
|
||||
|
||||
* - 芯片休眠时禁用所有 GPIO (:ref:`CONFIG_PM_SLP_DISABLE_GPIO`)
|
||||
- ON
|
||||
|
||||
* - 关闭 MAC 和基带 (:ref:`CONFIG_ESP_PHY_MAC_BB_PD`)
|
||||
- ON
|
||||
|
||||
* - 关闭 CPU (:ref:`CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP`)
|
||||
- ON
|
||||
|
||||
* - 在 light sleep 状态配置 flash 进入 deep power-down 模式 (:ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`)
|
||||
- ON
|
||||
|
||||
* - ``max_freq_mhz``
|
||||
- {IDF_TARGET_NAME} 支持的最大 CPU 频率
|
||||
|
||||
* - ``min_freq_mhz``
|
||||
- {CONFIG_XTAL_FREQ}
|
||||
|
||||
* - ``light_sleep_enable``
|
||||
- true
|
||||
|
||||
.. note::
|
||||
上表中不涉及的配置均是默认。
|
||||
|
||||
.. note::
|
||||
在 {IDF_TARGET_NAME} 上，light sleep 期间 SPI flash 供电需保持开启，不提供 :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`。
|
||||
|
||||
.. only:: esp32s3
|
||||
|
||||
.. list-table::
|
||||
|
||||
@@ -491,10 +491,26 @@ RTC 外设和内存断电
|
||||
|
||||
{IDF_TARGET_NAME} 中只有 RTC 高速内存，因此，如果程序中的某些值被标记为 ``RTC_DATA_ATTR``、``RTC_SLOW_ATTR`` 或 ``RTC_FAST_ATTR`` 属性，那么所有这些值都将被存入 RTC 高速内存，默认情况下保持供电。如有需要，也可以使用函数 :cpp:func:`esp_sleep_pd_config` 对其进行修改。
|
||||
|
||||
.. _spi_flash_power_down_dpd:
|
||||
|
||||
SPI Flash 进入 deep power-down 模式
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
为降低 Light-sleep 期间 SPI Flash 的功耗，ESP-IDF **优先推荐**采用 **Deep Power-Down（DPD）**：通过启用配置项 :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`，令 SPI Flash 在供电保持开启的前提下进入器件内部的深度休眠指令状态。多数 SPI Flash 在 DPD 下电流可降至极低水平（常低于 1 µA），同时可避免反复上下电带来的唤醒延迟。
|
||||
|
||||
在几乎所有应用场景中，相较彻底切断 SPI Flash 供电，DPD 在安全性与功耗之间通常是更好的折中。
|
||||
|
||||
.. note::
|
||||
**两种方式互斥：** Light-sleep 下的 SPI Flash **断电**（:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` 或通过 ``esp_sleep_pd_config`` 将 ``ESP_PD_DOMAIN_VDDSDIO`` 置为关闭）与 **DPD** **不可同时使用**， 在 menuconfig 中仅能在禁用 :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` 后再启用 :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`。
|
||||
|
||||
.. warning::
|
||||
|
||||
使用该功能前需要查阅使用芯片所搭载的 SPI Flash 的技术手册是否支持 deep power-down 模式。
|
||||
|
||||
.. _spi_flash_power_down:
|
||||
|
||||
SPI Flash 断电
|
||||
^^^^^^^^^^
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
默认情况下，调用函数 :cpp:func:`esp_light_sleep_start` 后，SPI Flash **不会** 断电，因为在 sleep 过程中断电 SPI Flash 存在风险。具体而言，SPI Flash 断电需要时间，但是在此期间，系统有可能被唤醒，导致 SPI Flash 重新被上电。此时，断电尚未完成又重新上电的硬件行为有可能导致 SPI Flash 无法正常工作。
|
||||
|
||||
@@ -524,18 +540,7 @@ SPI Flash 断电
|
||||
- Light-sleep 模式下，ESP-IDF 没有提供保证 SPI Flash 一定会被断电的机制。
|
||||
- 不管用户的配置如何，函数 :cpp:func:`esp_deep_sleep_start` 都会强制断电 SPI Flash
|
||||
|
||||
.. _spi_flash_power_down_dpd:
|
||||
|
||||
SPI Flash 进入 deep power-down 模式
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
除了通过让 SPI Flash 完全断电来降低芯片功耗之外，还可以通过启用 Kconfig 配置项 :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`，进一步减少休眠期间 SPI Flash 的功耗。与直接对 SPI Flash 断电相比，该功能能够避免芯片从休眠唤醒时 SPI Flash 重新上电所带来的额外延迟，同时也能保持极低的功耗。大多数 SPI Flash 在进入 Deep Power-Down（DPD）模式后电流消耗低于 1 µA。
|
||||
|
||||
在几乎所有应用场景中，使用 DPD 模式都比直接断电 SPI Flash 更具优势，兼顾了安全性与低功耗表现。
|
||||
|
||||
.. warning::
|
||||
|
||||
使用该功能前需要查阅使用芯片所搭载的 SPI Flash 的技术手册是否支持 deep power-down 模式。
|
||||
.. _spi_flash_sleep_strategy_recommendations:
|
||||
|
||||
SPI Flash 休眠策略选择建议
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
@@ -543,7 +548,7 @@ SPI Flash 休眠策略选择建议
|
||||
在休眠场景下，SPI Flash 的处理方式直接影响系统的安全性、功耗。不同应用场景对这些因素的侧重不同，因此需要选择合适的 SPI Flash 休眠策略。
|
||||
|
||||
SPI Flash 不掉电
|
||||
"""""""""""""
|
||||
""""""""""""""""""""
|
||||
|
||||
不同 SPI Flash 的待机功耗不一致，在 ESP 系列芯片中，SPI Flash 的待机功耗通常低于 30 µA，在以下场景中，建议保持 SPI Flash 不掉电：
|
||||
|
||||
@@ -555,27 +560,12 @@ SPI Flash 不掉电
|
||||
|
||||
在上述情况下，保持 SPI Flash 供电是最保守、也是最安全的选择，但需要注意其待机功耗相对较高 (约 10-30 µA)。
|
||||
|
||||
SPI Flash 掉电
|
||||
"""""""""""
|
||||
|
||||
可以参考 :ref:`spi_flash_power_down` 实现在休眠中掉电 SPI Flash。在以下条件满足或经过充分评估后，可以考虑该策略：
|
||||
|
||||
1. 应用对极低功耗有严格要求。
|
||||
|
||||
2. 唤醒源可控，通常仅启用 RTC timer 唤醒源。
|
||||
|
||||
3. 能够确保实际睡眠时间大于 SPI Flash 彻底断电所需时间。对于除 ESP32-C5 和 ESP32-C61 之外的 ESP 系列芯片，SPI Flash 彻底断电所需时间可能大于 300ms；而对于 ESP32-C5 和 ESP32-C61，由于支持快速放电功能，彻底断电所需时间大于 5ms。如果 SPI Flash 供电电路中存在并联电容，可能需要更长的睡眠时间。
|
||||
|
||||
4. 如果休眠时间过短，SPI Flash 上电和下电过程所消耗的功耗可能会超过保持供电时的功耗。
|
||||
|
||||
5. 对 SPI Flash 供电及 IO 状态有充分控制，休眠时避免因为管脚上拉导致 SPI Flash 漏电。
|
||||
|
||||
由于 SPI Flash 的断电过程受硬件设计、IO 阻抗特性、供电以及环境因素影响较大，ESP-IDF 无法保证在 Light-sleep 模式下 SPI Flash 一定能够安全断电，因此该方式仅适用于风险可控且经过充分验证的场景。
|
||||
|
||||
SPI Flash 进入 deep power-down（DPD）模式
|
||||
""""""""""""""""""""""""""""""""""""""""""
|
||||
|
||||
在绝大多数应用场景中，推荐优先使用 SPI Flash 的 Deep Power-Down（DPD）模式来降低休眠功耗。功耗数据、时序及如何启用该功能请直接参见上文 :ref:`spi_flash_power_down_dpd`，此处不再重复。DPD 模式适用于以下场景：
|
||||
若待机功耗仍偏高，应优先采用 **Deep Power-Down（DPD）**，通过 :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD` 降低休眠电流；功耗数据、时序及启用方式参见前文 :ref:`spi_flash_power_down_dpd`。
|
||||
|
||||
DPD 模式适用于以下场景：
|
||||
|
||||
1. 需要显著降低休眠期间 SPI Flash 的功耗，但又希望避免 SPI Flash 重新上电的风险。
|
||||
|
||||
@@ -583,6 +573,25 @@ SPI Flash 进入 deep power-down（DPD）模式
|
||||
|
||||
3. 使用的 SPI Flash 芯片明确支持 Deep Power-Down 模式。
|
||||
|
||||
.. only:: not SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
|
||||
SPI Flash 掉电
|
||||
"""""""""""""""""
|
||||
|
||||
可以参考 :ref:`spi_flash_power_down` 实现在休眠中掉电 SPI Flash。在以下条件满足或经过充分评估后，可以考虑该策略：
|
||||
|
||||
1. 应用对极低功耗有严格要求。
|
||||
|
||||
2. 唤醒源可控，通常仅启用 RTC timer 唤醒源。
|
||||
|
||||
3. 能够确保实际睡眠时间大于 SPI Flash 彻底断电所需时间。对于 ESP 系列芯片，SPI Flash 彻底断电所需时间可能大于 300ms。如果 SPI Flash 供电电路中存在并联电容，可能需要更长的睡眠时间。
|
||||
|
||||
4. 如果休眠时间过短，SPI Flash 上电和下电过程所消耗的功耗可能会超过保持供电时的功耗。
|
||||
|
||||
5. 对 SPI Flash 供电及 IO 状态有充分控制，休眠时避免因为管脚上拉导致 SPI Flash 漏电。
|
||||
|
||||
由于 SPI Flash 的断电过程受硬件设计、IO 阻抗特性、供电以及环境因素影响较大，ESP-IDF 无法保证在 Light-sleep 模式下 SPI Flash 一定能够安全断电，因此该方式仅适用于风险可控且经过充分验证的场景。
|
||||
|
||||
配置 IO（仅适用于 Deep-sleep）
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
|
||||
Reference in New Issue
Block a user