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feat(soc): Add RISC-V trace ecause width and packet format caps

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Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
Erhan Kurubas
2026-09-03 08:20:11 +02:00
co-authored by Cursor
parent a9b89a3fd5
commit 5b4a90da6e
16 changed files with 80 additions and 0 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+8
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@@ -1623,6 +1623,10 @@ config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1638,3 +1642,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
components/soc/esp32c5/include/soc/soc_caps.h
+2
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@@ -647,7 +647,9 @@
#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED (1) /*!< LP UART wakeup source is kept triggered */
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+8
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@@ -1359,6 +1359,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 100
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 5
components/soc/esp32c6/include/soc/soc_caps.h
+2
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@@ -551,4 +551,6 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+8
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@@ -1243,6 +1243,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1258,3 +1262,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
components/soc/esp32c61/include/soc/soc_caps.h
+2
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@@ -501,10 +501,12 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
/*------------------------------------- No Reset CAPS -------------------------------------*/
// \#define SOC_CAPS_NO_RESET_BY_ANA_BOD (1) //TODO: [ESP32C61] IDF-9254
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+8
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@@ -1255,6 +1255,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 100
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 5
components/soc/esp32h2/include/soc/soc_caps.h
+2
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@@ -532,4 +532,6 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+8
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@@ -1155,6 +1155,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 100
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 5
components/soc/esp32h21/include/soc/soc_caps.h
+2
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@@ -500,4 +500,6 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+8
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@@ -1391,6 +1391,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1407,6 +1411,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
config SOC_ASRC_SUPPORTED
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+2
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@@ -571,10 +571,12 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
/*---------------------------------- ASRC CAPS ----------------------------------*/
#define SOC_ASRC_SUPPORTED (1)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+8
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@@ -1939,6 +1939,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1955,6 +1959,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+2
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@@ -742,8 +742,10 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
#define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM (1) /*!< Encoder AHB master can reach external PSRAM */
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+8
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@@ -1871,6 +1871,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1887,6 +1891,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 2
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
+2
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@@ -697,8 +697,10 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (2U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
#define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM (1) /*!< Encoder AHB master can reach external PSRAM */