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refactor(adc): move some ADC soc_caps to adc_ll.h

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This commit is contained in:
gaoxu
2026-06-01 19:05:33 +08:00
parent 13b4430716
commit 7dfc685010
58 changed files with 607 additions and 960 deletions
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components/esp_adc/adc_cali_curve_fitting.c
+4 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,6 +13,7 @@
#include "esp_check.h"
#include "esp_heap_caps.h"
#include "soc/soc_caps.h"
#include "hal/adc_ll.h"
#include "esp_adc/adc_cali_scheme.h"
#include "adc_cali_interface.h"
#include "esp_private/adc_share_hw_ctrl.h"
@@ -134,7 +135,7 @@ static esp_err_t cali_raw_to_voltage(void *arg, int raw, int *voltage)
int chan_compensation = adc_get_hw_calibration_chan_compens(ctx->unit_id, ctx->chan, ctx->atten);
raw -= chan_compensation;
/* Limit the range */
int max_val = (1L << SOC_ADC_RTC_MAX_BITWIDTH) - 1;
int max_val = (1L << ADC_LL_RTC_MAX_BITWIDTH) - 1;
raw = raw <= 0 ? 0 :
raw > max_val ? max_val : raw;
#endif // SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED
@@ -222,7 +223,7 @@ static esp_err_t check_valid(const adc_cali_curve_fitting_config_t *config)
ESP_RETURN_ON_FALSE(config->unit_id < SOC_ADC_PERIPH_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid ADC unit");
ESP_RETURN_ON_FALSE(config->atten < SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid ADC attenuation");
bool available_oneshot_bitwidth = (config->bitwidth >= SOC_ADC_RTC_MIN_BITWIDTH && config->bitwidth <= SOC_ADC_RTC_MAX_BITWIDTH);
bool available_oneshot_bitwidth = (config->bitwidth >= ADC_LL_RTC_MIN_BITWIDTH && config->bitwidth <= ADC_LL_RTC_MAX_BITWIDTH);
bool available_dma_bitwidth = (config->bitwidth >= SOC_ADC_DIGI_MIN_BITWIDTH && config->bitwidth <= SOC_ADC_DIGI_MAX_BITWIDTH);
bool default_bitwidth_mark = (config->bitwidth == ADC_BITWIDTH_DEFAULT);
bool available_bitwidth = (available_oneshot_bitwidth || available_dma_bitwidth || default_bitwidth_mark);
components/esp_adc/adc_common.c
+1 -1
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@@ -31,7 +31,7 @@ esp_err_t adc_io_to_channel(int io_num, adc_unit_t * const unit_id, adc_channel_
bool found = false;
for (int i = 0; i < SOC_ADC_PERIPH_NUM; i++) {
for (int j = 0; j < SOC_ADC_MAX_CHANNEL_NUM; j++) {
for (int j = 0; j < ADC_LL_MAX_CHANNEL_NUM; j++) {
if (adc_channel_io_map[i][j] == io_num) {
*channel = j;
*unit_id = i;
components/esp_adc/adc_continuous.c
+5 -3
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@@ -32,8 +32,10 @@
#include "esp_clk_tree.h"
#include "esp_private/gpio.h"
#include "esp_adc/adc_continuous.h"
#include "hal/adc_periph.h"
#include "hal/adc_types.h"
#include "hal/adc_hal.h"
#include "hal/adc_ll.h"
#include "hal/dma_types.h"
#include "soc/soc_caps.h"
#include "esp_memory_utils.h"
@@ -467,7 +469,7 @@ esp_err_t adc_continuous_config(adc_continuous_handle_t handle, const adc_contin
for (int i = 0; i < config->pattern_num; i++) {
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
//we add this error log to hint users what happened
if (SOC_ADC_DIG_SUPPORTED_UNIT(config->adc_pattern[i].unit) == 0) {
if (ADC_LL_DIG_SUPPORTED_UNIT(config->adc_pattern[i].unit) == 0) {
ESP_LOGE(ADC_TAG, "ADC2 continuous mode is no longer supported, please use ADC1. Search for errata on espressif website for more details. You can enable CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 to force use ADC2");
}
#endif //CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
@@ -477,11 +479,11 @@ esp_err_t adc_continuous_config(adc_continuous_handle_t handle, const adc_contin
* On all continuous mode supported chips, we will always check the unit to see if it's a continuous mode supported unit.
* However, on ESP32C3 and ESP32S3, we will jump this check, if `CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` is enabled.
*/
ESP_RETURN_ON_FALSE(SOC_ADC_DIG_SUPPORTED_UNIT(config->adc_pattern[i].unit), ESP_ERR_INVALID_ARG, ADC_TAG, "Only support using ADC1 DMA mode");
ESP_RETURN_ON_FALSE(ADC_LL_DIG_SUPPORTED_UNIT(config->adc_pattern[i].unit), ESP_ERR_INVALID_ARG, ADC_TAG, "Only support using ADC1 DMA mode");
#endif //#if !CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3
}
ESP_RETURN_ON_FALSE(config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC sampling frequency out of range");
ESP_RETURN_ON_FALSE(config->sample_freq_hz <= ADC_LL_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= ADC_LL_SAMPLE_FREQ_THRES_LOW, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC sampling frequency out of range");
#if CONFIG_IDF_TARGET_ESP32
handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE1;
#elif CONFIG_IDF_TARGET_ESP32S2
components/esp_adc/adc_continuous_internal.h
+2 -1
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@@ -14,6 +14,7 @@
#include "freertos/ringbuf.h"
#include "hal/adc_types.h"
#include "hal/adc_hal.h"
#include "hal/adc_ll.h"
//For DMA
#if SOC_GDMA_SUPPORTED
#include "esp_private/gdma.h"
@@ -97,7 +98,7 @@ struct adc_continuous_ctx_t {
uint32_t flush_pool: 1; //Flush the internal pool when the pool is full. With this flag, the `on_pool_ovf` event will not happen.
} flags;
#if SOC_ADC_DIG_IIR_FILTER_SUPPORTED
adc_iir_filter_t *iir_filter[SOC_ADC_DIGI_IIR_FILTER_NUM]; //ADC IIR filter context
adc_iir_filter_t *iir_filter[ADC_LL_DIGI_IIR_FILTER_NUM]; //ADC IIR filter context
#endif
#if SOC_ADC_MONITOR_SUPPORTED
adc_monitor_t *adc_monitor[SOC_ADC_DIGI_MONITOR_NUM]; // adc monitor context
components/esp_adc/adc_filter.c
+6 -6
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,11 +21,11 @@ static const char *TAG = "adc_filter";
static portMUX_TYPE s_filter_spinlock = portMUX_INITIALIZER_UNLOCKED;
#if SOC_ADC_DIG_IIR_FILTER_UNIT_BINDED
static atomic_bool s_adc_filter_claimed[SOC_ADC_DIGI_IIR_FILTER_NUM] = {ATOMIC_VAR_INIT(false),
#if (SOC_ADC_DIGI_IIR_FILTER_NUM >= 2)
ATOMIC_VAR_INIT(false)
static atomic_bool s_adc_filter_claimed[ADC_LL_DIGI_IIR_FILTER_NUM] = {ATOMIC_VAR_INIT(false),
#if (ADC_LL_DIGI_IIR_FILTER_NUM >= 2)
ATOMIC_VAR_INIT(false)
#endif
};
};
static esp_err_t s_adc_filter_claim(adc_continuous_handle_t handle, adc_iir_filter_t *filter_ctx, adc_unit_t unit)
{
@@ -61,7 +61,7 @@ static esp_err_t s_adc_filter_claim(adc_continuous_handle_t handle, adc_iir_filt
assert(handle && filter_ctx);
portENTER_CRITICAL(&s_filter_spinlock);
for (int i = 0; i < SOC_ADC_DIGI_IIR_FILTER_NUM; i++) {
for (int i = 0; i < ADC_LL_DIGI_IIR_FILTER_NUM; i++) {
bool found = !handle->iir_filter[i];
if (found) {
handle->iir_filter[i] = filter_ctx;
components/esp_adc/adc_oneshot.c
+3 -3
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@@ -89,7 +89,7 @@ esp_err_t adc_oneshot_new_unit(const adc_oneshot_unit_init_cfg_t *init_config, a
* We only check this on ESP32C3, because other adc units are no longer supported on later chips
* If CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 is enabled, we jump this check
*/
ESP_GOTO_ON_FALSE(SOC_ADC_DIG_SUPPORTED_UNIT(init_config->unit_id), ESP_ERR_INVALID_ARG, err, TAG, "adc unit not supported");
ESP_GOTO_ON_FALSE(ADC_LL_DIG_SUPPORTED_UNIT(init_config->unit_id), ESP_ERR_INVALID_ARG, err, TAG, "adc unit not supported");
#endif
unit = heap_caps_calloc(1, sizeof(adc_oneshot_unit_ctx_t), ADC_MEM_ALLOC_CAPS);
@@ -197,7 +197,7 @@ esp_err_t adc_oneshot_config_channel(adc_oneshot_unit_handle_t handle, adc_chann
{
ESP_RETURN_ON_FALSE(handle && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
ESP_RETURN_ON_FALSE(config->atten < SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid attenuation");
ESP_RETURN_ON_FALSE(((config->bitwidth >= SOC_ADC_RTC_MIN_BITWIDTH && config->bitwidth <= SOC_ADC_RTC_MAX_BITWIDTH) || config->bitwidth == ADC_BITWIDTH_DEFAULT), ESP_ERR_INVALID_ARG, TAG, "invalid bitwidth");
ESP_RETURN_ON_FALSE(((config->bitwidth >= ADC_LL_RTC_MIN_BITWIDTH && config->bitwidth <= ADC_LL_RTC_MAX_BITWIDTH) || config->bitwidth == ADC_BITWIDTH_DEFAULT), ESP_ERR_INVALID_ARG, TAG, "invalid bitwidth");
ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(handle->unit_id), ESP_ERR_INVALID_ARG, TAG, "invalid channel");
ESP_RETURN_ON_ERROR(s_adc_io_init(handle->unit_id, channel), TAG, "adc io init failed");
@@ -205,7 +205,7 @@ esp_err_t adc_oneshot_config_channel(adc_oneshot_unit_handle_t handle, adc_chann
adc_oneshot_hal_ctx_t *hal = &(handle->hal);
adc_oneshot_hal_chan_cfg_t cfg = {
.atten = config->atten,
.bitwidth = (config->bitwidth == ADC_BITWIDTH_DEFAULT) ? SOC_ADC_RTC_MAX_BITWIDTH : config->bitwidth,
.bitwidth = (config->bitwidth == ADC_BITWIDTH_DEFAULT) ? ADC_LL_RTC_MAX_BITWIDTH : config->bitwidth,
};
portENTER_CRITICAL(&rtc_spinlock);
adc_oneshot_hal_channel_config(hal, &cfg, channel);
components/esp_adc/esp32/adc_cali_line_fitting.c
+2 -1
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@@ -14,6 +14,7 @@
#include "hal/adc_types.h"
#include "hal/efuse_ll.h"
#include "soc/soc_caps.h"
#include "hal/adc_ll.h"
#include "esp_adc/adc_cali_scheme.h"
#include "adc_cali_interface.h"
@@ -157,7 +158,7 @@ esp_err_t adc_cali_create_scheme_line_fitting(const adc_cali_line_fitting_config
ESP_RETURN_ON_FALSE(config && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
ESP_RETURN_ON_FALSE(config->unit_id < SOC_ADC_PERIPH_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid ADC unit");
ESP_RETURN_ON_FALSE(config->atten < SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid ADC attenuation");
ESP_RETURN_ON_FALSE(((config->bitwidth >= SOC_ADC_RTC_MIN_BITWIDTH && config->bitwidth <= SOC_ADC_RTC_MAX_BITWIDTH) || config->bitwidth == ADC_BITWIDTH_DEFAULT), ESP_ERR_INVALID_ARG, TAG, "invalid bitwidth");
ESP_RETURN_ON_FALSE(((config->bitwidth >= ADC_LL_RTC_MIN_BITWIDTH && config->bitwidth <= ADC_LL_RTC_MAX_BITWIDTH) || config->bitwidth == ADC_BITWIDTH_DEFAULT), ESP_ERR_INVALID_ARG, TAG, "invalid bitwidth");
adc_cali_scheme_t *scheme = (adc_cali_scheme_t *)heap_caps_calloc(1, sizeof(adc_cali_scheme_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
ESP_RETURN_ON_FALSE(scheme, ESP_ERR_NO_MEM, TAG, "no mem for adc calibration scheme");
components/esp_adc/esp32c2/adc_cali_line_fitting.c
+2 -1
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@@ -14,6 +14,7 @@
#include "esp_heap_caps.h"
#include "esp_efuse_rtc_calib.h"
#include "soc/soc_caps.h"
#include "hal/adc_ll.h"
#include "esp_adc/adc_cali_scheme.h"
#include "adc_cali_interface.h"
@@ -123,7 +124,7 @@ static esp_err_t check_valid(const adc_cali_line_fitting_config_t *config)
ESP_LOGW(TAG, "Experimental: ADC Atten 0 calibration can now only used for inputs lower than 950mV. Calibration Scheme may get updated, DON'T USE FOR MASS PRODUCTION!");
}
bool available_oneshot_bitwidth = (config->bitwidth >= SOC_ADC_RTC_MIN_BITWIDTH && config->bitwidth <= SOC_ADC_RTC_MAX_BITWIDTH);
bool available_oneshot_bitwidth = (config->bitwidth >= ADC_LL_RTC_MIN_BITWIDTH && config->bitwidth <= ADC_LL_RTC_MAX_BITWIDTH);
bool available_dma_bitwidth = (config->bitwidth >= SOC_ADC_DIGI_MIN_BITWIDTH && config->bitwidth <= SOC_ADC_DIGI_MAX_BITWIDTH);
bool default_bitwidth_mark = (config->bitwidth == ADC_BITWIDTH_DEFAULT);
bool available_bitwidth = (available_oneshot_bitwidth || available_dma_bitwidth || default_bitwidth_mark);
components/esp_adc/esp32s2/adc_cali_line_fitting.c
+2 -1
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@@ -16,6 +16,7 @@
#include "hal/adc_types.h"
#include "soc/efuse_periph.h"
#include "soc/soc_caps.h"
#include "hal/adc_ll.h"
#include "esp_adc/adc_cali_scheme.h"
#include "adc_cali_interface.h"
@@ -90,7 +91,7 @@ esp_err_t adc_cali_create_scheme_line_fitting(const adc_cali_line_fitting_config
ESP_RETURN_ON_FALSE(config->unit_id < SOC_ADC_PERIPH_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid ADC unit");
ESP_RETURN_ON_FALSE(config->atten < SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid ADC attenuation");
//S2 Oneshot read only supports 13 bits, DMA read only supports 12 bits
ESP_RETURN_ON_FALSE(((config->bitwidth == SOC_ADC_RTC_MAX_BITWIDTH || config->bitwidth == SOC_ADC_DIGI_MAX_BITWIDTH) || config->bitwidth == ADC_BITWIDTH_DEFAULT), ESP_ERR_INVALID_ARG, TAG, "invalid bitwidth");
ESP_RETURN_ON_FALSE(((config->bitwidth == ADC_LL_RTC_MAX_BITWIDTH || config->bitwidth == SOC_ADC_DIGI_MAX_BITWIDTH) || config->bitwidth == ADC_BITWIDTH_DEFAULT), ESP_ERR_INVALID_ARG, TAG, "invalid bitwidth");
// current version only accepts encoding ver 1 and ver 2.
uint8_t adc_encoding_version = esp_efuse_rtc_table_read_calib_version();
ESP_RETURN_ON_FALSE(((adc_encoding_version == 1) || (adc_encoding_version == 2)), ESP_ERR_NOT_SUPPORTED, TAG, "Calibration required eFuse bits not burnt");
components/esp_adc/test_apps/adc/main/test_adc.c
+7 -7
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@@ -149,7 +149,7 @@ TEST_CASE("ADC oneshot stress test that get zero even if convent done", "[adc_on
};
adc_oneshot_chan_cfg_t config = {
.bitwidth = SOC_ADC_RTC_MAX_BITWIDTH,
.bitwidth = ADC_LL_RTC_MAX_BITWIDTH,
.atten = atten,
};
@@ -194,14 +194,14 @@ static void s_adc_oneshot_with_sleep(adc_unit_t unit_id, adc_channel_t channel)
//-------------ADC Channel Config---------------//
adc_oneshot_chan_cfg_t config = {
.bitwidth = SOC_ADC_RTC_MAX_BITWIDTH,
.bitwidth = ADC_LL_RTC_MAX_BITWIDTH,
};
//-------------ADC Calibration Init---------------//
bool do_calibration = false;
adc_cali_handle_t cali_handle[TEST_ATTEN_NUMS] = {};
for (int i = 0; i < TEST_ATTEN_NUMS; i++) {
do_calibration = test_adc_calibration_init(unit_id, channel, g_test_atten[i], SOC_ADC_RTC_MAX_BITWIDTH, &cali_handle[i]);
do_calibration = test_adc_calibration_init(unit_id, channel, g_test_atten[i], ADC_LL_RTC_MAX_BITWIDTH, &cali_handle[i]);
}
if (!do_calibration) {
ESP_LOGW(TAG, "No efuse bits burnt, only test the regi2c analog register values");
@@ -345,7 +345,7 @@ TEST_CASE("ADC continuous monitor init_deinit", "[adc]")
adc_continuous_config_t dig_cfg = {
.pattern_num = 1,
.adc_pattern = adc_pattern,
.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_LOW,
.sample_freq_hz = ADC_LL_SAMPLE_FREQ_THRES_LOW,
.conv_mode = ADC_CONV_SINGLE_UNIT_1,
.format = TEST_ADC_FORMAT_TYPE,
};
@@ -445,7 +445,7 @@ TEST_CASE("ADC continuous monitor functionary", "[adc]")
adc_continuous_config_t dig_cfg = {
.pattern_num = 2,
.adc_pattern = adc_pattern,
.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_LOW,
.sample_freq_hz = ADC_LL_SAMPLE_FREQ_THRES_LOW,
.conv_mode = ADC_CONV_SINGLE_UNIT_1,
.format = TEST_ADC_FORMAT_TYPE,
};
@@ -492,12 +492,12 @@ TEST_CASE("ADC continuous monitor functionary", "[adc]")
switch (pull_mode) {
case GPIO_PULLUP_ONLY:
#if !CONFIG_IDF_TARGET_ESP32S2
TEST_ASSERT_UINT32_WITHIN(SOC_ADC_SAMPLE_FREQ_THRES_LOW * 0.1, SOC_ADC_SAMPLE_FREQ_THRES_LOW, m1h_cnt);
TEST_ASSERT_UINT32_WITHIN(ADC_LL_SAMPLE_FREQ_THRES_LOW * 0.1, ADC_LL_SAMPLE_FREQ_THRES_LOW, m1h_cnt);
TEST_ASSERT_EQUAL(0, m1l_cnt); //low limit should NOT triggrted when pull_up
#endif
break;
case GPIO_PULLDOWN_ONLY:
TEST_ASSERT_UINT32_WITHIN(SOC_ADC_SAMPLE_FREQ_THRES_LOW * 0.1, SOC_ADC_SAMPLE_FREQ_THRES_LOW, m1l_cnt);
TEST_ASSERT_UINT32_WITHIN(ADC_LL_SAMPLE_FREQ_THRES_LOW * 0.1, ADC_LL_SAMPLE_FREQ_THRES_LOW, m1l_cnt);
TEST_ASSERT_EQUAL(0, m1h_cnt);
break;
case GPIO_PULLUP_PULLDOWN:
components/esp_adc/test_apps/adc/main/test_adc_driver.c
+4 -4
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@@ -314,13 +314,13 @@ TEST_CASE("ADC filter exhausted allocation", "[adc_continuous]")
};
TEST_ESP_OK(adc_continuous_new_handle(&adc_config, &handle));
adc_iir_filter_handle_t filter_hdl[SOC_ADC_DIGI_IIR_FILTER_NUM + 1] = {};
adc_iir_filter_handle_t filter_hdl[ADC_LL_DIGI_IIR_FILTER_NUM + 1] = {};
adc_continuous_iir_filter_config_t filter_config = {
.unit = ADC_UNIT_1,
.channel = ADC_CHANNEL_0,
.coeff = ADC_DIGI_IIR_FILTER_COEFF_2,
};
for (int i = 0; i < SOC_ADC_DIGI_IIR_FILTER_NUM; i++) {
for (int i = 0; i < ADC_LL_DIGI_IIR_FILTER_NUM; i++) {
#if SOC_ADC_DIG_IIR_FILTER_UNIT_BINDED
//On these chips, the unit and the filter_id should be the same
filter_config.unit = i;
@@ -329,9 +329,9 @@ TEST_CASE("ADC filter exhausted allocation", "[adc_continuous]")
}
filter_config.unit = ADC_UNIT_1;
TEST_ASSERT(adc_new_continuous_iir_filter(handle, &filter_config, &filter_hdl[SOC_ADC_DIGI_IIR_FILTER_NUM]) == ESP_ERR_NOT_FOUND);
TEST_ASSERT(adc_new_continuous_iir_filter(handle, &filter_config, &filter_hdl[ADC_LL_DIGI_IIR_FILTER_NUM]) == ESP_ERR_NOT_FOUND);
for (int i = 0; i < SOC_ADC_DIGI_IIR_FILTER_NUM; i++) {
for (int i = 0; i < ADC_LL_DIGI_IIR_FILTER_NUM; i++) {
TEST_ESP_OK(adc_del_continuous_iir_filter(filter_hdl[i]));
}
components/esp_adc/test_apps/adc/main/test_adc_performance.c
+6 -6
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@@ -384,9 +384,9 @@ static void test_adc_continuous_sample_freq(uint32_t sample_freq_hz)
TEST_CASE("ADC continuous sample frequency test", "[adc_continuous][performance]")
{
// Test minimum frequency
test_adc_continuous_sample_freq(SOC_ADC_SAMPLE_FREQ_THRES_LOW);
test_adc_continuous_sample_freq(ADC_LL_SAMPLE_FREQ_THRES_LOW);
// Test maximum frequency
test_adc_continuous_sample_freq(SOC_ADC_SAMPLE_FREQ_THRES_HIGH);
test_adc_continuous_sample_freq(ADC_LL_SAMPLE_FREQ_THRES_HIGH);
}
#endif //#if SOC_ADC_DMA_SUPPORTED
@@ -411,7 +411,7 @@ static float test_adc_oneshot_std(adc_atten_t atten, bool is_performance_test)
//-------------ADC Channel Config---------------//
adc_oneshot_chan_cfg_t config = {
.bitwidth = SOC_ADC_RTC_MAX_BITWIDTH,
.bitwidth = ADC_LL_RTC_MAX_BITWIDTH,
};
//-------------ADC Calibration Init---------------//
@@ -427,7 +427,7 @@ static float test_adc_oneshot_std(adc_atten_t atten, bool is_performance_test)
TEST_ESP_OK(adc_oneshot_config_channel(adc1_handle, channel, &config));
ESP_LOGI("TEST_ADC", "Test with atten: %d", atten);
s_reset_array(ADC_TEST_RAW_BUCKET_SIZE(SOC_ADC_RTC_MAX_BITWIDTH));
s_reset_array(ADC_TEST_RAW_BUCKET_SIZE(ADC_LL_RTC_MAX_BITWIDTH));
if (is_performance_test) {
test_adc_set_io_middle(ADC_UNIT_1, TEST_STD_ADC1_CHANNEL0);
@@ -511,7 +511,7 @@ static void s_adc_cali_speed(adc_unit_t unit_id, adc_channel_t channel)
bool do_calibration = false;
adc_cali_handle_t cali_handle[TEST_ATTEN_NUMS] = {};
for (int i = 0; i < TEST_ATTEN_NUMS; i++) {
do_calibration = test_adc_calibration_init(unit_id, channel, g_test_atten[i], SOC_ADC_RTC_MAX_BITWIDTH, &cali_handle[i]);
do_calibration = test_adc_calibration_init(unit_id, channel, g_test_atten[i], ADC_LL_RTC_MAX_BITWIDTH, &cali_handle[i]);
}
if (!do_calibration) {
@@ -532,7 +532,7 @@ static void s_adc_cali_speed(adc_unit_t unit_id, adc_channel_t channel)
//-------------ADC Channel Config---------------//
adc_oneshot_chan_cfg_t config = {
.bitwidth = SOC_ADC_RTC_MAX_BITWIDTH,
.bitwidth = ADC_LL_RTC_MAX_BITWIDTH,
};
//atten0 ~ atten3
components/esp_adc/test_apps/adc/main/test_common_adc.h
+1
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@@ -13,6 +13,7 @@
#include "unity.h"
#include "esp_log.h"
#include "soc/soc_caps.h"
#include "hal/adc_ll.h"
#include "esp_private/adc_private.h"
#include "esp_adc/adc_cali.h"
#include "esp_adc/adc_cali_scheme.h"
components/esp_hal_ana_conv/adc_hal.c
+4 -4
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@@ -90,9 +90,9 @@ void adc_hal_digi_deinit()
---------------------------------------------------------------*/
static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t convert_mode)
{
#if SOC_IS(ESP32) || SOC_ADC_DIGI_CONTROLLER_NUM == 1
#if SOC_IS(ESP32) || ADC_LL_DIGI_CONTROLLER_NUM == 1
return ADC_LL_DIGI_CONV_ONLY_ADC1;
#elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2)
#elif (ADC_LL_DIGI_CONTROLLER_NUM >= 2)
switch (convert_mode) {
case ADC_CONV_SINGLE_UNIT_1:
return ADC_LL_DIGI_CONV_ONLY_ADC1;
@@ -149,7 +149,7 @@ static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuo
void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg)
{
#if (SOC_ADC_DIGI_CONTROLLER_NUM == 1)
#if (ADC_LL_DIGI_CONTROLLER_NUM == 1)
//Only one pattern table, this variable is for readability
const int pattern_both = 0;
@@ -162,7 +162,7 @@ void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_c
adc_ll_set_power_manage(0, ADC_LL_POWER_SW_ON);
#endif
#elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2)
#elif (ADC_LL_DIGI_CONTROLLER_NUM >= 2)
uint32_t adc1_pattern_idx = 0;
uint32_t adc2_pattern_idx = 0;
components/esp_hal_ana_conv/esp32/adc_periph.c
+1 -1
View File
@@ -7,7 +7,7 @@
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][ADC_LL_MAX_CHANNEL_NUM] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM,
components/esp_hal_ana_conv/esp32/include/hal/adc_ll.h
+32 -23
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,7 +11,6 @@
#include "hal/adc_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/adc_periph.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "soc/sens_reg.h"
@@ -23,38 +22,48 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE (1 << 0)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE (1 << 0)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (0)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (10)
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (9)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (16)
* continuous
*-------------------------------------------------------------*/
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH (2000000)
#define ADC_LL_SAMPLE_FREQ_THRES_LOW (20000)
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) ((UNIT == 0) ? 1 : 0)
#define ADC_LL_DIGI_CONTROLLER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (16)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
//On esp32, ADC can only be continuously triggered when `ADC_LL_DEFAULT_CONV_LIMIT_EN == 1`, `ADC_LL_DEFAULT_CONV_LIMIT_NUM != 0`
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 1
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 1
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
typedef enum {
ADC_LL_CTRL_RTC = 0, ///< For ADC1 and ADC2. Select RTC controller.
components/esp_hal_ana_conv/esp32c2/include/hal/adc_ll.h
+35 -27
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,6 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
@@ -27,41 +26,50 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_MAX_CHANNEL_NUM (5)
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (1U)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
/*---------------------------------------------------------------
I2C SAR ADC REG PD workaround
---------------------------------------------------------------*/
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
typedef enum {
ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32c3/include/hal/adc_ll.h
+41 -33
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,6 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
@@ -28,59 +27,68 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_THRES0_HIGH_INT_ST_M | \
APB_SARADC_THRES1_HIGH_INT_ST_M | \
APB_SARADC_THRES0_LOW_INT_ST_M | \
APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (5)
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) ((UNIT == 0) ? 1 : 0) //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (1U)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/**
* Workaround: on ESP32C3, the internal hardware counter that counts ADC samples will not be automatically cleared,
* and there is no dedicated register to manually clear it. (see section 3.2 of the errata document).
* Therefore, traverse from 0 to the value configured last time, so as to clear the ADC sample counter.
*/
#define ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER (1)
#define ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER (1)
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
/*---------------------------------------------------------------
I2C SAR ADC REG PD workaround
---------------------------------------------------------------*/
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
typedef enum {
ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32c5/include/hal/adc_ll.h
+41 -28
View File
@@ -9,7 +9,6 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -28,47 +27,61 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (6)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32C5 supported to manage power mode
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (1U)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32C5 supported to manage power mode
/*---------------------------------------------------------------
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
typedef enum {
ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32c6/include/hal/adc_ll.h
+42 -29
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,7 +10,6 @@
#include "esp_attr.h"
#include "esp_rom_sys.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -29,46 +28,60 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (7)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32C6 supported to manage power mode
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (1U)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32C6 supported to manage power mode
/*---------------------------------------------------------------
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
typedef enum {
ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32c61/include/hal/adc_ll.h
+41 -28
View File
@@ -9,7 +9,6 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -28,47 +27,61 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_THRES_ALL_INTR_ST_M (SARADC_THRES0_HIGH_INT_ST_M | \
SARADC_THRES1_HIGH_INT_ST_M | \
SARADC_THRES0_LOW_INT_ST_M | \
SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? SARADC_THRES0_HIGH_INT_ST_M : SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? SARADC_THRES0_LOW_INT_ST_M : SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? SARADC_THRES0_HIGH_INT_ST_M : SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? SARADC_THRES0_LOW_INT_ST_M : SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (4)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32C61 supported to manage power mode
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (1U)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32C61 supported to manage power mode
/*---------------------------------------------------------------
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
typedef enum {
ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32h2/include/hal/adc_ll.h
+45 -35
View File
@@ -9,7 +9,6 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -28,53 +27,64 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (5)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 18
#define ADC_LL_CLKM_DIV_B_DEFAULT 5
#define ADC_LL_CLKM_DIV_A_DEFAULT 1
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32H2 supported to manage power mode
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5)
/*---------------------------------------------------------------
I2C SAR ADC REG PD workaround
---------------------------------------------------------------*/
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (1U)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 18
#define ADC_LL_CLKM_DIV_B_DEFAULT 5
#define ADC_LL_CLKM_DIV_A_DEFAULT 1
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32H2 supported to manage power mode
/*---------------------------------------------------------------
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
typedef enum {
ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32h21/include/hal/adc_ll.h
+42 -29
View File
@@ -9,7 +9,6 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -28,47 +27,61 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (5)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 18
#define ADC_LL_CLKM_DIV_B_DEFAULT 5
#define ADC_LL_CLKM_DIV_A_DEFAULT 1
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32H21 supported to manage power mode
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (1U)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 18
#define ADC_LL_CLKM_DIV_B_DEFAULT 5
#define ADC_LL_CLKM_DIV_A_DEFAULT 1
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32H21 supported to manage power mode
/*---------------------------------------------------------------
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
typedef enum {
ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32h4/include/hal/adc_ll.h
+41 -28
View File
@@ -9,7 +9,6 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -28,48 +27,62 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M | \
APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_ADC_FE_ON_MODEM_DOMAIN (1)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (5)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (5)
/*---------------------------------------------------------------
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (1U)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
/* Use 32 MHz XTAL / (5 + 2 / 5 + 1) = 5 MHz ADC_CTRL_CLK on H4. */
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 5
#define ADC_LL_CLKM_DIV_B_DEFAULT 5
#define ADC_LL_CLKM_DIV_A_DEFAULT 2
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 5
#define ADC_LL_CLKM_DIV_B_DEFAULT 5
#define ADC_LL_CLKM_DIV_A_DEFAULT 2
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32H4 supported to manage power mode
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32H4 supported to manage power mode
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
typedef enum {
ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32p4/include/hal/adc_ll.h
+43 -31
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,6 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "hal/adc_periph.h"
#include "soc/adc_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_struct.h"
@@ -27,47 +26,60 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define LP_ADC_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down
#define LP_ADC_FORCE_XPD_SAR_PD 2 // Force power down
#define LP_ADC_FORCE_XPD_SAR_PU 3 // Force power up
#define LP_ADC_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down
#define LP_ADC_FORCE_XPD_SAR_PD 2 // Force power down
#define LP_ADC_FORCE_XPD_SAR_PU 3 // Force power up
// ESP32P4 ADC2 channel is 2-7, so we need to subtract 2 to get the correct channel
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 2
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 2
#define ADC_LL_MAX_CHANNEL_NUM (8)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (((ADC_UNIT) == ADC_UNIT_1) ? 0 : 1)
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define LP_ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (10)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define LP_ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (10)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (2)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32P4 supported to manage power mode
#define ADC_LL_POWER_MANAGE_SUPPORTED 1 //ESP32P4 supported to manage power mode
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
typedef enum {
ADC_LL_CTRL_RTC = 0, ///< For ADC1 and ADC2. Select RTC controller.
components/esp_hal_ana_conv/esp32s2/include/hal/adc_ll.h
+42 -34
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,7 +8,6 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/adc_periph.h"
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#include "hal/assert.h"
@@ -29,50 +28,59 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE (1 << 0)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE (1 << 0)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_ADC1_THRES_INT_ST_M | APB_SARADC_ADC2_THRES_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_ADC1_THRES_INT_ST_M : APB_SARADC_ADC2_THRES_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_ADC1_THRES_INT_ST_M : APB_SARADC_ADC2_THRES_INT_ST_M)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_ADC1_THRES_INT_ST_M | APB_SARADC_ADC2_THRES_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_ADC1_THRES_INT_ST_M : APB_SARADC_ADC2_THRES_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_ADC1_THRES_INT_ST_M : APB_SARADC_ADC2_THRES_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (0)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (10)
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (13)
#define ADC_LL_RTC_MAX_BITWIDTH (13)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (3)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (2)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (2)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (3)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (2)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
/*---------------------------------------------------------------
I2C SAR ADC REG PD workaround
---------------------------------------------------------------*/
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
typedef enum {
ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32s3/include/hal/adc_ll.h
+41 -33
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,7 +8,6 @@
#include <stdio.h>
#include <stdbool.h>
#include "hal/adc_periph.h"
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#include "hal/assert.h"
@@ -28,53 +27,62 @@
extern "C" {
#endif
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE (1 << 0)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1)
/*---------------------------------------------------------------
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE (1 << 0)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1)
#define ADC_LL_THRES_ALL_INTR_ST_M (APB_SARADC_THRES0_HIGH_INT_ST_M | \
APB_SARADC_THRES1_HIGH_INT_ST_M | \
APB_SARADC_THRES0_LOW_INT_ST_M | \
APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_THRES1_HIGH_INT_ST_M)
#define ADC_LL_GET_LOW_THRES_MASK(monitor_id) ((monitor_id == 0) ? APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (0)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
#define ADC_LL_MAX_CHANNEL_NUM (10)
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (12)
#define ADC_LL_RTC_MAX_BITWIDTH (12)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
/*---------------------------------------------------------------
DMA
---------------------------------------------------------------*/
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
* continuous
*-------------------------------------------------------------*/
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH 83333
#define ADC_LL_SAMPLE_FREQ_THRES_LOW 611
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) ((UNIT == 0) ? 1 : 0) //Digital controller supported ADC unit
#define ADC_LL_DIGI_CONTROLLER_NUM (2)
#define ADC_LL_DIGI_IIR_FILTER_NUM (2)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*---------------------------------------------------------------
PWDET (Power Detect)
---------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_PWDET_CCT_DEFAULT (4)
/*---------------------------------------------------------------
I2C SAR ADC REG PD workaround
---------------------------------------------------------------*/
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
#define ADC_LL_ANA_CALI_REG_PD_WORKAROUND 1
#define ADC_LL_ANA_CALI_REG_BYTE_NUM 8
typedef enum {
ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
components/esp_hal_ana_conv/esp32s31/adc_periph.c
+1 -1
View File
@@ -7,7 +7,7 @@
#include "hal/adc_periph.h"
/* Store the GPIO number for each public ADC channel. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][ADC_LL_MAX_CHANNEL_NUM] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM,
components/esp_hal_ana_conv/esp32s31/include/hal/adc_ll.h
+44 -33
View File
@@ -7,7 +7,6 @@
#include <stdbool.h>
#include "hal/adc_periph.h"
#include "soc/adc_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/lp_peri_clkrst_struct.h"
@@ -22,51 +21,63 @@ extern "C" {
#endif
/*---------------------------------------------------------------
Macros
---------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
* common
*-------------------------------------------------------------*/
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
#define ADC_LL_FORCE_XPD_SAR_FSM 0 // Use FSM to control power
#define ADC_LL_FORCE_XPD_SAR_PD 2 // Force power down
#define ADC_LL_FORCE_XPD_SAR_PU 3 // Force power up
#define ADC_LL_FORCE_XPD_SAR_FSM 0 // Use FSM to control power
#define ADC_LL_FORCE_XPD_SAR_PD 2 // Force power down
#define ADC_LL_FORCE_XPD_SAR_PU 3 // Force power up
#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT) (1)
#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION (0)
#define ADC_LL_MAX_CHANNEL_NUM (8)
#define ADC_LL_DMA_USE_LP_AHB_GDMA 1
#define ADC_LL_DMA_USE_LP_AHB_GDMA 1
#define ADC_LL_DIGI_SAMPLE_FREQ_DYNAMIC_CLK_DIV 1
#define ADC_LL_RAW_DATA_WEIGHTED_SUM (1)
#define ADC_LL_DIGI_SAMPLE_FREQ_DYNAMIC_CLK_DIV 1
#define ADC_LL_RAW_DATA_WEIGHTED_SUM (1)
/*---------------------------------------------------------------
Differential
---------------------------------------------------------------*/
#define ADC_LL_ZERO_DIFF_CODE (2198)
* oneshot
*-------------------------------------------------------------*/
#define ADC_LL_RTC_MIN_BITWIDTH (17)
#define ADC_LL_RTC_MAX_BITWIDTH (17)
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
/*---------------------------------------------------------------
Oneshot
---------------------------------------------------------------*/
#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
* continuous
*-------------------------------------------------------------*/
#define ADC_LL_SAMPLE_FREQ_THRES_HIGH (83333U)
#define ADC_LL_SAMPLE_FREQ_THRES_LOW (611U)
#define ADC_LL_DIG_SUPPORTED_UNIT(UNIT) (1)
#define ADC_LL_DIGI_CONTROLLER_NUM (2)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 4
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 4
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_POWER_MANAGE_SUPPORTED 1
#define ADC_LL_POWER_MANAGE_SUPPORTED 1
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DEFAULT_CONV_LIMIT_EN (0)
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM (255)
#define ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER (0)
#define ADC_LL_PWDET_CCT_DEFAULT (4)
#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_LL_FSM_START_WAIT_DEFAULT (5)
#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_LL_DEFAULT_CONV_LIMIT_EN (0)
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM (255)
#define ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER (0)
/*---------------------------------------------------------------
* calibration
*-------------------------------------------------------------*/
#define ADC_LL_ZERO_DIFF_CODE (2198)
#define ADC_LL_PWDET_CCT_DEFAULT (4)
typedef enum {
ADC_LL_CTRL_DIG = 0, ///< S31 uses unified digital controller
@@ -531,7 +542,7 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits)
{
(void)adc_n;
HAL_ASSERT(bits == SOC_ADC_RTC_MAX_BITWIDTH || bits == ADC_BITWIDTH_DEFAULT);
HAL_ASSERT(bits == ADC_LL_RTC_MAX_BITWIDTH || bits == ADC_BITWIDTH_DEFAULT);
}
/**
components/esp_hal_ana_conv/include/hal/adc_oneshot_hal.h
+2 -1
View File
@@ -8,6 +8,7 @@
#include "hal/adc_types.h"
#include "hal/adc_hal_common.h"
#include "hal/adc_ll.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
@@ -40,7 +41,7 @@ typedef struct adc_oneshot_hal_ctx_t {
adc_oneshot_soc_handle_t dev; ///< ADC SoC layer handle
adc_unit_t unit; ///< ADC unit
adc_hal_work_mode_t work_mode; ///< ADC work mode
adc_oneshot_hal_chan_cfg_t chan_configs[SOC_ADC_MAX_CHANNEL_NUM]; ///< ADC configurations per channel
adc_oneshot_hal_chan_cfg_t chan_configs[ADC_LL_MAX_CHANNEL_NUM]; ///< ADC configurations per channel
adc_oneshot_clk_src_t clk_src; ///< Clock source
uint32_t clk_src_freq_hz; ///< Clock source frequency in hz
bool disable_dac_output; ///< Whether to disable DAC output, only for chips supporting DAC
components/esp_hal_ana_conv/include/hal/adc_periph.h
+2 -1
View File
@@ -10,6 +10,7 @@
#include "soc/soc_caps.h"
#if SOC_ADC_SUPPORTED
#include "soc/adc_channel.h"
#include "hal/adc_ll.h"
#endif
#ifdef __cplusplus
@@ -23,7 +24,7 @@ extern "C" {
* - >=0 : GPIO number index.
* - -1 : Not support.
*/
extern const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM];
extern const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][ADC_LL_MAX_CHANNEL_NUM];
#ifdef __cplusplus
}
components/esp_hw_support/adc_share_hw_ctrl.c
+1 -1
View File
@@ -103,7 +103,7 @@ void IRAM_ATTR adc_set_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten)
}
#if SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED
static int s_adc_cali_chan_compens[SOC_ADC_MAX_CHANNEL_NUM][SOC_ADC_ATTEN_NUM] = {};
static int s_adc_cali_chan_compens[ADC_LL_MAX_CHANNEL_NUM][SOC_ADC_ATTEN_NUM] = {};
void adc_load_hw_calibration_chan_compens(adc_unit_t adc_n, adc_channel_t chan, adc_atten_t atten)
{
int version = esp_efuse_rtc_calib_get_ver();
components/soc/esp32/include/soc/Kconfig.soc_caps.in
-24
View File
@@ -231,18 +231,10 @@ config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 10
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 16
@@ -267,22 +259,6 @@ config SOC_ADC_DIGI_MONITOR_NUM
int
default 0
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 2000000
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 20000
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 9
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_SHARED_POWER
bool
default y
components/soc/esp32/include/soc/soc_caps.h
-9
View File
@@ -131,26 +131,17 @@
#define SOC_ADC_RTC_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) ((UNIT == 0) ? 1 : 0)
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16) //Two pattern table, each contains 16 items. Each item takes 1 byte. But only support ADC1 using DMA mode
#define SOC_ADC_DIGI_MIN_BITWIDTH (9)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_RESULT_BYTES (2)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
#define SOC_ADC_DIGI_MONITOR_NUM (0U) // to reference `IDF_TARGET_SOC_ADC_DIGI_MONITOR_NUM` in document
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH (2000000)
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW (20000)
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (9)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< ADC power control is shared by PWDET */
#define SOC_ADC_SHARED_POWER 1
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
-28
View File
@@ -175,18 +175,10 @@ config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
@@ -199,30 +191,10 @@ config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32c2/include/soc/soc_caps.h
-12
View File
@@ -70,27 +70,15 @@
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
-28
View File
@@ -251,18 +251,10 @@ config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
@@ -283,30 +275,10 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_DIGI_IIR_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32c3/include/soc/soc_caps.h
-12
View File
@@ -97,29 +97,17 @@
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) ((UNIT == 0) ? 1 : 0) //Digital controller supported ADC unit
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+2 -30
View File
@@ -359,33 +359,21 @@ config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 6
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 2
default 12
config SOC_ADC_DIGI_MONITOR_NUM
int
@@ -399,22 +387,6 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1 -13
View File
@@ -122,30 +122,18 @@
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (6)
#define SOC_ADC_MAX_CHANNEL_NUM (6)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+2 -30
View File
@@ -307,33 +307,21 @@ config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 7
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 2
default 12
config SOC_ADC_DIGI_MONITOR_NUM
int
@@ -347,22 +335,6 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+1 -13
View File
@@ -107,30 +107,18 @@
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7)
#define SOC_ADC_MAX_CHANNEL_NUM (7)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+2 -30
View File
@@ -223,33 +223,21 @@ config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 4
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 2
default 12
config SOC_ADC_DIGI_MONITOR_NUM
int
@@ -263,22 +251,6 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
+1 -13
View File
@@ -81,30 +81,18 @@
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_MAX_CHANNEL_NUM (4)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (4)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+2 -30
View File
@@ -307,33 +307,21 @@ config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 2
default 12
config SOC_ADC_DIGI_MONITOR_NUM
int
@@ -347,22 +335,6 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+1 -12
View File
@@ -124,29 +124,18 @@
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+2 -30
View File
@@ -275,33 +275,21 @@ config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 2
default 12
config SOC_ADC_DIGI_MONITOR_NUM
int
@@ -315,22 +303,6 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_TEMPERATURE_SHARE_INTR
bool
default y
components/soc/esp32h21/include/soc/soc_caps.h
+1 -12
View File
@@ -108,29 +108,18 @@
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+2 -30
View File
@@ -287,33 +287,21 @@ config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 2
default 12
config SOC_ADC_DIGI_MONITOR_NUM
int
@@ -327,22 +315,6 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_TEMPERATURE_SHARE_INTR
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+1 -13
View File
@@ -115,30 +115,18 @@
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+2 -30
View File
@@ -439,33 +439,21 @@ config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 8
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 16
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 2
default 12
config SOC_ADC_DIGI_MONITOR_NUM
int
@@ -479,22 +467,6 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+1 -13
View File
@@ -143,30 +143,18 @@
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
// #define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 6)
#define SOC_ADC_MAX_CHANNEL_NUM (8)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16) /*!< Four pattern tables, each contains 4 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
-28
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@@ -283,18 +283,10 @@ config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 10
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 32
@@ -307,10 +299,6 @@ config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_RESULT_BYTES
int
default 2
@@ -323,22 +311,6 @@ config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 13
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 13
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
-12
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@@ -117,29 +117,17 @@
#define SOC_ADC_DIG_IIR_FILTER_UNIT_BINDED 1 //ADC filter is binded with the ADC unit
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(UNIT) (10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (32) /*!< Two pattern table, each contains 16 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (2)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (13)
#define SOC_ADC_RTC_MAX_BITWIDTH (13)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
-28
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@@ -319,18 +319,10 @@ config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 10
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 24
@@ -351,30 +343,10 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_DIGI_IIR_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
-12
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@@ -113,29 +113,17 @@
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) ((UNIT == 0) ? 1 : 0) //Digital controller supported ADC unit
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (24) //Two pattern table, each contains 12 items. Each item takes 1 byte
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
-24
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@@ -419,30 +419,14 @@ config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 8
config SOC_ADC_ATTEN_NUM
int
default 1
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 17
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 17
config SOC_ADC_DMA_SUPPORTED
bool
default y
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 16
@@ -463,14 +447,6 @@ config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
components/soc/esp32s31/include/soc/soc_caps.h
-7
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@@ -141,22 +141,15 @@
/*!< SAR ADC Module*/
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_MAX_CHANNEL_NUM (8)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (8)
#define SOC_ADC_ATTEN_NUM (1U)
#define SOC_ADC_RTC_MIN_BITWIDTH (17)
#define SOC_ADC_RTC_MAX_BITWIDTH (17)
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_DIGI_MIN_BITWIDTH (17)
#define SOC_ADC_DIGI_MAX_BITWIDTH (17)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) (1)
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH (83333U)
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW (611U)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIFF_SUPPORTED (1)