A peripheral's reset also resets the ones it occupies, so a lock has to cover
both. Gate the ECDSA MPI lock on SOC_ECDSA_USES_MPI rather than the runtime
ecdsa_ll_is_mpi_required() and set that capability on C5, lock the Key Manager
path in esp_key_mgr.c, clean HMAC after its reset, and enable DS before the
primitives its reset covers.
- Also add RNG LL-APIs for ESP32-C61
- Add SOC_RNG_CLOCK_IS_INDEPENDENT for ESP32-C61: now that
rng_ll_disable() actually clears the RNG clock gate, the application
needs the esp_hw_support startup hook to re-enable the RNG after
bootloader_random_disable()
Every other SOC_*_HIGH macro in soc.h is an exclusive region end;
SOC_RAM_ICACHE1_HIGH was the inclusive last byte (0x40867fff). This
also made the reclaimed ICache1 heap region in single core mode
(components/heap/port/esp32h4/memory_layout.c, sized as HIGH - LOW)
one byte short. Change the value to the exclusive end 0x40868000 and
drop the +1 compensation at the SOC_HP_RAM_HIGH definition.
Both PSRAM layouts were mapped as a single RWX window, so everything in external
RAM - the heap included - was executable.
PSRAM used as data only is now RW, and under XIP-from-PSRAM it is split per
section as ESP32-P4 does: .text RX, .rodata read-only, and the MMU-page
alignment gaps and the reclaimed heap RW, so neither is executable.
Both describe the layout that esp_psram_init() produces, and the entries are
locked, so - again as on ESP32-P4 - they are only narrowed when
CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION says that layout applies. Without
it the application owns the region and PSRAM stays RWX.
The per-section entries cost one PMP entry more than the 16 available, so the CPU
subsystem and peripheral windows are chained as TOR entries, taking one entry
instead of three.
soc.h is corrected against the S31 bus address map: the peripheral window base
was 1 MB too low, and the LP peripheral top, derived from a register base plus a
size rather than from the map, was 16 KB short. SOC_NON_CACHEABLE_OFFSET_FLASH
is added.
ESP32-S31 uses the same trace encoder IP as ESP32-P4. Of the E-Trace v2.0
parameters the two targets report, only privilege_width_p differs (1 on P4,
2 on S31), and it affects both the sync packet layout and the filter's
privilege selector.
- Add the SOC_RISCV_TRACE_* caps for ESP32-S31 along with the esp32s31 LL, and
declare TRACE0/TRACE1 in the target's trace_struct.h.
- Carry privilege_width_p as SOC_RISCV_TRACE_PRIV_WIDTH so the sync packet
decoder can locate the address field, which starts one bit later on targets
that implement supervisor mode.
- Use the RISC-V architectural privilege encoding (0 user, 1 supervisor,
3 machine) in the public filter enum so the values do not change per target,
and let each LL narrow them to its own register field.
- Add riscv_trace_ll_priv_is_supported() per target, so a privilege level the
selector cannot represent is rejected with ESP_ERR_NOT_SUPPORTED rather than
being silently narrowed to a different level. It lives next to the narrowing
code so the two cannot drift apart.
- Fix trace buffer allocation on targets whose internal RAM is not reached
through a cache. esp_cache_get_alignment() reports 0 there, which underflowed
the size check and failed every allocation. Align base and size to the larger
of the reported cache line and the encoder's 4-byte write granularity.
harshal.patil
Mahavir Jain
morris
nilesh.kale
Jiang Jiang Jian
wanckl
Konstantin Kondrashov
Erhan KurubasandCursor
Hu Rui
wuzhenghui
Laukik Hase
Armando (Dou Yiwen)
hebinglin
Chen Jichang
Island
cjin
Michael (XIAO Xufeng)
Gao Xu