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Merge branch 'refactor/formate_old_spi_struct_new_style' into 'master'

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refactor(driver_spi): re-generate old spi struct header in new style

See merge request espressif/esp-idf!52270
This commit is contained in:
morris
2026-09-04 14:16:13 +08:00
parent df2192b38f 236a12a51b
commit 0ae0276b35
21 changed files with 6400 additions and 2076 deletions
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components/esp_hal_gpspi/esp32/include/hal/spi_ll.h
-1
View File
@@ -1300,7 +1300,6 @@ static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode)
return 0;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
#ifdef __cplusplus
components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h
+31 -32
View File
@@ -199,9 +199,9 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
hw->clk_gate.mst_clk_sel = 1;
hw->dma_conf.val = 0;
hw->dma_conf.tx_seg_trans_clr_en = 1;
hw->dma_conf.rx_seg_trans_clr_en = 1;
hw->dma_conf.dma_seg_trans_en = 0;
hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
hw->dma_conf.dma_slv_seg_trans_en = 0;
}
/**
@@ -226,7 +226,7 @@ static inline void spi_ll_slave_init(spi_dev_t *hw)
// Configure DMA In-Link to not be terminated when transaction bit counter exceeds
hw->dma_conf.rx_eof_en = 0;
hw->dma_conf.dma_seg_trans_en = 0;
hw->dma_conf.dma_slv_seg_trans_en = 0;
//Disable unneeded ints
hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK;
@@ -283,7 +283,7 @@ static inline void spi_ll_apply_config(spi_dev_t *hw)
*/
static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
{
return hw->dma_int_raw.trans_done;
return hw->dma_int_raw.trans_done_int_raw;
}
/**
@@ -374,7 +374,7 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw)
*/
static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
{
hw->dma_int_clr.infifo_full_err = 1;
hw->dma_int_clr.dma_infifo_full_err_int_clr = 1;
}
/**
@@ -384,7 +384,7 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
*/
static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw)
{
hw->dma_int_clr.outfifo_empty_err = 1;
hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1;
}
/*------------------------------------------------------------------------------
@@ -672,7 +672,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li
*/
static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans)
{
hw->dma_conf.dma_seg_trans_en = seg_trans;
hw->dma_conf.dma_slv_seg_trans_en = seg_trans;
}
/**
@@ -1004,11 +1004,11 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen,
*/
addr = HAL_SWAP32(addr);
//otherwise only addr register is sent
hw->addr = addr;
hw->addr.val = addr;
} else {
// shift the address to MSB of addr register.
// output address will be sent from MSB to LSB of addr register
hw->addr = addr << (32 - addrlen);
hw->addr.val = addr << (32 - addrlen);
}
}
@@ -1084,7 +1084,7 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
*/
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
{
return hw->slave1.data_bitlen;
return hw->slave1.slv_data_bitlen;
}
/*------------------------------------------------------------------------------
@@ -1093,16 +1093,16 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
//helper macros to generate code for each interrupts
#define FOR_EACH_ITEM(op, list) do { list(op) } while(0)
#define INTR_LIST(item) \
item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \
item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done, dma_int_set.rd_buf_done_int_set) \
item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done, dma_int_set.wr_buf_done_int_set) \
item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done, dma_int_set.rd_dma_done_int_set) \
item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done, dma_int_set.wr_dma_done_int_set) \
item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \
item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7, dma_int_set.cmd7_int_set) \
item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8, dma_int_set.cmd8_int_set) \
item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9, dma_int_set.cmd9_int_set) \
item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda, dma_int_set.cmda_int_set)
item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr, dma_int_set.trans_done_int_set) \
item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr, dma_int_set.slv_rd_buf_done_int_set) \
item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr, dma_int_set.slv_wr_buf_done_int_set) \
item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr, dma_int_set.slv_rd_dma_done_int_set) \
item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr, dma_int_set.slv_wr_dma_done_int_set) \
item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr, dma_int_set.dma_seg_trans_done_int_set) \
item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr, dma_int_set.slv_cmd7_int_set) \
item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr, dma_int_set.slv_cmd8_int_set) \
item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr, dma_int_set.slv_cmd9_int_set) \
item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr, dma_int_set.slv_cmda_int_set)
static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
{
@@ -1150,7 +1150,7 @@ static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
*/
static inline void spi_ll_disable_int(spi_dev_t *hw)
{
hw->dma_int_ena.trans_done = 0;
hw->dma_int_ena.trans_done_int_ena = 0;
}
/**
@@ -1160,7 +1160,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw)
*/
static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
{
hw->dma_int_clr.trans_done = 1;
hw->dma_int_clr.trans_done_int_clr = 1;
}
/**
@@ -1180,7 +1180,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw)
*/
static inline void spi_ll_enable_int(spi_dev_t *hw)
{
hw->dma_int_ena.trans_done = 1;
hw->dma_int_ena.trans_done_int_ena = 1;
}
/*------------------------------------------------------------------------------
@@ -1188,20 +1188,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw)
*----------------------------------------------------------------------------*/
static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask)
{
hw->slave.rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
}
static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw)
{
return hw->slave1.data_bitlen / 8;
return hw->slave1.slv_data_bitlen / 8;
}
static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
{
return hw->slave1.last_addr;
return hw->slave1.slv_last_addr;
}
/**
@@ -1574,7 +1574,7 @@ __attribute__((always_inline))
static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer)
{
conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28);
conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr;
conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.val;
conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl.val;
conf_buffer[SPI_LL_CLOCK_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->clock.val;
conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->user.val;
@@ -1612,7 +1612,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
hw->slave.dma_seg_magic_value = magic_value;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
#ifdef __cplusplus
components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h
+32 -33
View File
@@ -204,9 +204,9 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
hw->clk_gate.mst_clk_sel = 1;
hw->dma_conf.val = 0;
hw->dma_conf.tx_seg_trans_clr_en = 1;
hw->dma_conf.rx_seg_trans_clr_en = 1;
hw->dma_conf.dma_seg_trans_en = 0;
hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
hw->dma_conf.dma_slv_seg_trans_en = 0;
}
/**
@@ -231,7 +231,7 @@ static inline void spi_ll_slave_init(spi_dev_t *hw)
// Configure DMA In-Link to not be terminated when transaction bit counter exceeds
hw->dma_conf.rx_eof_en = 0;
hw->dma_conf.dma_seg_trans_en = 0;
hw->dma_conf.dma_slv_seg_trans_en = 0;
//Disable unneeded ints
hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK;
@@ -288,7 +288,7 @@ static inline void spi_ll_apply_config(spi_dev_t *hw)
*/
static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
{
return hw->dma_int_raw.trans_done;
return hw->dma_int_raw.trans_done_int_raw;
}
/**
@@ -379,7 +379,7 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw)
*/
static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
{
hw->dma_int_clr.infifo_full_err = 1;
hw->dma_int_clr.dma_infifo_full_err_int_clr = 1;
}
/**
@@ -389,7 +389,7 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
*/
static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw)
{
hw->dma_int_clr.outfifo_empty_err = 1;
hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1;
}
/*------------------------------------------------------------------------------
@@ -677,7 +677,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li
*/
static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans)
{
hw->dma_conf.dma_seg_trans_en = seg_trans;
hw->dma_conf.dma_slv_seg_trans_en = seg_trans;
}
/**
@@ -1009,11 +1009,11 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen,
*/
addr = HAL_SWAP32(addr);
//otherwise only addr register is sent
hw->addr = addr;
hw->addr.val = addr;
} else {
// shift the address to MSB of addr register.
// output address will be sent from MSB to LSB of addr register
hw->addr = addr << (32 - addrlen);
hw->addr.val = addr << (32 - addrlen);
}
}
@@ -1089,7 +1089,7 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
*/
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
{
return hw->slave1.data_bitlen;
return hw->slave1.slv_data_bitlen;
}
/*------------------------------------------------------------------------------
@@ -1098,16 +1098,16 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
//helper macros to generate code for each interrupts
#define FOR_EACH_ITEM(op, list) do { list(op) } while(0)
#define INTR_LIST(item) \
item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done=1) \
item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done=1) \
item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done=1) \
item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done=1) \
item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done=1) \
item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done=1) \
item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \
item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \
item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9=1) \
item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda=1)
item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr=1) \
item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr=1) \
item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr=1) \
item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr=1) \
item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr=1) \
item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr=1) \
item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr=1) \
item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr=1) \
item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr=1) \
item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr=1)
static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
{
@@ -1155,7 +1155,7 @@ static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
*/
static inline void spi_ll_disable_int(spi_dev_t *hw)
{
hw->dma_int_ena.trans_done = 0;
hw->dma_int_ena.trans_done_int_ena = 0;
}
/**
@@ -1165,7 +1165,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw)
*/
static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
{
hw->dma_int_raw.trans_done = 0;
hw->dma_int_raw.trans_done_int_raw = 0;
}
/**
@@ -1175,7 +1175,7 @@ static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
*/
static inline void spi_ll_set_int_stat(spi_dev_t *hw)
{
hw->dma_int_raw.trans_done = 1;
hw->dma_int_raw.trans_done_int_raw = 1;
}
/**
@@ -1185,7 +1185,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw)
*/
static inline void spi_ll_enable_int(spi_dev_t *hw)
{
hw->dma_int_ena.trans_done = 1;
hw->dma_int_ena.trans_done_int_ena = 1;
}
/*------------------------------------------------------------------------------
@@ -1193,20 +1193,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw)
*----------------------------------------------------------------------------*/
static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask)
{
hw->slave.rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
}
static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw)
{
return hw->slave1.data_bitlen / 8;
return hw->slave1.slv_data_bitlen / 8;
}
static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
{
return hw->slave1.last_addr;
return hw->slave1.slv_last_addr;
}
/*------------------------------------------------------------------------------
@@ -1493,7 +1493,7 @@ __attribute__((always_inline))
static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer)
{
conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28);
conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr;
conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.val;
conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl.val;
conf_buffer[SPI_LL_CLOCK_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->clock.val;
conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->user.val;
@@ -1531,7 +1531,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
hw->slave.dma_seg_magic_value = magic_value;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h
-1
View File
@@ -1220,7 +1220,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
return hw->slave1.slv_last_addr;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h
-1
View File
@@ -1516,7 +1516,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
hw->slave.dma_seg_magic_value = magic_value;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h
-1
View File
@@ -1220,7 +1220,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
return hw->slave1.slv_last_addr;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h
-1
View File
@@ -1523,7 +1523,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
hw->slave.dma_seg_magic_value = magic_value;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h
+2
View File
@@ -1597,6 +1597,8 @@ static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode)
return 8;
}
#undef SPI_LL_UNUSED_INT_MASK
#ifdef __cplusplus
}
#endif
components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h
-1
View File
@@ -1241,7 +1241,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
return hw->slave1.slv_last_addr;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h
-1
View File
@@ -1302,7 +1302,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
return hw->slave1.slv_last_addr;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h
+43 -44
View File
@@ -384,8 +384,8 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw)
*/
static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
{
hw->dma_conf.infifo_full_clr = 1;
hw->dma_conf.infifo_full_clr = 0;
hw->dma_conf.dma_infifo_full_clr = 1;
hw->dma_conf.dma_infifo_full_clr = 0;
}
/**
@@ -395,8 +395,8 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
*/
static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw)
{
hw->dma_conf.outfifo_empty_clr = 1;
hw->dma_conf.outfifo_empty_clr = 0;
hw->dma_conf.dma_outfifo_empty_clr = 1;
hw->dma_conf.dma_outfifo_empty_clr = 0;
}
/*------------------------------------------------------------------------------
@@ -670,7 +670,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li
static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans)
{
hw->dma_conf.dma_seg_trans_en = seg_trans;
hw->dma_conf.dma_slv_seg_trans_en = seg_trans;
}
/**
@@ -930,7 +930,7 @@ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup)
*/
static inline void spi_ll_slave_set_seg_en(spi_dev_t *hw, bool en)
{
hw->dma_conf.dma_seg_trans_en = en;
hw->dma_conf.dma_slv_seg_trans_en = en;
}
/*------------------------------------------------------------------------------
@@ -944,7 +944,7 @@ static inline void spi_ll_slave_set_seg_en(spi_dev_t *hw, bool en)
*/
static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen)
{
hw->miso_dlen.usr_miso_bit_len = bitlen - 1;
hw->miso_dlen.usr_miso_dbitlen = bitlen - 1;
}
/**
@@ -955,7 +955,7 @@ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen)
*/
static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen)
{
hw->mosi_dlen.usr_mosi_bit_len = bitlen - 1;
hw->mosi_dlen.usr_mosi_dbitlen = bitlen - 1;
}
/**
@@ -1042,11 +1042,11 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen,
*/
addr = HAL_SWAP32(addr);
//otherwise only addr register is sent
hw->addr = addr;
hw->addr.val = addr;
} else {
// shift the address to MSB of addr register.
// output address will be sent from MSB to LSB of addr register
hw->addr = addr << (32 - addrlen);
hw->addr.val = addr << (32 - addrlen);
}
}
@@ -1116,7 +1116,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
*/
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
{
return hw->slv_rd_byte.data_bytelen * 8;
return hw->slv_rd_byte.slv_data_bytelen * 8;
}
/*------------------------------------------------------------------------------
@@ -1126,21 +1126,21 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
#define FOR_EACH_ITEM(op, list) do { list(op) } while(0)
#define INTR_LIST(item) \
item(SPI_LL_INTR_TRANS_DONE, slave.int_trans_done_en, slave.trans_done, slave.trans_done=0) \
item(SPI_LL_INTR_RDBUF, slave.int_rd_buf_done_en, slv_rdbuf_dlen.rd_buf_done, slv_rdbuf_dlen.rd_buf_done=0) \
item(SPI_LL_INTR_WRBUF, slave.int_wr_buf_done_en, slv_wrbuf_dlen.wr_buf_done, slv_wrbuf_dlen.wr_buf_done=0) \
item(SPI_LL_INTR_RDDMA, slave.int_rd_dma_done_en, slv_rd_byte.rd_dma_done, slv_rd_byte.rd_dma_done=0) \
item(SPI_LL_INTR_WRDMA, slave.int_wr_dma_done_en, slave1.wr_dma_done, slave1.wr_dma_done=0) \
item(SPI_LL_INTR_RDBUF, slave.int_rd_buf_done_en, slv_rdbuf_dlen.slv_rd_buf_done, slv_rdbuf_dlen.slv_rd_buf_done=0) \
item(SPI_LL_INTR_WRBUF, slave.int_wr_buf_done_en, slv_wrbuf_dlen.slv_wr_buf_done, slv_wrbuf_dlen.slv_wr_buf_done=0) \
item(SPI_LL_INTR_RDDMA, slave.int_rd_dma_done_en, slv_rd_byte.slv_rd_dma_done, slv_rd_byte.slv_rd_dma_done=0) \
item(SPI_LL_INTR_WRDMA, slave.int_wr_dma_done_en, slave1.slv_wr_dma_done, slave1.slv_wr_dma_done=0) \
item(SPI_LL_INTR_SEG_DONE, slave.int_dma_seg_trans_en, hold.dma_seg_trans_done, hold.dma_seg_trans_done=0) \
item(SPI_LL_INTR_IN_SUC_EOF, dma_int_ena.in_suc_eof, dma_int_raw.in_suc_eof, dma_int_clr.in_suc_eof=1) \
item(SPI_LL_INTR_OUT_EOF, dma_int_ena.out_eof, dma_int_raw.out_eof, dma_int_clr.out_eof=1) \
item(SPI_LL_INTR_OUT_TOTAL_EOF, dma_int_ena.out_total_eof, dma_int_raw.out_total_eof, dma_int_clr.out_total_eof=1) \
item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err=1) \
item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err, dma_int_raw.outfifo_empty_err, dma_int_clr.outfifo_empty_err=1) \
item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \
item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \
item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9=1) \
item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda=1) \
item(SPI_LL_INTR_OUT_DONE, dma_int_ena.out_done, dma_int_raw.out_done, dma_int_clr.out_done=1)
item(SPI_LL_INTR_IN_SUC_EOF, dma_int_ena.in_suc_eof_int_ena, dma_int_raw.in_suc_eof_int_raw, dma_int_clr.in_suc_eof_int_clr=1) \
item(SPI_LL_INTR_OUT_EOF, dma_int_ena.out_eof_int_ena, dma_int_raw.out_eof_int_raw, dma_int_clr.out_eof_int_clr=1) \
item(SPI_LL_INTR_OUT_TOTAL_EOF, dma_int_ena.out_total_eof_int_ena, dma_int_raw.out_total_eof_int_raw, dma_int_clr.out_total_eof_int_clr=1) \
item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err_int_ena, dma_int_raw.infifo_full_err_int_raw, dma_int_clr.infifo_full_err_int_clr=1) \
item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err_int_ena, dma_int_raw.outfifo_empty_err_int_raw, dma_int_clr.outfifo_empty_err_int_clr=1) \
item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr=1) \
item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr=1) \
item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr=1) \
item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr=1) \
item(SPI_LL_INTR_OUT_DONE, dma_int_ena.out_done_int_ena, dma_int_raw.out_done_int_raw, dma_int_clr.out_done_int_clr=1)
__attribute__((always_inline))
static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
@@ -1230,20 +1230,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw)
*----------------------------------------------------------------------------*/
static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask)
{
hw->slv_rd_byte.rdbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
hw->slv_rd_byte.wrbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slv_rd_byte.rddma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slv_rd_byte.wrdma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
hw->slv_rd_byte.slv_rdbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
hw->slv_rd_byte.slv_wrbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slv_rd_byte.slv_rddma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slv_rd_byte.slv_wrdma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
}
static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw)
{
return hw->slv_rd_byte.data_bytelen;
return hw->slv_rd_byte.slv_data_bytelen;
}
static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
{
return HAL_FORCE_READ_U32_REG_FIELD(hw->slave1, last_addr);
return HAL_FORCE_READ_U32_REG_FIELD(hw->slave1, slv_last_addr);
}
/*------------------------------------------------------------------------------
@@ -1343,8 +1343,8 @@ static inline void spi_ll_dma_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel)
__attribute__((always_inline))
static inline void spi_ll_dma_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, void *addr)
{
dma_in->dma_in_link.addr = (int) addr & 0xFFFFF;
dma_in->dma_in_link.start = 1;
dma_in->dma_in_link.inlink_addr = (int) addr & 0xFFFFF;
dma_in->dma_in_link.inlink_start = 1;
}
/**
@@ -1355,7 +1355,7 @@ static inline void spi_ll_dma_rx_start(spi_dma_dev_t *dma_in, uint32_t channel,
*/
static inline void spi_ll_dma_rx_stop(spi_dma_dev_t *dma_in, uint32_t channel)
{
dma_in->dma_in_link.stop = 1;
dma_in->dma_in_link.inlink_stop = 1;
}
/**
@@ -1393,7 +1393,7 @@ __attribute__((always_inline))
static inline uint32_t spi_ll_dma_get_in_suc_eof_desc_addr(spi_dma_dev_t *dma_in, uint32_t channel)
{
ESP_STATIC_ANALYZER_CHECK(!dma_in, -1);
return dma_in->dma_in_suc_eof_des_addr;
return dma_in->in_suc_eof_des_addr.val;
}
/**
@@ -1435,8 +1435,8 @@ static inline void spi_ll_dma_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel)
__attribute__((always_inline))
static inline void spi_ll_dma_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, void *addr)
{
dma_out->dma_out_link.addr = (int) addr & 0xFFFFF;
dma_out->dma_out_link.start = 1;
dma_out->dma_out_link.outlink_addr = (int) addr & 0xFFFFF;
dma_out->dma_out_link.outlink_start = 1;
}
/**
@@ -1447,7 +1447,7 @@ static inline void spi_ll_dma_tx_start(spi_dma_dev_t *dma_out, uint32_t channel,
*/
static inline void spi_ll_dma_tx_stop(spi_dma_dev_t *dma_out, uint32_t channel)
{
dma_out->dma_out_link.stop = 1;
dma_out->dma_out_link.outlink_stop = 1;
}
/**
@@ -1509,17 +1509,17 @@ __attribute__((always_inline))
static inline uint32_t spi_ll_dma_get_out_eof_desc_addr(spi_dma_dev_t *dma_out, uint32_t channel)
{
ESP_STATIC_ANALYZER_CHECK(!dma_out, -1);
return dma_out->dma_out_eof_des_addr;
return dma_out->out_eof_des_addr.val;
}
static inline void spi_ll_dma_rx_restart(spi_dma_dev_t *dma_in, uint32_t channel)
{
dma_in->dma_in_link.restart = 1;
dma_in->dma_in_link.inlink_restart = 1;
}
static inline void spi_ll_dma_tx_restart(spi_dma_dev_t *dma_out, uint32_t channel)
{
dma_out->dma_out_link.restart = 1;
dma_out->dma_out_link.outlink_restart = 1;
}
static inline void spi_ll_dma_rx_disable(spi_dma_dev_t *dma_in)
@@ -1534,7 +1534,7 @@ static inline void spi_ll_dma_tx_disable(spi_dma_dev_t *dma_out)
static inline bool spi_ll_tx_get_empty_err(spi_dev_t *hw)
{
return hw->dma_int_raw.outfifo_empty_err;
return hw->dma_int_raw.outfifo_empty_err_int_raw;
}
/*------------------------------------------------------------------------------
@@ -1861,7 +1861,7 @@ static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer)
{
conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFFFFF | (SPI_LL_SCT_MAGIC_NUMBER << 28);
conf_buffer[SPI_LL_CMD_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->cmd.val;
conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr;
conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.val;
conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl.val;
conf_buffer[SPI_LL_CTRL1_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl1.val;
conf_buffer[SPI_LL_CTRL2_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl2.val;
@@ -1911,7 +1911,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
hw->slv_rd_byte.dma_seg_magic_value = magic_value;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h
+33 -34
View File
@@ -215,9 +215,9 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
hw->clk_gate.mst_clk_sel = 1;
hw->dma_conf.val = 0;
hw->dma_conf.tx_seg_trans_clr_en = 1;
hw->dma_conf.rx_seg_trans_clr_en = 1;
hw->dma_conf.dma_seg_trans_en = 0;
hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
hw->dma_conf.dma_slv_seg_trans_en = 0;
}
/**
@@ -242,7 +242,7 @@ static inline void spi_ll_slave_init(spi_dev_t *hw)
// Configure DMA In-Link to not be terminated when transaction bit counter exceeds
hw->dma_conf.rx_eof_en = 0;
hw->dma_conf.dma_seg_trans_en = 0;
hw->dma_conf.dma_slv_seg_trans_en = 0;
//Disable unneeded ints
hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK;
@@ -299,7 +299,7 @@ static inline void spi_ll_apply_config(spi_dev_t *hw)
*/
static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
{
return hw->dma_int_raw.trans_done;
return hw->dma_int_raw.trans_done_int_raw;
}
/**
@@ -390,7 +390,7 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw)
*/
static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
{
hw->dma_int_clr.infifo_full_err = 1;
hw->dma_int_clr.dma_infifo_full_err_int_clr = 1;
}
/**
@@ -400,7 +400,7 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
*/
static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw)
{
hw->dma_int_clr.outfifo_empty_err = 1;
hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1;
}
/*------------------------------------------------------------------------------
@@ -692,7 +692,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li
*/
static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans)
{
hw->dma_conf.dma_seg_trans_en = seg_trans;
hw->dma_conf.dma_slv_seg_trans_en = seg_trans;
}
/**
@@ -1043,11 +1043,11 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen,
*/
addr = HAL_SWAP32(addr);
//otherwise only addr register is sent
hw->addr = addr;
hw->addr.val = addr;
} else {
// shift the address to MSB of addr register.
// output address will be sent from MSB to LSB of addr register
hw->addr = addr << (32 - addrlen);
hw->addr.val = addr << (32 - addrlen);
}
}
@@ -1124,7 +1124,7 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
*/
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
{
return hw->slave1.data_bitlen;
return hw->slave1.slv_data_bitlen;
}
/*------------------------------------------------------------------------------
@@ -1133,18 +1133,18 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
//helper macros to generate code for each interrupts
#define FOR_EACH_ITEM(op, list) do { list(op) } while(0)
#define INTR_LIST(item) \
item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \
item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err, dma_int_set.infifo_full_err_int_set) \
item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err, dma_int_raw.outfifo_empty_err, dma_int_clr.outfifo_empty_err, dma_int_set.outfifo_empty_err_int_set) \
item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done, dma_int_set.rd_buf_done_int_set) \
item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done, dma_int_set.wr_buf_done_int_set) \
item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done, dma_int_set.rd_dma_done_int_set) \
item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done, dma_int_set.wr_dma_done_int_set) \
item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \
item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7, dma_int_set.cmd7_int_set) \
item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8, dma_int_set.cmd8_int_set) \
item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9, dma_int_set.cmd9_int_set) \
item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda, dma_int_set.cmda_int_set)
item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr, dma_int_set.trans_done_int_set) \
item(SPI_LL_INTR_IN_FULL, dma_int_ena.dma_infifo_full_err_int_ena, dma_int_raw.dma_infifo_full_err_int_raw, dma_int_clr.dma_infifo_full_err_int_clr, dma_int_set.dma_infifo_full_err_int_set) \
item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.dma_outfifo_empty_err_int_ena, dma_int_raw.dma_outfifo_empty_err_int_raw, dma_int_clr.dma_outfifo_empty_err_int_clr, dma_int_set.dma_outfifo_empty_err_int_set) \
item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr, dma_int_set.slv_rd_buf_done_int_set) \
item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr, dma_int_set.slv_wr_buf_done_int_set) \
item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr, dma_int_set.slv_rd_dma_done_int_set) \
item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr, dma_int_set.slv_wr_dma_done_int_set) \
item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr, dma_int_set.dma_seg_trans_done_int_set) \
item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr, dma_int_set.slv_cmd7_int_set) \
item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr, dma_int_set.slv_cmd8_int_set) \
item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr, dma_int_set.slv_cmd9_int_set) \
item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr, dma_int_set.slv_cmda_int_set)
static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
{
@@ -1192,7 +1192,7 @@ static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask)
*/
static inline void spi_ll_disable_int(spi_dev_t *hw)
{
hw->dma_int_ena.trans_done = 0;
hw->dma_int_ena.trans_done_int_ena = 0;
}
/**
@@ -1202,7 +1202,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw)
*/
static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
{
hw->dma_int_clr.trans_done = 1;
hw->dma_int_clr.trans_done_int_clr = 1;
}
/**
@@ -1222,7 +1222,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw)
*/
static inline void spi_ll_enable_int(spi_dev_t *hw)
{
hw->dma_int_ena.trans_done = 1;
hw->dma_int_ena.trans_done_int_ena = 1;
}
/*------------------------------------------------------------------------------
@@ -1230,20 +1230,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw)
*----------------------------------------------------------------------------*/
static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask)
{
hw->slave.rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
}
static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw)
{
return hw->slave1.data_bitlen / 8;
return hw->slave1.slv_data_bitlen / 8;
}
static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
{
return hw->slave1.last_addr;
return hw->slave1.slv_last_addr;
}
/*------------------------------------------------------------------------------
@@ -1535,7 +1535,7 @@ __attribute__((always_inline))
static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer)
{
conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28);
conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr;
conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.val;
conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl.val;
conf_buffer[SPI_LL_CLOCK_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->clock.val;
conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->user.val;
@@ -1573,7 +1573,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
hw->slave.dma_seg_magic_value = magic_value;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h
-1
View File
@@ -1298,7 +1298,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
return hw->slave1.slv_last_addr;
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK
/**
components/esp_hal_mspi/esp32c2/include/hal/gpspi_flash_ll.h
+6 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -48,9 +48,9 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
dev->clk_gate.mst_clk_sel = 1;
dev->dma_conf.val = 0;
dev->dma_conf.tx_seg_trans_clr_en = 1;
dev->dma_conf.rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_seg_trans_en = 0;
dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_slv_seg_trans_en = 0;
}
/**
@@ -336,7 +336,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
{
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen);
dev->addr = (addr << (32 - bitlen)) | padding_ones;
dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
}
/**
@@ -347,7 +347,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
*/
static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
{
dev->addr = addr;
dev->addr.val = addr;
}
/**
components/esp_hal_mspi/esp32c3/include/hal/gpspi_flash_ll.h
+6 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -49,9 +49,9 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
dev->clk_gate.mst_clk_sel = 1;
dev->dma_conf.val = 0;
dev->dma_conf.tx_seg_trans_clr_en = 1;
dev->dma_conf.rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_seg_trans_en = 0;
dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_slv_seg_trans_en = 0;
}
/**
@@ -336,7 +336,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
{
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen);
dev->addr = (addr << (32 - bitlen)) | padding_ones;
dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
}
/**
@@ -347,7 +347,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
*/
static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
{
dev->addr = addr;
dev->addr.val = addr;
}
/**
components/esp_hal_mspi/esp32s2/include/hal/gpspi_flash_ll.h
+5 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -265,7 +265,7 @@ static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock
static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_miso = bitlen > 0;
dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0;
dev->miso_dlen.usr_miso_dbitlen = bitlen ? (bitlen - 1) : 0;
}
/**
@@ -278,7 +278,7 @@ static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitle
static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0;
dev->mosi_dlen.usr_mosi_dbitlen = bitlen ? (bitlen - 1) : 0;
}
/**
@@ -331,7 +331,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
{
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen);
dev->addr = (addr << (32 - bitlen)) | padding_ones;
dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
}
/**
@@ -342,7 +342,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
*/
static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
{
dev->addr = addr;
dev->addr.val = addr;
}
/**
components/esp_hal_mspi/esp32s3/include/hal/gpspi_flash_ll.h
+6 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -55,9 +55,9 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
dev->clk_gate.mst_clk_sel = 1;
dev->dma_conf.val = 0;
dev->dma_conf.tx_seg_trans_clr_en = 1;
dev->dma_conf.rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_seg_trans_en = 0;
dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_slv_seg_trans_en = 0;
}
/**
@@ -342,7 +342,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
{
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen);
dev->addr = (addr << (32 - bitlen)) | padding_ones;
dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
}
/**
@@ -353,7 +353,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
*/
static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
{
dev->addr = addr;
dev->addr.val = addr;
}
/**
components/soc/esp32c2/register/soc/spi_struct.h
+1367 -407
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32c3/register/soc/spi_struct.h
+1259 -352
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32s2/register/soc/spi_struct.h
+2244 -738
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32s3/register/soc/spi_struct.h
+1366 -405
View File
File diff suppressed because it is too large Load Diff