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55,303 Commits 25 Branches 192 Tags
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4503 Commits

Author SHA1 Message Date
Marius Vikhammer
f5e06de75f Merge branch 'bugfix/h4_touch_caps' into 'master' 
fix(soc): use standard touch wakeup cap name on ESP32-H4

See merge request espressif/esp-idf!52093
 2026-09-09 20:43:42 +08:00
harshal.patil
de3a510a18 fix(esp_security): cover the crypto reset coupling in the driver locks 
A peripheral's reset also resets the ones it occupies, so a lock has to cover
both. Gate the ECDSA MPI lock on SOC_ECDSA_USES_MPI rather than the runtime
ecdsa_ll_is_mpi_required() and set that capability on C5, lock the Key Manager
path in esp_key_mgr.c, clean HMAC after its reset, and enable DS before the
primitives its reset covers.
 2026-09-08 14:03:50 +05:30
Mahavir Jain
84a6967aa1 Merge branch 'feat/add_sm3_hash_support_and_testcases' into 'master' 
add SM3 hash support and testcases

See merge request espressif/esp-idf!44830
 2026-09-08 09:02:41 +05:30
morris
ba2b9256e2 Merge branch 'feat/esp32s31_adds_efuse_adc_calib' into 'master' 
feat(efuse): Adds efuse ADC calibration support for ESP32S31

Closes IDF-16140

See merge request espressif/esp-idf!52390
 2026-09-04 15:47:22 +08:00
morris
0ae0276b35 Merge branch 'refactor/formate_old_spi_struct_new_style' into 'master' 
refactor(driver_spi): re-generate old spi struct header in new style

See merge request espressif/esp-idf!52270
 2026-09-04 14:16:13 +08:00
morris
df2192b38f Merge branch 'trace_encoder_hw_params' into 'master' 
Trace encoder hw params

See merge request espressif/esp-idf!52338
 2026-09-04 13:42:31 +08:00
nilesh.kale
7f413c914d feat(sha): add SM3 hardware support 
Enable hardware SM3 digest support on ESP32-H4, ESP32-S31 and ESP32-C5
via the SHA peripheral (mode 14).
 2026-09-04 11:24:39 +08:00
Jiang Jiang Jian
4b2669edde Merge branch 'feat/pm_components_ram_optimize' into 'master' 
feat(pm): pm components ram optimize

Closes PM-840

See merge request espressif/esp-idf!51672
 2026-09-04 10:32:26 +08:00
wanckl
236a12a51b fix(driver_spi): re-generate spi_struct header for old chip 2026-09-03 21:24:52 +08:00
Konstantin Kondrashov
1a814e95c3 feat(efuse): Adds efuse ADC calibration support for ESP32S31 2026-09-03 14:03:25 +03:00
Erhan Kurubas
5b4a90da6e feat(soc): Add RISC-V trace ecause width and packet format caps 
Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-03 08:20:11 +02:00
morris
45dbcfafd0 Merge branch 'test/touch_sleep_ci' into 'master' 
test(touch): Clean up the touch sensor test app and remove unused LL functions

See merge request espressif/esp-idf!48484
 2026-09-02 17:50:25 +08:00
Hu Rui
207a508b9b test(touch): Clean up the touch sensor test app and remove unused LL functions 2026-09-02 15:39:02 +08:00
Mahavir Jain
a3192567d5 Merge branch 'feat/cpu_region_protection_h4' into 'master' 
Memory region protection for ESP32-H4

Closes IDF-12588

See merge request espressif/esp-idf!47070
 2026-08-31 17:41:52 +05:30
wuzhenghui
11c590c053 change(esp_hw_support): optimize retention driver RAM cost 2026-08-31 15:26:18 +08:00
Laukik Hase
52a6ad71ee feat(hal): Add LL-API to check whether RNG is enabled 
- Also add RNG LL-APIs for ESP32-C61
- Add SOC_RNG_CLOCK_IS_INDEPENDENT for ESP32-C61: now that
  rng_ll_disable() actually clears the RNG clock gate, the application
  needs the esp_hw_support startup hook to re-enable the RNG after
  bootloader_random_disable()
 2026-08-28 10:20:54 +05:30
Marius Vikhammer
01582e0f12 fix(soc): use standard touch wakeup cap name on ESP32-H4 
The H4-only spelling was unread, so touch wakeup never compiled in.
 2026-08-26 16:43:53 +08:00
harshal.patil
a7f4dbf35a fix(soc): make SOC_RAM_ICACHE1_HIGH an exclusive bound on ESP32-H4 
Every other SOC_*_HIGH macro in soc.h is an exclusive region end;
SOC_RAM_ICACHE1_HIGH was the inclusive last byte (0x40867fff). This
also made the reclaimed ICache1 heap region in single core mode
(components/heap/port/esp32h4/memory_layout.c, sized as HIGH - LOW)
one byte short. Change the value to the exclusive end 0x40868000 and
drop the +1 compensation at the SOC_HP_RAM_HIGH definition.
 2026-08-25 10:40:28 +05:30
harshal.patil
07debe6edc feat(esp_hw_support): Memory region protection for ESP32-H4 2026-08-25 10:40:28 +05:30
morris
cd356d592d refactor(adc): move channel count to adc LL 2026-08-25 12:30:52 +08:00
Armando (Dou Yiwen)
b532be2707 Merge branch 'fix/fix_mpll_cali_flow_s31' into 'master' 
mpll: improved mpll calibration flow on s31

See merge request espressif/esp-idf!51928
 2026-08-25 02:48:14 +00:00
morris
e93e858123 Merge branch 'fix/ci_h4_enable_spi_test' into 'master' 
fix(driver_spi): ci enable h4 generic test

Closes IDF-15615

See merge request espressif/esp-idf!51937
 2026-08-24 15:48:35 +08:00
morris
7b9cc1ac79 Merge branch 'refactor/dac_priv_dma_callbacks' into 'master' 
refactor(dac): move DMA interrupt handling behind dac_priv_dma callbacks

See merge request espressif/esp-idf!51860
 2026-08-24 10:23:51 +08:00
Armando (Dou Yiwen)
9726078b55 fix(mpll): improved mpll calibration flow on esp32s31 
Signed-off-by: Armando (Dou Yiwen) <douyiwen@espressif.com>
 2026-08-24 09:34:36 +08:00
wanckl
4cf27f5e88 fix(driver_spi): ci enable h4 generic test 2026-08-21 19:39:57 +08:00
Hu Rui
18e0614798 refactor(dac): move DMA interrupt handling behind dac_priv_dma callbacks 2026-08-21 18:53:09 +08:00
morris
1c13ed9bf3 Merge branch 'fix/esp_idf_h4_pmu_icg_mapping' into 'master' 
fix(esp_hw_support): pmu_icg_mapping define mistake

See merge request espressif/esp-idf!51905
 2026-08-21 11:49:03 +08:00
Jiang Jiang Jian
9ad859a1e4 Merge branch 'fix/esp32s31_cpu_clk_src_dependency' into 'master' 
fix(esp_hw_support): fix esp32s31 cpu clk src dependency

Closes BT-4455

See merge request espressif/esp-idf!51572
 2026-08-20 20:53:03 +08:00
morris
d8df109e32 Merge branch 'feat/spi_master_ddr_mode' into 'master' 
feat(driver_spi): master driver support DDR(DTR) clock mode

Closes IDFGH-12948

See merge request espressif/esp-idf!49810
 2026-08-20 17:40:32 +08:00
hebinglin
27fe024e30 fix(esp_hw_support): pmu_icg_mapping define mistake 2026-08-20 17:23:26 +08:00
morris
fe465ae1fe Merge branch 'fix/psram-ecc-mspi-dma-align' into 'master' 
fix(mspi): handle PSRAM ECC DMA alignment across MSPI users

Closes IDF-15850, IDF-15910, and IDF-15700

See merge request espressif/esp-idf!49987
 2026-08-20 11:51:46 +08:00
wanckl
a9ce9e4abf feat(driver_spi): master driver support DDR(DTR) clock mode 2026-08-19 17:22:45 +08:00
wuzhenghui
4b34a6b250 feat(bootloader): use CPLL/4 as flash default 80M clock source 2026-08-19 16:16:05 +08:00
harshal.patil
01b86f1269 change(esp_hw_support): harden the ESP32-S31 PSRAM region permissions 
Both PSRAM layouts were mapped as a single RWX window, so everything in external
RAM - the heap included - was executable.

PSRAM used as data only is now RW, and under XIP-from-PSRAM it is split per
section as ESP32-P4 does: .text RX, .rodata read-only, and the MMU-page
alignment gaps and the reclaimed heap RW, so neither is executable.

Both describe the layout that esp_psram_init() produces, and the entries are
locked, so - again as on ESP32-P4 - they are only narrowed when
CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION says that layout applies. Without
it the application owns the region and PSRAM stays RWX.

The per-section entries cost one PMP entry more than the 16 available, so the CPU
subsystem and peripheral windows are chained as TOR entries, taking one entry
instead of three.

soc.h is corrected against the S31 bus address map: the peripheral window base
was 1 MB too low, and the LP peripheral top, derived from a register base plus a
size rather than from the map, was 16 KB short. SOC_NON_CACHEABLE_OFFSET_FLASH
is added.
 2026-08-19 09:39:52 +05:30
nilesh.kale
b5891edb9b feat: enable cpu region protection for esp32s31 2026-08-17 19:23:58 +05:30
Chen Jichang
2b8029c775 feat(mspi): split dma and mspi alignment 2026-08-17 16:49:27 +08:00
Island
ac6504cab6 Merge branch 'fix/use_conflict_cb_for_regi2c_when_regdma_rf_is_used' into 'master' 
feat(sleep): applied regi2c conflict process at regdma rf

See merge request espressif/esp-idf!51770
 2026-08-17 14:43:56 +08:00
cjin
5533d153f5 feat(sleep): applied regi2c conflict process at regdma rf 2026-08-14 16:29:55 +08:00
Chen Jichang
f2cf926e0a feat(rgb_lcd): support draw bitmap hook 2026-08-13 14:29:43 +08:00
Michael (XIAO Xufeng)
ea634fc1e9 Merge branch 'fix/fix_mpll_init_flow' into 'master' 
mpll: improved mpll init flow

See merge request espressif/esp-idf!51658
 2026-08-11 21:43:44 +08:00
Erhan Kurubas
114807c981 feat(riscv_trace): add trace support for ESP32-H21 2026-08-11 13:06:45 +02:00
Erhan Kurubas
cde1da8fe6 feat(riscv_trace): add trace support for ESP32-H4 2026-08-11 13:06:45 +02:00
Erhan Kurubas
64d913f86b feat(riscv_trace): add trace support for ESP32-C61 2026-08-11 13:06:45 +02:00
Armando (Dou Yiwen)
81acd9c18f fix(mpll): fix mpll calibration fail bug 2026-08-11 17:57:55 +08:00
Erhan Kurubas
cd89c2b22b feat(riscv_trace): add trace support for ESP32-H2 2026-08-07 14:44:03 +02:00
Erhan Kurubas
5e9000329a feat(riscv_trace): add trace support for ESP32-C6 2026-08-07 14:44:03 +02:00
Erhan Kurubas
91534a8488 fix(soc): correct mem_start_addr typo in H2/H21 trace header 2026-08-07 14:44:03 +02:00
Erhan Kurubas
57ccd12f17 Merge branch 'esp32c5_trace_encoder' into 'master' 
feat(esp_riscv_trace): add ESP32-C5 support

See merge request espressif/esp-idf!51384
 2026-08-07 13:45:10 +02:00
Gao Xu
c7a146ea24 Merge branch 'fix/update_trng_workflow_for_esp32s31' into 'master' 
fix(rng): update TRNG bringup for esp32s31 runtime use

See merge request espressif/esp-idf!48579
 2026-08-07 11:32:46 +08:00
Erhan Kurubas
1a59c3e769 feat(esp_riscv_trace): add ESP32-C5 support 2026-08-06 17:13:04 +02:00