Fix DTM TX buffer leak in the BLE controller that could cause memory exhaustion and Interrupt WDT timeout during or after DTM TX tests.
Closes BLERP-3072 and BLERP-3097
See merge request espressif/esp-idf!52250
The adjtime() wrapper stored the microsecond offset into the 32-bit
`long` timex.offset field without checking for overflow. A large delta
(e.g. 400 days) was computed in 64-bit and silently truncated when
assigned, wrapping into a small value that passed the ~35 minute range
check. adjtime() then returned 0 instead of the expected -1.
Compute the offset in int64_t and reject values that do not fit in the
timex.offset field with EINVAL. Add a regression test for a multi-day delta.
Closes https://github.com/espressif/esp-idf/issues/19051
fix(ppa): fix for SRM operation potential block if do 90/270 degree rotation
Closes IDFGH-18204 and IDFGH-17870
See merge request espressif/esp-idf!49657
The GDMA layer used `max_data_burst_size == 0` as the only way to disable the
data burst. That conflicts with the upstream drivers' convention where a zeroed
config struct means "unset", so users had no way to ask for the driver default
burst size.
GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no
benefit over the non-burst mode. The MSPI alignment constraint under Flash
Encryption / PSRAM ECC still takes precedence and is reported with a warning.
The upstream drivers using GDMA now apply their own default burst size (16
bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver:
- esp_async_crc (AHB / AXI GDMA backend)
- esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend)
Callers that really want no burst can now set `dma_burst_size` to 1.
A peripheral's reset also resets the ones it occupies, so a lock has to cover
both. Gate the ECDSA MPI lock on SOC_ECDSA_USES_MPI rather than the runtime
ecdsa_ll_is_mpi_required() and set that capability on C5, lock the Key Manager
path in esp_key_mgr.c, clean HMAC after its reset, and enable DS before the
primitives its reset covers.
ECDSA enable pulses a reset that also holds SHA in reset, and SHA shares
its DMA with AES. Key Manager enable pulses a reset that also covers the
XTS-AES flash encryption key-usage selector. Neither path was serialized
against those victims, so a hardware ECDSA/HMAC/DS operation could
corrupt a concurrent SHA/AES transfer or an in-flight encrypted flash
read.
- Take the SHA/AES lock inside esp_crypto_ecdsa_lock_acquire(), before
MPI, matching the DS lock order (sha_aes < mpi)
- Add esp_crypto_key_mgr_enable_periph_clk_no_reset() and switch ECDSA,
HMAC and DS to it; they only need the key-usage selector writable
- Hold esp_crypto_key_manager_lock across those clock enable/disable
pairs so selector writes stay serialized without resetting KM
Add a mbedtls_ut case that enters TOP PD light sleep then runs minimal
AES/SHA/MPI/ECC/ECDSA ops, catching crypto modules left unusable after wake.
Co-authored-by: Cursor <cursoragent@cursor.com>
Island
Armando (Dou Yiwen)
Jiang Jiang Jian
Rahul Tank
Guillaume Souchere
morris
Li Shuai
Ashish Sharma
muhaidong
Liu Linyan
Marius Vikhammer
Alexey Gerenkov
Mahavir Jain
wangjialiang
Michael (XIAO Xufeng)
Song Ruo Jing
Konstantin Kondrashov
harshal.patil
radek.tandler
Aditya Patwardhan
C.S.M
Wang Meng Yang
Alexey Lapshin
wuzhenghuiandCursor
Chen Jichang
Martin Vychodil