On Xtensa the PMS violation shares ETS_MEMACCESS_ERR_INUM with the cache error
and arrives as PANIC_RSN_CACHEERR. ESP32-S2 tells the two apart, ESP32-S3 never
did (//MV note in dd938eb95), so PMS faults were reported as "Cache error".
panic_memprot_fill_info() now claims the panic only when
esp_mprot_get_active_intr() reports a pending violation, and the ESP32-S3 cache
error path consults it, falling back to the cache error report as before.
RISC-V has a dedicated interrupt, so its reporting stays unconditional.
ESP32-S2 and ESP32 are untouched.
Move print_memprot_err_details() and its state out of the RISC-V panic_arch.c
into port/panic_memprot.c behind panic_memprot_fill_info(), so the report can
be shared with the Xtensa PMS targets. No functional change.
change(esp_tee): Force non-deterministic ECDSA signing for TEE secure storage keys
Closes IDF-15937 and IDF-15939
See merge request espressif/esp-idf!50355
Objects with atomic members must not be allocated to PSRAM, otherwise
the ordering guarantee of atomic accesses is weakened due to a hardware
behavior on ESP32 chips. Explicitly request MALLOC_CAP_INTERNAL |
MALLOC_CAP_8BIT for:
- i2c master bus object (atomic status/trans_idx)
- i3c master bus object (atomic fsm)
- ISP processor and AE/AF/AWB/HIST controllers (atomic fsm)
- JPEG decoder/encoder dma2d transaction descriptors (atomic started)
- PPA transaction storage embedding dma2d_trans_t
- dma2d m2m test transaction embedding dma2d_trans_t
- Also add RNG LL-APIs for ESP32-C61
- Add SOC_RNG_CLOCK_IS_INDEPENDENT for ESP32-C61: now that
rng_ll_disable() actually clears the RNG clock gate, the application
needs the esp_hw_support startup hook to re-enable the RNG after
bootloader_random_disable()
Extend the test peripheral with receipt timestamps and an auto-recycle
hook so runtime tests can observe handoff latency and sustain arrivals from
dispatch completion.
Add a standalone Unity app covering fixed first-submission deadlines,
callback-entry batch drain, shared ESP timer task fairness, periodic
timestamp light-sleep behavior, synchronous flush, dispatch latency,
deinit races, bounded inflight peaks, and timeout conversion at both
supported tick rates. Verify FIFO delivery and reject delayed-consumer and
extra-marker false positives.
Render BLE_LOG_RT_PERF lines in the performance log parser and
cross-reference the runtime and performance apps from their READMEs.
Replace the dedicated BLE Log FreeRTOS task with a deferred esp_timer
batch dispatch. The first submission anchors a one-shot 1 ms deadline;
the callback drains the queue depth captured at entry and schedules the
next fixed defer only for arrivals left behind. Later submissions cannot
move the current deadline, and no fixed batch-size cap limits throughput.
Protect queue and timer lifetime with runtime references. Drain queued
submissions before ble_log_lbm_flush_all_trans waits for transport
ownership to return, so synchronous flush does not depend on the deferred
alarm firing.
Keep the defer alarm as a light-sleep wake source and select
ESP_TIMER_IN_IRAM. Timestamp synchronization uses the shared ESP timer task
with skipped unhandled events, so it neither wakes light sleep nor replays
missed periods. Retain legacy task and trigger symbols as hidden no-op
sdkconfig compatibility options.
"test alignment for dma" discarded every test_alignment() verdict and
counted a failed allocation as a pass, so it could never fail. Fix that,
use the external line size for PSRAM, and run hw-align in PSRAM configs.
