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3975 Commits

Author SHA1 Message Date
Erhan Kurubas
1c397699b2 feat(system): add OCD stub bin support for more targets 
Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4,
esp32h21 and esp32p4. Update TEE linker scripts with
correct esp_tee_app_config offsets for the 0x3000 stub reservation
 2026-09-03 13:04:45 +02:00
Jiang Jiang Jian
9a70df6d5e Merge branch 'docs/update_coexist_docs_v6.0' into 'release/v6.0' 
docs(coex): enable coexist docs for c61 (v6.0)

See merge request espressif/esp-idf!51379
 2026-09-03 18:00:58 +08:00
Mahavir Jain
78f0f418c8 Merge branch 'fix/disable-key-mgr_v6.0' into 'release/v6.0' 
Disable Key Manager support (v6.0)

See merge request espressif/esp-idf!51391
 2026-09-03 13:42:49 +05:30
Armando (Dou Yiwen)
5af18cd40b fix(mpll): fix mpll calibration fail bug 2026-08-12 13:33:08 +08:00
linruihao
359e211b17 docs(coex): enable coexist docs for c61 2026-08-12 08:55:18 +08:00
harshal.patil
516e849636 change(security): disable Key Manager support on ESP32-C5/P4/S31 
The Key Manager hardware peripheral in its current form needs further
design changes before it can be offered as a production feature.
Until a revised peripheral design is available, withdraw ESP-IDF
support for it on all Key Manager capable targets.
 2026-08-11 09:41:38 +05:30
Alexey Lapshin
8c6ac38275 feat(soc): enable zb* extensions for esp32p4 greater v3 2026-07-15 16:46:44 +07:00
morris
4edbc85a4a Merge branch 'bugfix/uart_sw_flow_ctrl_xoff_char_v6.0' into 'release/v6.0' 
fix(uart): fix uart sw flow ctrl XOFF char write to wrong reg on ESP32C6 (v6.0)

See merge request espressif/esp-idf!50524
 2026-07-15 11:52:07 +08:00
morris
df9d2b7ab8 Merge branch 'refactor/move_regdma_entry_config_to_driver_layer_emac_v6.0' into 'release/v6.0' 
refactor(emac): move sleep retention config into driver layer (v6.0)

See merge request espressif/esp-idf!50620
 2026-07-13 17:15:22 +08:00
morris
44e2e2477f refactor(emac): move sleep retention config into driver layer 
Keep the EMAC regdma retention definitions in esp_eth so the backup
layout stays aligned with driver-owned sleep retention behavior.
 2026-07-10 16:04:09 +08:00
Song Ruo Jing
65f2cb7c05 fix(uart): fix uart sw flow ctrl XOFF char write to wrong reg on ESP32C6 
Add software flow control test case

Introduced in e6ef4d1791

Closes https://github.com/espressif/esp-idf/issues/18779
 2026-07-09 19:24:07 +08:00
Chen Jichang
73075097b1 change(ahb_dma): update c61 eco3 header files 2026-07-09 12:31:21 +08:00
Jiang Jiang Jian
ecb9d864d5 Merge branch 'feat/update_pmu_pau_reg_description_v6.0' into 'release/v6.0' 
feat(soc): update esp32c61 PMU & PAU reg header descriptions (v6.0)

See merge request espressif/esp-idf!50432
 2026-07-08 14:33:53 +08:00
muhaidong
dd8653bbeb fix(coex): remove unsupported external coex soc caps 2026-07-07 14:07:47 +08:00
morris
b3b9ebb516 Merge branch 'bugfix/i2c_set_but_not_used_variable_v6.0' into 'release/v6.0' 
fix(i2c): remove unused but set variables (v6.0)

See merge request espressif/esp-idf!50371
 2026-07-07 13:13:07 +08:00
wuzhenghui
97d115919d feat(soc): update PMU & PAU register description 2026-07-06 21:23:16 +08:00
morris
b312cdf341 fix(i2c): remove unused but set variables 2026-07-06 11:11:39 +08:00
Song Ruo Jing
abe1d3ae48 feat(ppa): add sleep retention support for DMA2D and PPA 2026-07-03 21:57:39 +08:00
Jiang Jiang Jian
af3cf03943 Merge branch 'bugfix/esp_idf_ulp_wakeupcauses_record_v6.0' into 'release/v6.0' 
fix(ulp): record wakeup causes before lp core request sleep v6.0

See merge request espressif/esp-idf!49142
 2026-06-30 16:48:50 +08:00
Mahavir Jain
d5dff24868 Merge branch 'fix/remove_nonexistent_crypto_registers_c61_v6.0' into 'release/v6.0' 
Remove non-existent crypto registers (ESP32-C61) (v6.0)

See merge request espressif/esp-idf!49450
 2026-06-29 19:01:30 +05:30
hebinglin
a764b5f222 fix(ulp): record wakeup causes before lp core request sleep 2026-06-29 16:25:56 +08:00
Jiang Jiang Jian
87d6d58dc8 Merge branch 'fix/move_system_retention_to_esp_hw_support_v6.0' into 'release/v6.0' 
refactor(esp_hw_support): move system_periph_retention from soc to esp_hw_support (v6.0)

See merge request espressif/esp-idf!49750
 2026-06-29 15:41:21 +08:00
Jiang Jiang Jian
e3ef21aa13 Merge branch 'feat/support_usb_wakeup_v6.0' into 'release/v6.0' 
feat: support usb as wakeup source from light sleep (v6.0)

See merge request espressif/esp-idf!49502
 2026-06-29 15:39:20 +08:00
Jiang Jiang Jian
f881254b0f Merge branch 'fix/esp_idf_lp_uart_wakeup_muti_times_v6.0' into 'release/v6.0' 
fix(ulp): fix lp uart keep wakeup triggered v6.0

See merge request espressif/esp-idf!49399
 2026-06-29 15:38:47 +08:00
harshal.patil
a9b74b5219 fix(soc): Remove non-existent crypto registers (ESP32-C61) 2026-06-29 12:27:50 +05:30
morris
3576e8a4d4 Merge branch 'bugfix/gpspi_flash_freq_calc_v6.0' into 'release/v6.0' 
fix(spi_flash): gpspi flash clock could reach higher frequency (v6.0)

See merge request espressif/esp-idf!49441
 2026-06-29 10:18:04 +08:00
wuzhenghui
c669729707 refactor(esp_hw_support): move system_periph_retention from soc to esp_hw_support 2026-06-17 12:18:57 +08:00
JiangGuangMing
e89a04d89e feat(sleep/usb): support usb as wakeup source from light sleep 
Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-06-11 09:13:20 +08:00
Aditya Patwardhan
94be07050f change(secure_boot): mark ECDSA based Secure Boot V2 as insecure on affected SoCs 
ECDSA based Secure Boot V2 is not functional for certain input vectors on
ESP32-C5/C61/H2/P4 and on the preview targets ESP32-H4/H21. RSA based Secure
Boot V2 is the recommended scheme where the SoC supports it. This issue will be
fixed in a future hardware ECO revision; more details will be shared through the
hardware errata document.

A new hidden Kconfig option SECURE_BOOT_V2_ECDSA_INSECURE marks the affected
mass-production SoCs (ESP32-C5/C61/H2/P4). On these SoCs, when hardware Secure
Boot V2 is enabled, the ECDSA (V2) signing scheme is no longer offered by
default; it must be turned on explicitly via SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
under "Allow potentially insecure options" (CONFIG_SECURE_BOOT_INSECURE). App
signing without hardware Secure Boot is not affected. Note that ESP32-C61 has no
RSA based Secure Boot V2, so it has no Secure Boot scheme enabled by default.

The preview targets ESP32-H4 and ESP32-H21 mark ECDSA Secure Boot V2 as not
supported in their SoC capabilities instead of using the option above. As
ESP32-H4 has no other Secure Boot V2 scheme, Secure Boot is disabled entirely on
it; ESP32-H21 retains RSA based Secure Boot V2.

The security documentation keeps the ECDSA Secure Boot V2 content visible and
adds a warning describing the limitation (including that ECDSA Secure Boot V2 on
ESP32-C61 is not recommended for production). CI apps that exercise ECDSA Secure
Boot V2 on the affected SoCs set CONFIG_SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
accordingly.
 2026-06-10 18:06:48 +05:30
Song Ruo Jing
a242565623 fix(spi_flash): gpspi flash clock could reach higher frequency 2026-06-09 21:56:36 +08:00
hebinglin
f088b73ea8 fix(ulp): fix lp uart keep wakeup triggered 2026-06-08 19:49:42 +08:00
Chen Jichang
d1a64bffc0 refactor(clk_tree): use general api to enable the clk 2026-05-15 13:55:37 +08:00
Jiang Jiang Jian
e5191e1612 Merge branch 'bugfix/idf_13957_v6.0' into 'release/v6.0' 
bugfix: fix wifi loss packet and missing interrupt issues when switching root clock source

See merge request espressif/esp-idf!48432
 2026-05-15 12:32:25 +08:00
Mahavir Jain
36f3329a23 Merge branch 'feature/recovery_bootloader_support_v6.0' into 'release/v6.0' 
feat(bootloader): Support recovery bootloader for ESP32P4 (v6.0)

See merge request espressif/esp-idf!48468
 2026-05-15 09:52:49 +05:30
Marius Vikhammer
97c1ba269a Merge branch 'feature/update_efuse_table_esp32h4_v6.0' into 'release/v6.0' 
feat(efuse): Update efuse table for ESP32-H4 (v6.0)

See merge request espressif/esp-idf!48248
 2026-05-15 09:54:28 +08:00
Jiang Jiang Jian
0e34961c91 Merge branch 'feat/soc_usb_fsls_phy_num_backport_v6.0' into 'release/v6.0' 
feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets (backport v6.0)

See merge request espressif/esp-idf!47937
 2026-05-14 15:14:14 +08:00
Konstantin Kondrashov
9e03819d91 feat(efuse): Update efuse table for ESP32-H4 2026-05-14 14:42:49 +08:00
morris
ba0b59f9d4 Merge branch 'backport/h264_regdma_retention_v6.0' into 'release/v6.0' 
feat(esp32p4): add H264 REGDMA link and sleep retention module

See merge request espressif/esp-idf!48375
 2026-05-14 11:57:50 +08:00
Konstantin Kondrashov
a742bd519a feat(bootloader): Support recovery bootloader for ESP32P4/C61 2026-05-13 10:18:15 +03:00
sibeibei
86a9823e5e fix(wifi): fix modem sleep flag clear failed 2026-05-12 19:22:54 +08:00
igor.masar
bcb9d60812 feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets 
Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3, ESP32-P4 and
ESP32-H4 to expose the number of FSLS USB_WRAP PHYs available on each
target. This separates FSLS USB_WRAP support from OTG/UTMI support so
that downstream code can gate FSLS PHY handling independently.
 2026-05-12 18:03:56 +08:00
sibeibei
1d16c0fbad bugfix: fix wifi loss packet and missing interrupt issues when switching root clock source 2026-05-12 15:37:53 +08:00
houhaiyan
6d3b78a8e1 feat(esp32p4): add H264 REGDMA link and sleep retention module 2026-05-11 15:10:35 +08:00
Konstantin Kondrashov
e0a6cc9a23 feat(efuse): Adds efuse calibration field for esp32c5 2026-05-07 15:59:58 +03:00
Konstantin Kondrashov
855da651d3 feat(efuse): Adds efuse for ESP32-H2 revision 1.2 2026-05-01 12:15:33 +03:00
gaoxu
1110a80f31 fix(isp): fix isp clock source error 2026-04-24 10:43:54 +08:00
Mahavir Jain
64c744abb7 docs: update PSRAM and flash encryption docs with per-page and separate key capabilities 2026-04-02 12:20:24 +05:30
Laukik Hase
2f0e634586 fix(soc): Correct the ESP32-C61 ROM stack start address 2026-03-30 18:30:22 +05:30
Jiang Jiang Jian
424a9a8c0d Merge branch 'bugfix/add_pvt_enable_flag_in_pvt_func_v6.0' into 'release/v6.0' 
feat(pvt): add pvt enable flag & change pvt limit & sleep adapt time on release v6.0

See merge request espressif/esp-idf!46808
 2026-03-24 10:30:43 +08:00
Jack
12f56a1333 Revert "disable PVT feature for esp32c5" 
This reverts commit bfb052dbac.
 2026-03-23 20:28:50 +08:00