feat(system): add OCD stub bin support for more targets

Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4, esp32h21 and esp32p4. Update TEE linker scripts with correct esp_tee_app_config offsets for the 0x3000 stub reservation
2026-09-22 13:01:16 +03:00 · 2026-07-27 17:04:28 +03:00
parent 8a1336523a
commit 1c397699b2
14 changed files with 60 additions and 4 deletions
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@@ -406,6 +406,7 @@ menu "ESP System Settings"
        bool "Preload OpenOCD stub binaries to speed up debugging. 12K memory will be reserved"
        default n
        depends on SOC_DEBUG_HAVE_OCD_STUB_BINS
+        depends on !IDF_TARGET_ESP32P4 || ESP32P4_SELECTS_REV_LESS_V3 || CACHE_L2_CACHE_512KB
        help
            OpenOCD uses stub code to access flash during programming or when inserting and removing
            SW flash breakpoints.
@@ -415,6 +416,12 @@ menu "ESP System Settings"
            By enabling this option, 12K of memory in RAM will be preallocated with the stub code,
            eliminating the need to back up and restore the memory region.

+            The stub binaries are prebuilt and linked to run at the start of IRAM (_iram_start).
+            On ESP32-P4 rev >= v3, _iram_start is 0x4FF00000 + L2 cache size, so it only matches the
+            stub's link address (0x4FF80000) when the L2 cache is 512KB. This option is therefore
+            only available on ESP32-P4 rev >= v3 when CACHE_L2_CACHE_512KB is selected. Earlier P4
+            revisions and other targets place _iram_start at a fixed address and are not affected.
+
    config ESP_DEBUG_OCDAWARE
        bool "Make exception and panic handlers JTAG/OCD aware"
        default y
--- a/components/esp_system/openocd_stub_bins/CMakeLists.txt
+++ b/components/esp_system/openocd_stub_bins/CMakeLists.txt
@@ -15,10 +15,14 @@ set(openocd_path $ENV{OPENOCD_SCRIPTS})

 if(openocd_path)
    set(stub_bin_path ${openocd_path}/../espressif/stub_bins)
-    if(IS_DIRECTORY ${stub_bin_path} AND IS_DIRECTORY ${stub_bin_path}/${target})
-        set(code_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_code.inc")
-        set(data_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_data.inc")
-        set(img_header "${stub_bin_path}/${target}/stub_flash_idf_image.h")
+    set(stub_target_dir ${target})
+    if(target STREQUAL "esp32p4" AND CONFIG_ESP32P4_REV_MIN_FULL LESS 300)
+        set(stub_target_dir "esp32p4-rev1")
+    endif()
+    if(IS_DIRECTORY ${stub_bin_path} AND IS_DIRECTORY ${stub_bin_path}/${stub_target_dir})
+        set(code_bin "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_binary_code.inc")
+        set(data_bin "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_binary_data.inc")
+        set(img_header "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_image.h")
        if(EXISTS ${code_bin} AND EXISTS ${data_bin} AND EXISTS ${img_header})
            set(dest_dir "${CMAKE_BINARY_DIR}/openocd_stub_bins")
            set(output_code_bin "${dest_dir}/stub_flash_idf_binary_code.inc")
--- a/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in
+++ b/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in
@@ -32,7 +32,12 @@
 * should be stored via esp_app_tee_config structure
 */

+#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x32b0 );
+#else
 PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2b0 );
+#endif
+
 PROVIDE ( GDMA                      = 0x60080000 );

 /* SPI Flash functions required from the ROM (refer esp32c5.rom.spiflash.ld) */
--- a/components/esp_tee/subproject/main/ld/esp32c61/esp_tee.ld.in
+++ b/components/esp_tee/subproject/main/ld/esp32c61/esp_tee.ld.in
@@ -32,7 +32,12 @@
 * should be stored via esp_app_tee_config structure
 */

+#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x32b0 );
+#else
 PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2b0 );
+#endif
+
 PROVIDE ( GDMA                      = 0x60080000 );

 /* SPI Flash functions required from the ROM (refer esp32c61.rom.spiflash.ld) */
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -1667,6 +1667,10 @@ config SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
    bool
    default y

+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
+
 config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR
    bool
    default y
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -668,6 +668,9 @@
 // #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
 #define SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT (1)

+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*------------------------------------- ULP CAPS -------------------------------------*/
 #define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR         (1) /*!< LP Core interrupts all map to a single entry in vector table */
 #define SOC_LP_CORE_SUPPORT_ETM                     (1) /*!< LP Core supports ETM */
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -1290,3 +1290,7 @@ config SOC_PHY_COMBO_MODULE
 config SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
    bool
    default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -526,5 +526,8 @@
 #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
 #define SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT (1)

+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*------------------------------------- No Reset CAPS -------------------------------------*/
 //  \#define SOC_CAPS_NO_RESET_BY_ANA_BOD           (1)   //TODO: [ESP32C61] IDF-9254
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -962,3 +962,7 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT
 config SOC_RCC_IS_INDEPENDENT
    bool
    default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -532,3 +532,6 @@
 // #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1)    /*!< Support multiple connections optimization */
 // #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED  (1)    /*!< Support For BLE Periodic Adv Enhancements */
 // #define SOC_BLE_CTE_SUPPORTED           (1)    /*!< Support Bluetooth LE Constant Tone Extension (CTE) */
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -1014,3 +1014,7 @@ config SOC_USB_OTG_PERIPH_NUM
 config SOC_USB_FSLS_PHY_NUM
    int
    default 1
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -541,3 +541,6 @@
 /*-------------------------- USB CAPS ----------------------------------------*/
 #define SOC_USB_OTG_PERIPH_NUM          (1U)
 #define SOC_USB_FSLS_PHY_NUM            (1U)
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1998,3 +1998,7 @@ config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
 config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
    bool
    default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -772,3 +772,6 @@
 #define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS   (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
 #define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED   (1) /*!< LP UART wakeup source is kept triggered */
 #define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)