Drivers that allocate from the unencrypted PSRAM carve-out via
MALLOC_CAP_SPIRAM_NO_ENC currently have no way to verify after the fact
which pool a buffer came from. This is particularly relevant for callers
using heap_caps_malloc_prefer(MALLOC_CAP_SPIRAM_NO_ENC, MALLOC_CAP_SPIRAM),
where a silent fallback to encrypted PSRAM would still pass the typical
esp_ptr_external_ram() check.
Expose esp_psram_ptr_is_no_enc() in the public esp_psram.h header. It
performs a range check against the carve-out's virtual-address window and
returns false when PSRAM is not initialized or CONFIG_SPIRAM_ENC_EXEMPT is
disabled, so callers do not need to guard the call site with #if.
Also reference the helper from the External RAM documentation alongside
the heap_caps_malloc(MALLOC_CAP_SPIRAM_NO_ENC) usage example.
If the virtual-address pool is exhausted when reserving the unencrypted
PSRAM carve-out (the warning at L388 may already have fired for the main
mapping), esp_mmu_map_reserve_block_with_caps() returns an error rather
than aborting. Convert the previous assert() into a logged fallback that
disables the carve-out for this boot, mirroring the SPIRAM_ENC_EXEMPT_SIZE
>= psram_available_size path.
Also extend esp_psram_extram_test() to run the standard memory test on
the carve-out region when CONFIG_SPIRAM_ENC_EXEMPT is enabled, so the
unencrypted mapping is exercised on startup like the other PSRAM regions.
Extends the External RAM encryption section to describe
CONFIG_SPIRAM_ENC_EXEMPT and the MALLOC_CAP_SPIRAM_NO_ENC heap
capability, including a security warning and a typical DMA-alignment
use case. Mirrors the change in zh_CN.
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.
PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
Any idf.py invocation could hang indefinitely with no output while
spawning an unbounded chain of "idf.py --version" subprocesses,
eventually exhausting system memory.
During init_cli(), idf.py parses the project's dependencies.lock to
vet trusted component-provided idf_ext.py extensions. If the lock
contains a component whose manifest has an "if: idf_version" clause,
evaluating it calls idf-component-manager's _get_idf_version(). Outside
a CMake build the IDF_VERSION environment variable is not set, so that
function falls back to running "idf.py --version" as a subprocess,
which re-enters init_cli() and recurses without bound.
During a normal CMake build the component manager runs as a subprocess
that already has IDF_VERSION in its environment (see build/config.env),
so the fallback is never reached. The recursion happens only because
idf.py runs component-manager code in-process during its own CLI
startup, outside that context.
Seed IDF_VERSION into os.environ early in init_cli(), before any
dependencies.lock parsing, using the subprocess-free
idf_version_from_cmake() helper. This gives in-process component-manager
code the same IDF_VERSION a CMake build would provide.
Replace the eTaskGetState() polling guard in prvTaskDeleteWithCaps()
with a per-core xTaskGetCurrentTaskHandleForCore() check, so the
predicate matches vTaskDelete()'s immediate-vs-deferred decision. This
closes the taskTASK_SCHEDULED_TO_YIELD race against the IDLE-deferred
TCB cleanup on the SMP preview kernel; behaviour is unchanged on the
default IDF kernel and on single-core targets.
A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.
The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.
This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
This commit started threaded server to serve multiple clients
simultaneously in individual thread, eliminating the single-threaded
server limitation that caused the device's mid-OTA reconnect to time
out while the previous connection was still being torn down.
SSL is now wrapped per-connection inside the handler thread (in
setup()) so the main accept loop never blocks on a TLS handshake.
Closes IDFCI-3505
(cherry picked from commit 7647d54271)
On RISC-V chips with SPIRAM support (esp32c5, esp32c61, esp32h4, esp32p4,
esp32s31), esp_restart_noos() was disabling the cache while the current
stack pointer could still be in external RAM. Any stack access after cache
disable (function call, local variable spill) would then fault with
"Cache disabled but cached memory region accessed".
Xtensa chips (esp32, esp32s2, esp32s3) already had this guard via the
SET_STACK macro. Add the equivalent for RISC-V:
- Add rv_utils_set_sp() to riscv/rv_utils.h (plain "mv sp, %0" with a
memory clobber; no window register management needed on RISC-V)
- In each affected system_internal.c, under
CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM, check whether the current
SP is in PSRAM and if so switch it to the top of internal BSS before
any cache disable or writeback operation
- Fix xTaskCreateStaticPinnedToCore() stack size argument in the
spiram_stack test (was passing bytes instead of word count)
- Mark the null-pointer write in func_do_exception() as volatile to
prevent the compiler from optimizing it away
- Extend the [spiram_stack] tests to RISC-V by sharing fibonacci() and
the task/finish helpers across architectures, guarding only the
Xtensa-specific WINDOWBASE/WINDOWSTART prints
Mahavir Jain
harshal.patil
Jiang Jiang Jian
Zhang Wen Xu
Roland Dobai
Sudeep Mohanty
yinqingzhao
muhaidong
Rahul Tank
Xiao Xufeng
sibeibei
nilesh.kale
Jin Cheng
Sahil Yadav
Guillaume Souchere
Chen Jichang
morris