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Merge branch 'fix/disable_i2c_master_clk_while_hw_hop_processing_v6.0' into 'release/v6.0'

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fix(esp_phy): check hw freq hop done before disabling common clock (v6.0)

See merge request espressif/esp-idf!48558
This commit is contained in:
Zhang Wen Xu
2026-05-15 17:54:02 +00:00
parent 4c36706b41 65d9ecb75c
commit a1ba61203e
6 changed files with 73 additions and 18 deletions
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41
components/esp_phy/Kconfig
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@@ -219,5 +219,46 @@ menu "PHY"
PLL track helps the PHY module adapt to temperature changes, ensuring stable performance.
When pll enabled, the ESP PHY module will periodically track and adjust PLL parameters.
config ESP_PHY_PLL_TRACK_TEMP_DEBUG
bool "PHY temperature tracking debug mode"
depends on ESP_PHY_DEBUG
default n
help
If enabled, allows customization of temperature delta for PHY track pll.
config ESP_PHY_PLL_TRACK_TEMP_DEBUG_FLAG
int "Debug flag for PHY temperature tracking"
depends on ESP_PHY_PLL_TRACK_TEMP_DEBUG
range 1 3
default 1
help
Bitmask debug flag passed to the PHY temperature tracking routine.
Each bit enables a specific tracking mode.
- bit0: PLL tracking
- bit1: Calibration parameter tracking
config ESP_PHY_PLL_TRACK_TEMP_DELTA
int "Temperature delta for PHY track pll"
depends on ESP_PHY_PLL_TRACK_TEMP_DEBUG
range 0 255
default 10
help
Set the temperature delta for PHY track pll.
config ESP_PHY_INIT_IRAM
bool "Place PHY (de)init in IRAM"
depends on SOC_IEEE802154_BLE_ONLY
default n
help
Select this option to place esp_phy and PHY library functions related to phy_init in IRAM.
This config applies to ESP32-H2, ESP32-H21, and ESP32-H4.
config ESP_PHY_ENABLE_VERSION_PRINT
bool "Print PHY version"
default y
help
Select to print PHY version in esp_phy_enable. This config only applies to esp32hxx for now.
endif
endmenu # PHY

18
components/esp_phy/include/esp_private/phy.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -267,6 +267,22 @@ void esp_phy_sleep_data_init(void);
void esp_phy_sleep_data_deinit(void);
#endif
/**
* @brief Wait for frequency hardware hop to complete
*
*/
void phy_wait_freq_hw_hop_done(void);
#if CONFIG_ESP_PHY_PLL_TRACK_TEMP_DEBUG
/**
* @brief Set the temperature delta for PHY track pll
*
* @param debug_flag Debug flag for PHY temperature tracking
* @param track_temp Temperature delta for PHY temperature tracking
*/
void phy_track_temp_debug(uint8_t debug_flag, uint8_t track_temp);
#endif
#ifdef __cplusplus
}
#endif

2
components/esp_phy/lib

Submodule components/esp_phy/lib updated: ac744ff2c5...59c1234e92

6
components/esp_phy/src/phy_common.c
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@@ -377,3 +377,9 @@ void phy_wakeup_from_modem_state_extra_init(void)
}
#endif
#endif
__attribute__((weak)) void phy_wait_freq_hw_hop_done(void)
{
ESP_LOGD(TAG, "phy_wait_freq_hw_hop_done is not implemented");
return;
}

20
components/esp_phy/src/phy_init.c
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@@ -36,12 +36,6 @@
#include "soc/rtc_periph.h"
// TODO: IDF-15338
#if CONFIG_IDF_TARGET_ESP32C5
#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a001c)
#define FECOEX_SET_FREQ_RESTEN (BIT(30))
#endif
#if CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION
#include "esp_partition.h"
#endif
@@ -342,6 +336,9 @@ void esp_phy_enable(esp_phy_modem_t modem)
assert(phy_module_has_clock_bits(PHY_INIT_MODEM_CLOCK_REQUIRED_BITS));
if (s_is_phy_calibrated == false) {
esp_phy_load_cal_and_init();
#if CONFIG_ESP_PHY_PLL_TRACK_TEMP_DEBUG
phy_track_temp_debug(CONFIG_ESP_PHY_PLL_TRACK_TEMP_DEBUG_FLAG, CONFIG_ESP_PHY_PLL_TRACK_TEMP_DELTA);
#endif
s_is_phy_calibrated = true;
} else {
#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
@@ -363,22 +360,12 @@ void esp_phy_enable(esp_phy_modem_t modem)
#endif
sleep_modem_wifi_do_phy_retention(true, wifimac_link_is_sel);
} else {
// TODO: IDF-15338
#if CONFIG_IDF_TARGET_ESP32C5
REG_CLR_BIT(FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_FREQ_RESTEN);
REG_SET_BIT(FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_FREQ_RESTEN);
#endif
phy_wakeup_init();
}
} else {
phy_wakeup_from_modem_state_extra_init();
}
#else
// TODO: IDF-15338
#if CONFIG_IDF_TARGET_ESP32C5
REG_CLR_BIT(FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_FREQ_RESTEN);
REG_SET_BIT(FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_FREQ_RESTEN);
#endif
phy_wakeup_init();
#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP */
@@ -456,6 +443,7 @@ void esp_phy_disable(esp_phy_modem_t modem)
// Update WiFi MAC time before disable WiFi/BT common peripheral clock
phy_update_wifi_mac_time(true, esp_timer_get_time());
#endif
phy_wait_freq_hw_hop_done();
// Disable WiFi/BT common peripheral clock. Do not disable clock for hardware RNG
esp_phy_common_clock_disable();
}

4
components/esp_phy/src/phy_init_esp32hxx.c
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@@ -118,6 +118,9 @@ void esp_phy_enable(esp_phy_modem_t modem)
if (!s_phy_is_enabled) {
register_chipv7_phy(NULL, NULL, PHY_RF_CAL_FULL);
phy_version_print();
#if CONFIG_ESP_PHY_PLL_TRACK_TEMP_DEBUG
phy_track_temp_debug(CONFIG_ESP_PHY_PLL_TRACK_TEMP_DEBUG_FLAG, CONFIG_ESP_PHY_PLL_TRACK_TEMP_DELTA);
#endif
s_phy_is_enabled = true;
} else {
phy_wakeup_init();
@@ -153,6 +156,7 @@ void esp_phy_disable(esp_phy_modem_t modem)
#endif
phy_close_rf();
phy_xpd_tsens();
phy_wait_freq_hw_hop_done();
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_PHY_MODULE);
#endif