Remove ~50 duplicate local definitions of ALIGN_UP/ALIGN_DOWN/ALIGN_UP_BY/
ALIGN_DOWN_BY across the codebase and replace them with canonical
ESP_ALIGN_UP/ESP_ALIGN_DOWN from esp_macros.h.
Use dual-path macros: C keeps fragment-style designated initializers;
C++ uses GNU statement expressions (ESP_LOG_CONFIG_INIT pattern).
Add compile-only C++ regression tests for LP UART/I2C and ULP RISC-V I2C.
Closes https://github.com/espressif/esp-idf/issues/18369
Co-authored-by: Cursor <cursoragent@cursor.com>
Use the target RC_FAST approximation for LP core delay conversion.
This prevents ESP32-S31 from under-delaying when running from RC_FAST.
Co-authored-by: Cursor <cursoragent@cursor.com>
On SOC_LP_GPIO_MATRIX_SUPPORTED targets, use lp_gpio_matrix_input and
lp_gpio_matrix_output instead of lp_gpio_connect_* so matrix outputs use
rtcio_hal_matrix_out (LP GPIO IOMUX applied in HAL).
LP UART remapped pins: drop rtc_gpio_iomux_func_sel(pin, 1); rtc_gpio_init
already selects RTCIO_LL_PIN_FUNC.
Non-matrix LP I2C: select dedicated LP I2C RTC IOMUX via rtc_gpio_iomux_output
(same mux register write as rtc_gpio_iomux_func_sel; matches HAL naming for
peripheral-owned output enable on dedicated mux functions).
This allows rtc_gpio_deinit to always switch the pad back to GPIO,
regardless of lp io clock enabled or not, so that gpio_config can
always switch the IO back to GPIO use after wakeup from deep sleep.
fix(ulp/lp_core): fix LP UART data_bits validation and add full word-length test coverage
Closes PM-715, PM-660, IDFCI-10410, and IDFCI-10464
See merge request espressif/esp-idf!47432
Add LP SPI HAL LL layer for ESP32-S31 and ESP32-P4, enable the
peripheral in soc_caps, and port the HP-side and LP-core-side SPI
drivers to use the new LL abstraction.
lp_core_uart_set_pin() unconditionally configured the RTS and CTS GPIO
pins even when flow control was disabled. Only configure the RTS pin
when UART_HW_FLOWCTRL_RTS is set, and the CTS pin when
UART_HW_FLOWCTRL_CTS is set.
On chips with SOC_LP_GPIO_MATRIX_SUPPORTED (esp32p4, esp32s31), when the
default IOMUX pin is used for LP UART, calling rtc_gpio_iomux_func_sel()
alone only selects the IOMUX function on the pad side but does not set
sig_in_sel=0 on the peripheral side. This leaves the LP UART RX input
still reading from the LP GPIO Matrix (where no signal is connected),
causing RX to receive nothing.
Apply the same fix that was already in the HP UART driver: use
rtc_gpio_iomux_input() / rtc_gpio_iomux_output() which additionally
configure the peripheral to bypass the LP GPIO Matrix for IOMUX pins.
Current implementation of interrupt wait cycle calculation depends on a
delay and local counter method, which is inaccurate in achieving precise
timeouts. This commit updates the implementaion to use CPU cycles
instead, as they are more accurate.
Closes https://github.com/espressif/esp-idf/pull/18208
Fixes for LP ADC to work when used from the LP core
Closes PM-646, IDFCI-5374, IDFCI-5375, IDFCI-5376, and IDFCI-5377
See merge request espressif/esp-idf!45165
- Removed conditional definitions for various RCC_ATOMIC macros across
multiple files, replacing them with a unified PERIPH_RCC_ATOMIC() macro.
- Updated instances where specific RCC_ATOMIC macros were used to ensure
consistent usage of PERIPH_RCC_ATOMIC().
- Deleted unused uart_share_hw_ctrl.h file as its functionality is now
integrated into the new structure.
This commit sets the calibration parameters for a a given LP ADC unit
and channel to improve the raw LP ADC reading when read from the LP
core. The calibration params are set from the HP core.
This commit fixes the following issues with the LP mailbox when LP core
interrupts are enabled -
1. Removed static storage classifier on the interrupt handler to remove
internal linkage and allow the linker to override the weak symbol.
2. Fixed a bug in the interrupt handler where the ACK bit interrupt was
not being cleared correctly.
3. Fixed a bug in the LP core interrupt handler where the message mask
was not being set correctly.
Closes https://github.com/espressif/esp-idf/issues/18095
The existing spinlock mechanism possibly has an overlap of memory
operations during multi core execution, as visible in CI testing. When
running the example inter_cpu_critical_section, shared count increment
stops at 299999 instead of reaching 300000, but this only happens
randomly 1 out of 10 times. It is suspected that a memory operation
happens simultaneously from both core, even though spinlock protection
is in place.
To handle this problem, a memory barrier (fence instruction) is added
at critical places during spinlock acquire and release, to ensure that
all memory operations upto that point are completed and synchronised
before proceeding further.
