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Merge branch 'fix/lp_uart_data_bits' into 'master'

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fix(ulp/lp_core): fix LP UART data_bits validation and add full word-length test coverage

Closes PM-715, PM-660, IDFCI-10410, and IDFCI-10464

See merge request espressif/esp-idf!47432
This commit is contained in:
Sudeep Mohanty
2026-04-28 08:43:03 +02:00
parent c4efd82c25 4155acbdd1
commit cc025fa3d5
10 changed files with 1009 additions and 557 deletions
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50
components/ulp/lp_core/lp_core/lp_core_uart.c
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@@ -180,45 +180,49 @@ int lp_core_uart_read_bytes(uart_port_t lp_uart_num, void *buf, size_t size, int
uint32_t timeout_start = ulp_lp_core_get_cpu_cycles();
while (remaining_bytes > 0) {
/* Read from the Rx FIFO
* We set rx_len to -1 to read all bytes in the Rx FIFO
*/
rx_len = -1;
uart_hal_read_rxfifo(&hal, (uint8_t *)(buf + bytes_rcvd), &rx_len);
/* Drain only as many bytes as fit in the remaining buffer space */
int fifo_len = uart_ll_get_rxfifo_len(hal.dev);
rx_len = (fifo_len < remaining_bytes) ? fifo_len : remaining_bytes;
if (rx_len) {
/* We have some data to read from the Rx FIFO. Check Rx interrupt status */
intr_status = uart_hal_get_intraw_mask(&hal);
if ((intr_status & UART_INTR_RXFIFO_FULL) ||
(intr_status & UART_INTR_RXFIFO_TOUT)) {
/* This is expected. Clear interrupt status and break */
uart_hal_clr_intsts_mask(&hal, intr_mask);
if (rx_len > 0) {
uart_hal_read_rxfifo(&hal, (uint8_t *)(buf + bytes_rcvd), &rx_len);
bytes_rcvd += rx_len;
remaining_bytes -= rx_len;
/* RXFIFO_FULL / RXFIFO_TOUT raw bits are sticky; acknowledge them
* so they do not short-circuit the next iteration. */
uart_hal_clr_intsts_mask(&hal, LP_UART_RX_INT_FLAG);
if (remaining_bytes <= 0) {
break;
} else if ((intr_status & UART_INTR_RXFIFO_OVF)) {
/* We reset the Rx FIFO if it overflows */
}
/* FIFO overflow and parity/framing errors are terminal */
intr_status = uart_hal_get_intraw_mask(&hal);
if (intr_status & UART_INTR_RXFIFO_OVF) {
uart_hal_clr_intsts_mask(&hal, intr_mask);
uart_hal_rxfifo_rst(&hal);
break;
} else if ((intr_status & LP_UART_ERR_INT_FLAG)) {
/* Transaction error. Abort */
} else if (intr_status & LP_UART_ERR_INT_FLAG) {
uart_hal_clr_intsts_mask(&hal, intr_mask);
return -1;
}
/* Update the byte counters */
bytes_rcvd += rx_len;
remaining_bytes -= rx_len;
/* Progress was made; restart the timeout window so callers with
* a finite timeout can tolerate gaps between bursts. */
timeout_start = ulp_lp_core_get_cpu_cycles();
} else {
/* We have no data to read from the Rx FIFO. Check for transaction timeout */
/* FIFO empty. Honour the caller's timeout. */
ret = lp_core_uart_check_timeout(intr_mask, timeout, timeout_start);
if (ret == ESP_ERR_TIMEOUT) {
/* Timeout. Clear interrupt status and break */
uart_hal_clr_intsts_mask(&hal, intr_mask);
break;
}
}
}
/* Return the number of bytes received */
return bytes_rcvd;
if (bytes_rcvd > size) {
bytes_rcvd = size;
}
return (int)bytes_rcvd;
}

46
components/ulp/lp_core/lp_core_uart.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -33,9 +33,9 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
esp_err_t ret = ESP_OK;
/* Argument sanity check */
if ((cfg->uart_proto_cfg.rx_flow_ctrl_thresh > SOC_LP_UART_FIFO_LEN) ||
(cfg->uart_proto_cfg.flow_ctrl > UART_HW_FLOWCTRL_MAX) ||
(cfg->uart_proto_cfg.data_bits > UART_DATA_BITS_MAX)) {
if ((cfg->uart_proto_cfg.rx_flow_ctrl_thresh >= SOC_LP_UART_FIFO_LEN) ||
(cfg->uart_proto_cfg.flow_ctrl >= UART_HW_FLOWCTRL_MAX) ||
(cfg->uart_proto_cfg.data_bits >= UART_DATA_BITS_MAX)) {
// Invalid config
return ESP_ERR_INVALID_ARG;
}
@@ -91,22 +91,31 @@ static esp_err_t lp_uart_config_io(gpio_num_t pin, rtc_gpio_mode_t direction, ui
return ESP_FAIL;
}
/* Set LP_IO direction */
ret = rtc_gpio_set_direction(pin, direction);
if (ret != ESP_OK) {
return ESP_FAIL;
}
/* Connect pins */
const uart_periph_sig_t *upin = &uart_periph_signal[LP_UART_PORT_NUM].pins[idx];
#if !SOC_LP_GPIO_MATRIX_SUPPORTED
/* When LP_IO Matrix is not support, LP_IO Mux must be connected to the pins */
ret = rtc_gpio_iomux_func_sel(pin, upin->iomux_func);
/* On non-matrix chips, LP UART pins are always the default IOMUX pins.
* Use the all-in-one rtc_gpio_iomux APIs which handle func sel and direction. */
if (direction == RTC_GPIO_MODE_OUTPUT_ONLY) {
ret = rtc_gpio_iomux_output(pin, upin->iomux_func);
} else {
ret = rtc_gpio_iomux_input(pin, upin->iomux_func, UART_PERIPH_SIGNAL(LP_UART_PORT_NUM, idx));
}
#else
/* If the configured pin is the default LP_IO Mux pin for LP UART, then set the LP_IO MUX function */
if (upin->default_gpio == pin) {
ret = rtc_gpio_iomux_func_sel(pin, upin->iomux_func);
/* rtc_gpio_iomux_input/output are all-in-one APIs that handle func sel,
* direction, and LP GPIO Matrix bypass in a single call. */
if (direction == RTC_GPIO_MODE_OUTPUT_ONLY) {
ret = rtc_gpio_iomux_output(pin, upin->iomux_func);
} else {
ret = rtc_gpio_iomux_input(pin, upin->iomux_func, UART_PERIPH_SIGNAL(LP_UART_PORT_NUM, idx));
}
} else {
ret = rtc_gpio_set_direction(pin, direction);
if (ret != ESP_OK) {
return ESP_FAIL;
}
/* Select FUNC1 for LP_IO Matrix */
ret = rtc_gpio_iomux_func_sel(pin, 1);
/* Connect the LP_IO to the LP UART peripheral signal */
@@ -145,10 +154,13 @@ static esp_err_t lp_core_uart_set_pin(const lp_core_uart_cfg_t *cfg)
ret = lp_uart_config_io(cfg->uart_pin_cfg.tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_PERIPH_SIGNAL_TX);
/* Configure Rx Pin */
ret = lp_uart_config_io(cfg->uart_pin_cfg.rx_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_PERIPH_SIGNAL_RX);
/* Configure RTS Pin */
ret = lp_uart_config_io(cfg->uart_pin_cfg.rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_PERIPH_SIGNAL_RTS);
/* Configure CTS Pin */
ret = lp_uart_config_io(cfg->uart_pin_cfg.cts_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_PERIPH_SIGNAL_CTS);
/* Configure RTS/CTS only when hardware flow control is enabled */
if (cfg->uart_proto_cfg.flow_ctrl & UART_HW_FLOWCTRL_RTS) {
ret = lp_uart_config_io(cfg->uart_pin_cfg.rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_PERIPH_SIGNAL_RTS);
}
if (cfg->uart_proto_cfg.flow_ctrl & UART_HW_FLOWCTRL_CTS) {
ret = lp_uart_config_io(cfg->uart_pin_cfg.cts_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_PERIPH_SIGNAL_CTS);
}
return ret;
}

43
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_uart.c
View File

@@ -1,11 +1,14 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include "hal/uart_types.h"
#include "hal/uart_ll.h"
#include "test_shared.h"
#include "ulp_lp_core_utils.h"
#include "ulp_lp_core_uart.h"
@@ -28,6 +31,12 @@ uint8_t rx_data[LP_UART_BUFFER_LEN] = {};
volatile uint8_t tx_len = 0;
volatile uint8_t rx_len = 0;
/* Last lp_core_uart_read_bytes return value for LP UART multi-device tests */
volatile int32_t read_return_value = 0;
/* Guarded buffer for read_bytes buffer-bounds test (pre + user + post) */
lp_uart_read_bounds_guard_t read_bounds_guard_region;
/* LP Core print test variables */
volatile char test_string[25];
volatile char test_long_string[200];
@@ -36,6 +45,17 @@ volatile uint32_t test_unsigned_integer;
volatile int test_hex;
volatile char test_character;
/* Wait until the HP peer has filled the LP UART RX FIFO with the full test burst,
* then allow the RX timeout condition to settle. This makes read_bytes behaviour
* deterministic for multi-device tests that depend on a single large FIFO drain. */
static void lp_uart_wait_rx_burst_ready(void)
{
uart_dev_t *dev = (uart_dev_t *)UART_LL_GET_HW(LP_UART_PORT_NUM);
while ((size_t)uart_ll_get_rxfifo_len(dev) < LP_UART_READ_RETURN_VALUE_BURST_LEN) {
}
ulp_lp_core_delay_us(400);
}
int main(void)
{
/* Enable interrupts.
@@ -89,6 +109,27 @@ int main(void)
}
}
if (test_cmd == LP_CORE_LP_UART_READ_BYTES_RETURN_VALUE_TEST) {
/* Read a burst that fits in hardware RX FIFO; HP asserts return value
* equals requested length (see test_lp_uart_read_bytes_return_value). */
lp_uart_wait_rx_burst_ready();
read_return_value = lp_core_uart_read_bytes(LP_UART_PORT_NUM, rx_data,
LP_UART_READ_RETURN_VALUE_BURST_LEN,
LP_UART_TRANS_WAIT_FOREVER);
}
if (test_cmd == LP_CORE_LP_UART_READ_BYTES_BOUNDS_TEST) {
/* Request a small user buffer while the link partner sends a larger burst;
* read_bytes must not corrupt guard regions past user_buf. */
memset(&read_bounds_guard_region, LP_UART_READ_BOUNDS_GUARD_PATTERN,
sizeof(read_bounds_guard_region));
lp_uart_wait_rx_burst_ready();
read_return_value = lp_core_uart_read_bytes(LP_UART_PORT_NUM,
read_bounds_guard_region.user_buf,
LP_UART_READ_BOUNDS_USER_BUF_LEN,
LP_UART_TRANS_WAIT_FOREVER);
}
if (test_cmd == LP_CORE_LP_UART_PRINT_TEST) {
/* Write various cases to test lp_core_printf to test various format specifiers */
lp_core_printf("%s\r\n", test_string);

36
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_shared.h
View File

@@ -5,6 +5,9 @@
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#define XOR_MASK 0xDEADBEEF
/* I2C test params */
@@ -15,6 +18,37 @@
/* LP UART test param */
#define UART_BUF_SIZE 1024
/*
* LP UART read_bytes return-value test (HP + LP):
* The burst must fit in the hardware RX FIFO yet typically exceed the LP UART
* driver's default RX FIFO full threshold (LP_UART_FULL_THRESH_DEFAULT in
* components/ulp/lp_core/lp_core/lp_core_uart.c). If either value changes,
* revisit this guard.
*/
#if (SOC_LP_UART_FIFO_LEN) < 12
#error "SOC_LP_UART_FIFO_LEN too small for LP UART read_bytes return-value test"
#endif
#define LP_UART_READ_RETURN_VALUE_BURST_LEN ((SOC_LP_UART_FIFO_LEN) - 1)
/* Small user buffer for read_bytes buffer-bounds test; HP sends RETURN_VALUE_BURST_LEN. */
#define LP_UART_READ_BOUNDS_USER_BUF_LEN ((SOC_LP_UART_FIFO_LEN) / 4)
/* Guard memory on each side of the user buffer (worst case = full FIFO depth per side). */
#define LP_UART_READ_BOUNDS_GUARD_LEN (2 * (SOC_LP_UART_FIFO_LEN))
#define LP_UART_READ_BOUNDS_GUARD_PATTERN 0xAA
typedef struct __attribute__((packed))
{
uint8_t pre_guard[LP_UART_READ_BOUNDS_GUARD_LEN];
uint8_t user_buf[LP_UART_READ_BOUNDS_USER_BUF_LEN];
uint8_t post_guard[LP_UART_READ_BOUNDS_GUARD_LEN];
} lp_uart_read_bounds_guard_t;
_Static_assert(sizeof(lp_uart_read_bounds_guard_t) ==
(LP_UART_READ_BOUNDS_GUARD_LEN + LP_UART_READ_BOUNDS_USER_BUF_LEN + LP_UART_READ_BOUNDS_GUARD_LEN),
"lp_uart_read_bounds_guard_t layout must match LP/HP shared memory view");
typedef enum {
LP_CORE_READ_WRITE_TEST = 1,
LP_CORE_DELAY_TEST,
@@ -27,6 +61,8 @@ typedef enum {
LP_CORE_LP_UART_READ_TEST,
LP_CORE_LP_UART_MULTI_BYTE_READ_TEST,
LP_CORE_LP_UART_PRINT_TEST,
LP_CORE_LP_UART_READ_BYTES_RETURN_VALUE_TEST,
LP_CORE_LP_UART_READ_BYTES_BOUNDS_TEST,
LP_CORE_LP_SPI_WRITE_READ_TEST,
LP_CORE_NO_COMMAND,
} lp_core_test_commands_t;

1337
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_uart.c
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File diff suppressed because it is too large Load Diff

31
components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py
View File

@@ -1,4 +1,4 @@
# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import pytest
from pytest_embedded import Dut
@@ -50,7 +50,6 @@ def test_lp_vad(dut: Dut) -> None:
dut.run_all_single_board_cases(group='lp_vad')
# TODO: Support LP I2C test for esp32p4 (IDF-9581)
@pytest.mark.generic_multi_device
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='TODO IDF-15572 Enable ULP multi device tests for ESP32-S31')
@pytest.mark.parametrize('count', [2], indirect=True)
@@ -61,16 +60,36 @@ def test_lp_vad(dut: Dut) -> None:
],
indirect=True,
)
@idf_parametrize('target', ['esp32c6'], indirect=['target'])
def test_lp_core_multi_device(case_tester) -> None: # type: ignore
case_tester.run_all_multi_dev_cases(reset=True)
@idf_parametrize('target', soc_filtered_targets('SOC_LP_I2C_SUPPORTED == 1'), indirect=['target'])
def test_lp_core_multi_device(case_tester: CaseTester) -> None:
# Run only non-UART multi-device cases (e.g. LP I2C); LP UART is covered
# by test_lp_uart_multi_device which targets all LP_CORE_SUPPORTED chips.
non_uart_cases = [case for case in case_tester.test_menu if 'uart' not in case.groups]
for case in non_uart_cases:
case_tester.run_multi_dev_case(case=case, reset=True)
@pytest.mark.generic_multi_device
@pytest.mark.parametrize('count', [2], indirect=True)
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
@idf_parametrize('target', soc_filtered_targets('SOC_ULP_LP_UART_SUPPORTED == 1'), indirect=['target'])
def test_lp_uart_multi_device(case_tester: CaseTester) -> None:
uart_cases = [case for case in case_tester.test_menu if 'uart' in case.groups and 'wakeup' not in case.groups]
for case in uart_cases:
case_tester.run_multi_dev_case(case=case, reset=True)
@pytest.mark.generic_multi_device
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='TODO IDF-15572 Enable ULP multi device tests for ESP32-S31')
@pytest.mark.parametrize(
'target',
soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'),
soc_filtered_targets('SOC_ULP_LP_UART_SUPPORTED == 1'),
indirect=True,
)
@pytest.mark.parametrize(

6
examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py
View File

@@ -1,11 +1,13 @@
# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import pytest
from pytest_embedded_idf.dut import IdfDut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
@pytest.mark.generic
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4', 'esp32s31'], indirect=['target'])
@idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target'])
def test_lp_core_build_sys(dut: IdfDut) -> None:
dut.expect('Sum calculated by ULP using external library func: 11')

11
examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py
View File

@@ -1,14 +1,21 @@
# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import logging
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
@pytest.mark.generic
@idf_parametrize('target', ['esp32c6', 'esp32p4', 'esp32c5'], indirect=['target'])
@idf_parametrize(
'target',
soc_filtered_targets(
'SOC_LP_CORE_SUPPORTED == 1 and SOC_ULP_LP_UART_SUPPORTED == 1 and SOC_DEEP_SLEEP_SUPPORTED == 1'
),
indirect=['target'],
)
def test_lp_core_pcnt(dut: Dut) -> None:
res = dut.expect(r'ULP will wake up processor after every (\d+) pulses')
wakeup_limit = res.group(1).decode('utf-8')

3
examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py
View File

@@ -3,9 +3,10 @@
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
@pytest.mark.generic
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4', 'esp32s31'], indirect=['target'])
@idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target'])
def test_lp_core_intr(dut: Dut) -> None:
dut.expect('Triggered 10 interrupts on the LP-Core, LP-Core received 10 interrupts')

3
examples/system/ulp/lp_core/lp_timer_interrupt/pytest_lp_timer_interrupt.py
View File

@@ -5,10 +5,11 @@ import time
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
@pytest.mark.generic
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target'])
@idf_parametrize('target', soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1'), indirect=['target'])
def test_lp_timer_interrupt(dut: Dut) -> None:
# Wait for LP core to be loaded and running
dut.expect_exact('LP core loaded with firmware and running successfully')