fix(ulp/lp_core): fix LP UART data_bits validation and add full word-length test coverage
Closes PM-715, PM-660, IDFCI-10410, and IDFCI-10464
See merge request espressif/esp-idf!47432
Add LP SPI HAL LL layer for ESP32-S31 and ESP32-P4, enable the
peripheral in soc_caps, and port the HP-side and LP-core-side SPI
drivers to use the new LL abstraction.
The multi-device LP UART tests were failing on esp32p4 due to several
issues in the test harness:
- LP ROM boot banner: On chips with LP ROM (esp32p4), the LP core emits
a ROM banner on LP UART during startup, corrupting the first bytes of
test data. Set skip_lp_rom_boot=true in the ULP config for write, read
and mismatch tests to suppress this.
- Stale FIFO data: The HP UART RX FIFO could accumulate garbage during
pin mux setup. Add uart_flush_input() after HP UART driver installation
and before each read phase. Call lp_core_uart_clear_buf() before LP-side
read tests to flush the LP UART RX FIFO as well.
- Missing synchronization: The HP reader could start listening before
the LP transmitter was ready (or vice versa), causing data loss at
higher baud rates. Add signal exchange (unity_send_signal /
unity_wait_for_signal) to coordinate LP-to-HP data transfers.
- Short read timeout: The uart_read_bytes() timeout of 10 ms was too
aggressive for slower baud rates. Increase to 100 ms.
Made-with: Cursor
Several LP core pytest files were either hardcoded to specific chip lists
or using a less-precise SOC capability filter:
- test_lp_core_multi_device: was locked to ['esp32c6'] pending a workaround
for LP I2C on esp32p4; all three active LP core chips now have
SOC_LP_I2C_SUPPORTED=1, so switch to soc_filtered_targets.
- test_lp_uart_wakeup_modes: was using SOC_LP_CORE_SUPPORTED which is
semantically wrong for a UART test; change to SOC_ULP_LP_UART_SUPPORTED.
- LP core example pytests (build_system, interrupt, gpio_intr_pulse_counter,
lp_timer_interrupt): replace hardcoded ['esp32c5', 'esp32c6', 'esp32p4']
with soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1') so that new
chips automatically get coverage when their SOC cap is enabled.
Refactor the LP UART multi-device tests to use a single parameterised
helper pair (test_lp_uart_write_cfg / test_lp_uart_read_cfg) instead of
one-off functions per config, and extend coverage to:
- write and read tests for 5-, 6-, 7-bit and even-parity configurations
- negative tests: word-length mismatch (FRAM_ERR recovery on LP side,
garbled receive on HP side)
- LP GPIO Matrix routing tests (SOC_LP_GPIO_MATRIX_SUPPORTED chips only):
swaps the default TX/RX GPIO numbers so both pins go through the LP GPIO
Matrix, covering the lp_gpio_connect_in/out_signal() branch of
lp_uart_config_io() that was previously untested at the data-transfer
level; the same physical cross-wiring as all other LP UART tests is reused
Add rtc_gpio_deinit() cleanup at the end of single-board LP UART tests
so configured pins are returned to HP/digital mode and do not interfere
with subsequent tests that may reuse the same GPIOs.
lp_core_uart_set_pin() unconditionally configured the RTS and CTS GPIO
pins even when flow control was disabled. Only configure the RTS pin
when UART_HW_FLOWCTRL_RTS is set, and the CTS pin when
UART_HW_FLOWCTRL_CTS is set.
On chips with SOC_LP_GPIO_MATRIX_SUPPORTED (esp32p4, esp32s31), when the
default IOMUX pin is used for LP UART, calling rtc_gpio_iomux_func_sel()
alone only selects the IOMUX function on the pad side but does not set
sig_in_sel=0 on the peripheral side. This leaves the LP UART RX input
still reading from the LP GPIO Matrix (where no signal is connected),
causing RX to receive nothing.
Apply the same fix that was already in the HP UART driver: use
rtc_gpio_iomux_input() / rtc_gpio_iomux_output() which additionally
configure the peripheral to bypass the LP GPIO Matrix for IOMUX pins.
Updated kconfig option type and other supporting changes in build system
to allow enabling both ULP FSM and ULP RISCV simultaneously. Users can
choose at run time which one to initialize and use.
NOTE: Both ULP FSM and ULP RISCV can't be used simultaneously at run
time because they share some common hardware like RTC slow memory space.
Closes https://github.com/espressif/esp-idf/issues/12999
The ULP sources include sdkconfig.h for compile-time configuration
values. The sdkconfig directory was previously available to the ULP
target indirectly through the COMPONENT_INCLUDES variable, which is
populated from the parent component's INTERFACE_INCLUDE_DIRECTORIES.
In cmake v1, idf_component_register() adds the config_dir as PUBLIC
include directory to every component (component.cmake:498), so it
ends up in INTERFACE_INCLUDE_DIRECTORIES and gets passed to the ULP
subproject via COMPONENT_INCLUDES.
In cmakev2, the config_dir is added as a build-level property and
applied to components as PRIVATE (component.cmake:1053), so it no
longer appears in INTERFACE_INCLUDE_DIRECTORIES. As a result, the
sdkconfig directory is missing from the ULP target's include paths.
Add the sdkconfig directory explicitly to the ULP target's include
directories. Note that SDKCONFIG_HEADER is already passed to the ULP
subproject and its directory is already extracted into sdkconfig_dir
for linker script preprocessing (IDFULPProject.cmake:40).
Signed-off-by: Frantisek Hrbata <frantisek.hrbata@espressif.com>
When ulp_lp_core_wakeup_main_processor() is called, it sets the
PMU_SW_INT_RAW bit on the HP side. The normal sleep path clears this
bit before re-entering sleep, but esp_wake_stub_sleep() did not, leaving
the wakeup cause sticky. This caused the PMU to immediately re-trigger a
wakeup as soon as sleep was requested from the wake stub, producing a
rapid re-wakeup loop that eventually triggered LP_WDT_SYS resets.
Add a test case that verifies the wake stub can return to sleep correctly
across multiple LP core wakeup cycles without the re-wakeup bug.
Closing https://github.com/espressif/esp-idf/issues/18308
Made-with: Cursor
Current implementation of interrupt wait cycle calculation depends on a
delay and local counter method, which is inaccurate in achieving precise
timeouts. This commit updates the implementaion to use CPU cycles
instead, as they are more accurate.
Closes https://github.com/espressif/esp-idf/pull/18208
Fixes for LP ADC to work when used from the LP core
Closes PM-646, IDFCI-5374, IDFCI-5375, IDFCI-5376, and IDFCI-5377
See merge request espressif/esp-idf!45165
- Removed conditional definitions for various RCC_ATOMIC macros across
multiple files, replacing them with a unified PERIPH_RCC_ATOMIC() macro.
- Updated instances where specific RCC_ATOMIC macros were used to ensure
consistent usage of PERIPH_RCC_ATOMIC().
- Deleted unused uart_share_hw_ctrl.h file as its functionality is now
integrated into the new structure.
This commit sets the calibration parameters for a a given LP ADC unit
and channel to improve the raw LP ADC reading when read from the LP
core. The calibration params are set from the HP core.
This commit fixes the following issues with the LP mailbox when LP core
interrupts are enabled -
1. Removed static storage classifier on the interrupt handler to remove
internal linkage and allow the linker to override the weak symbol.
2. Fixed a bug in the interrupt handler where the ACK bit interrupt was
not being cleared correctly.
3. Fixed a bug in the LP core interrupt handler where the message mask
was not being set correctly.
Closes https://github.com/espressif/esp-idf/issues/18095
The existing spinlock mechanism possibly has an overlap of memory
operations during multi core execution, as visible in CI testing. When
running the example inter_cpu_critical_section, shared count increment
stops at 299999 instead of reaching 300000, but this only happens
randomly 1 out of 10 times. It is suspected that a memory operation
happens simultaneously from both core, even though spinlock protection
is in place.
To handle this problem, a memory barrier (fence instruction) is added
at critical places during spinlock acquire and release, to ensure that
all memory operations upto that point are completed and synchronised
before proceeding further.
feat(hal): graduate rtc_cntl_timer/lp_timer hal/ll into a new component: esp_hal_rtc_timer and unify naming
Closes IDF-15045
See merge request espressif/esp-idf!44573
This is a follow up commit on top of below commit:
c061c781a3
This commit further increases the ADC_TEST_LOW_VAL threshold from 2165
to 2200, because some tests were found to be failing with ADC reading
values such as 2171, 2172, 2182 etc. Suspecting the ADC callibration or
surrounding temperature to cause such fluctuations which need higher
threshold to avoid test failures.
The low power ADC in ESP32P4 sometimes reads the data value as 2160,
2161 or a bit greater than that when running the CI test case named
esp32p4.defaults.test_lp_core -> LP ADC 1 raw read stress test. However,
the test only passes if value stays below the LOW_VAL threshold of 2160.
Hence, updated the LOW_VAL threshold to 2165 keeping some margin,
because ADC readings may differ slightly from board to board, so this
type of small variations in ADC values are expected.
