He Binglin 4e1b02d90c Merge branch 'change/esp_idf_ulp_add_int_api' into 'master' ...

change(ulp): add lp periph intr enable apis

See merge request espressif/esp-idf!47160

2026-04-14 17:23:22 +08:00

..

cmake

refactor(ulp): Allow both ULP-FSM and ULP-RISCV to enable at build time

2026-03-15 14:01:30 +05:30

ld

fix(lp-core): fixed rtc mem conflict on p4 eco5 between app and ULP

2025-11-20 17:03:23 +08:00

lp_core

Merge branch 'change/esp_idf_ulp_add_int_api' into 'master'

2026-04-14 17:23:22 +08:00

test_apps

Merge branch 'fix/lp_core_wake_stub_pmu_sw_int' into 'master'

2026-03-11 13:35:52 +08:00

ulp_common

feat(ulp): Allow usage oof ADC unit 2 on RISCV co processor

2025-09-22 12:38:37 +02:00

ulp_fsm

fix(hal): fix the issue of dual-core contention for RTC_CNTL regs

2026-02-10 12:08:03 +08:00

ulp_riscv

feat(ulp): Improved ULP delay API accuracy and removed floating point operations

2026-03-05 10:39:34 +02:00

CMakeLists.txt

refactor(ulp): Allow both ULP-FSM and ULP-RISCV to enable at build time

2026-03-15 14:01:30 +05:30

component_ulp_common.cmake

ulp: added basic support for building and running a binary in the lp core

2023-03-09 10:12:23 +08:00

esp32ulp_mapgen.py

feat(esp_libc): make picolibc default libc

2025-12-03 13:31:42 +07:00

Kconfig

refactor(ulp): Allow both ULP-FSM and ULP-RISCV to enable at build time

2026-03-15 14:01:30 +05:30

project_include.cmake

refactor(ulp): Allow both ULP-FSM and ULP-RISCV to enable at build time

2026-03-15 14:01:30 +05:30

sdkconfig.rename.esp32

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00

sdkconfig.rename.esp32s2

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00