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8012 Commits
Author SHA1 Message Date
Jiang Jiang Jian 4ea1cda1ff Merge branch 'feat/add_teardown_for_openthread_case_v6.0' into 'release/v6.0' 
ci: add tear down for openthread ci case (v6.0)

See merge request espressif/esp-idf!48778
 2026-06-29 15:31:26 +08:00
Jiang Jiang Jian fd4f77c8e6 Merge branch 'bugfix/nvs-bootloader-pytest-app-log_v6.0' into 'release/v6.0' 
test(nvs_bootloader): mark nvs bootloader pytest as flaky (v6.0)

See merge request espressif/esp-idf!48697
 2026-06-29 15:31:13 +08:00
Jiang Jiang Jian 8bd0912274 Merge branch 'fix/optimize_the_ot_ci_v6.0' into 'release/v6.0' 
fix(openthread): wait for all onlink GUAs to finish DAD before tests (v6.0)

See merge request espressif/esp-idf!48687
 2026-06-29 15:30:26 +08:00
Jiang Jiang Jian 6a989d0beb Merge branch 'bugfix/perf-benchmark-spiflash-ci-idfci-8082_v6.0' into 'release/v6.0' 
fix(examples): suppress perf_benchmark printf in CI (v6.0)

See merge request espressif/esp-idf!48643
 2026-06-29 15:29:45 +08:00
Mahavir Jain 4163417ff1 Merge branch 'feat/support_rom_psa_mbedtls_v6.0' into 'release/v6.0' 
feat(mbedtls): enable ESP32-C2(Rev2.0) ROM mbedTLS crypto for PSA (v6.0)

See merge request espressif/esp-idf!48843
 2026-06-29 11:22:33 +05:30
Mahavir Jain 732111f75a Merge branch 'feat/esp_tee_backports_v6.0' into 'release/v6.0' 
feat(esp_tee): Feature/fixes backports to `release/v6.0`

See merge request espressif/esp-idf!48486
 2026-06-29 11:21:13 +05:30
Mahavir Jain a4a2a4a5cb Merge branch 'fix_https_request_rom_impl_ci_failure_v6.0' into 'release/v6.0' 
fix(examples): make https_request rom_impl CI test resilient to transient external server failures (backport v6.0)

See merge request espressif/esp-idf!48418
 2026-06-29 11:18:51 +05:30
Mahavir Jain 7292d67dd6 Merge branch 'feat/restful_server_upgrade_vite_version_v6.0' into 'release/v6.0' 
feat(http_server/restful_server): Upgraded Vite version (v6.0)

See merge request espressif/esp-idf!49415
 2026-06-29 11:17:58 +05:30
Mahavir Jain e082ad95da Merge branch 'fix/memory_leak_cross_signed_cert_verify_v6.0' into 'release/v6.0' 
fix(esp_crt_bundle): fixes verification failures with cross signed certificates (v6.0)

See merge request espressif/esp-idf!48624
 2026-06-29 11:17:37 +05:30
Roland Dobai 913be3895f Merge branch 'fix/idfgh-17712-bootloader-extra-components_v6.0' into 'release/v6.0' 
fix(bootloader): discover BOOTLOADER_EXTRA_COMPONENT_DIRS in cmake v1 (v6.0)

See merge request espressif/esp-idf!49720
 2026-06-29 07:40:28 +02:00
morris 32a54c35de Merge branch 'fix/twaifd_assert_fail_v6.0' into 'release/v6.0' 
fix(driver_twai): fix driver assert fail when send frame (v6.0)

See merge request espressif/esp-idf!49941
 2026-06-29 12:35:29 +08:00
morris d91bff2f0f Merge branch 'ci/twai-runner-update-v6.0' into 'release/v6.0' 
ci: twai runner setup v6.0

See merge request espressif/esp-idf!49803
 2026-06-29 10:59:17 +08:00
morris 6c6071aa3c Merge branch 'ci/move_adc_runner_to_generic_v6.0' into 'release/v6.0' 
ci(adc): move all ADC runners to generic (v6.0)

See merge request espressif/esp-idf!49793
 2026-06-29 10:50:11 +08:00
morris b090f3d602 Merge branch 'fix/fix_mipi_lcd_dirty_buffer_v6.0' into 'release/v6.0' 
feat(lcd): support buffer switch interrupt (v6.0)

See merge request espressif/esp-idf!49101
 2026-06-29 10:49:26 +08:00
morris 94fa48c111 Merge branch 'fix/fix_i80_example_high_failure_ratio_v6.0' into 'release/v6.0' 
test(lcd): fix i80 lcd example pytest failure (v6.0)

See merge request espressif/esp-idf!49025
 2026-06-29 10:20:31 +08:00
morris 6dc0cc8de2 Merge branch 'test/uart_dma_ota_fix_v6.0' into 'release/v6.0' 
refactor(uhci): refactor uart_dma_ota example (v6.0)

See merge request espressif/esp-idf!48755
 2026-06-29 10:15:47 +08:00
morris df8b29aafc Merge branch 'doc/i2s_esp32_mclk_restriction_v6.0' into 'release/v6.0' 
docs(i2s): add note for the restriction of MCLK on esp32 (v6.0)

See merge request espressif/esp-idf!48571
 2026-06-29 10:12:10 +08:00
wanckl 14b5df881a feat(driver_twai): add prioritized TX queue support 2026-06-24 14:15:51 +08:00
Wan Lei 9f694876bf fix(driver_twai): enable ci test for h4 2026-06-24 14:15:51 +08:00
wanckl 35fb412e71 fix(ci): twai test close board to fixed ci jobs pullotion 2026-06-23 14:27:46 +08:00
harshal.patil 5ed711bc06 fix(esp_common/esp_fault): make ESP_FAULT_ASSERT survive optimization 
ESP_FAULT_ASSERT(C) was silently deleted by the optimizer when C is a cached
flag/status already proven by a preceding `if (!C) return/goto`: the compiler
folds C to a constant and drops all three checks, removing the fault-injection
protection with no warning.
 2026-06-18 19:41:56 +05:30
igor.udot 44b52749af ci: twai runner setup 2026-06-18 13:26:21 +08:00
gaoxu 84c58612c0 ci(adc): remove ADC runner and move ADC tests to generic 2026-06-18 10:32:44 +08:00
Konstantin Kondrashov 255478ce73 fix(bootloader): handle extra component dirs in v1 subproject 
Closes https://github.com/espressif/esp-idf/issues/18651
 2026-06-16 12:20:48 +03:00
harshal.patil 5f824c8683 fix(secure_boot): range-check ECDSA r,s in bootloader before ROM verify 2026-06-12 17:32:38 +05:30
Laukik Hase 93466c1fd3 feat(esp_tee): Add some required fields in the attestation token 
- Chip ID from the ROM
- Device MAC address from eFuse BLK1
- Device Optional Unique ID from eFuse BLK2
 2026-06-12 10:04:06 +05:30
Laukik Hase 140e1ae1f3 ci(esp_tee): Removed common_components dependency from ESP-TEE test-apps 2026-06-12 10:03:02 +05:30
Aditya Patwardhan 94be07050f change(secure_boot): mark ECDSA based Secure Boot V2 as insecure on affected SoCs 
ECDSA based Secure Boot V2 is not functional for certain input vectors on
ESP32-C5/C61/H2/P4 and on the preview targets ESP32-H4/H21. RSA based Secure
Boot V2 is the recommended scheme where the SoC supports it. This issue will be
fixed in a future hardware ECO revision; more details will be shared through the
hardware errata document.

A new hidden Kconfig option SECURE_BOOT_V2_ECDSA_INSECURE marks the affected
mass-production SoCs (ESP32-C5/C61/H2/P4). On these SoCs, when hardware Secure
Boot V2 is enabled, the ECDSA (V2) signing scheme is no longer offered by
default; it must be turned on explicitly via SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
under "Allow potentially insecure options" (CONFIG_SECURE_BOOT_INSECURE). App
signing without hardware Secure Boot is not affected. Note that ESP32-C61 has no
RSA based Secure Boot V2, so it has no Secure Boot scheme enabled by default.

The preview targets ESP32-H4 and ESP32-H21 mark ECDSA Secure Boot V2 as not
supported in their SoC capabilities instead of using the option above. As
ESP32-H4 has no other Secure Boot V2 scheme, Secure Boot is disabled entirely on
it; ESP32-H21 retains RSA based Secure Boot V2.

The security documentation keeps the ECDSA Secure Boot V2 content visible and
adds a warning describing the limitation (including that ECDSA Secure Boot V2 on
ESP32-C61 is not recommended for production). CI apps that exercise ECDSA Secure
Boot V2 on the affected SoCs set CONFIG_SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
accordingly.
 2026-06-10 18:06:48 +05:30
Hrushikesh Bhosale 542ae64088 feat(http_server/restful_server): Upgraded Vite version 
- Bumped up the Vite version to 7.3.2
 2026-06-09 11:24:40 +05:30
Ashish Sharma 8554f060cc fix(http_request): shifts to HTTP/1.1 in example pytest 2026-06-03 11:31:27 +08:00
Chen Jichang 9274289a62 feat(lcd): support buffer switch interrupt 2026-06-01 18:34:58 +08:00
Chen Jichang a42184d7b7 test(lcd): fix i80 lcd example pytest failure 2026-05-29 10:37:17 +08:00
Hrushikesh Bhosale 579769ad28 fix(examples): make https_request rom_impl test resilient to transient external server errors 
The rom_impl variant of the https_request example test connects to an
external server, which requires a valid system time for TLS certificate
validation. In CI, SNTP time sync can be unreachable, causing transient
failures. Write the host timestamp into the DUT's NVS partition (via the
existing write_time_to_nvs helper) before running the test, so the
firmware can set its clock without depending on external NTP servers.
 2026-05-27 11:56:53 +05:30
Hu Rui 98128e8b56 refactor(uhci): improve uart_dma_ota example & uhci docs 
add const to UHCI rx callback edata->data
 2026-05-25 10:57:16 +08:00
Jiang Guang Ming 6eb7f181a2 feat(mbedtls): enable ROM mbedTLS pytest with esp32c2 rev2.0 2026-05-25 10:07:47 +08:00
yiwenxiu 901c9dc903 ci: add tear down for openthread ci case 2026-05-22 10:41:15 +08:00
sonika.rathi 9dd56badbd test(nvs_bootloader): mark nvs bootloader pytest as flaky 2026-05-19 12:15:20 +02:00
Xu Si Yu 0ec7c487bc fix(openthread): wait for all onlink GUAs to finish DAD before tests 2026-05-19 17:39:41 +08:00
sonika.rathi 80687a7a52 fix(examples): suppress perf_benchmark printf in CI 2026-05-18 11:24:46 +02:00
Ashish Sharma 7f8dc336a6 fix(mbedtls): bring back deprecated config MBEDTLS_ECJPAKE_C 2026-05-18 14:56:18 +08:00
Jiang Jiang Jian 8f3d8b41c3 Merge branch 'feat/support_esp3261_cert_test_example_v6.0' into 'release/v6.0' 
feat(phy): support esp32c61 example cert test and antenna(Backport v6.0)

See merge request espressif/esp-idf!48596
 2026-05-16 10:27:40 +08:00
Jiang Jiang Jian dc9276941e Merge branch 'fix/ota_resumption_ci_failures_v6.0' into 'release/v6.0' 
fix(examples): solve OTA resumption CI failures (backport v6.0)

See merge request espressif/esp-idf!48578
 2026-05-15 20:29:10 +08:00
muhaidong 33bbd87a80 feat(phy): support esp32c61 example cert test and antenna 2026-05-15 19:34:52 +08:00
nilesh.kale 62a67bbcb8 fix(examples): solve OTA resumption CI failures (backport v6.0) 
This commit started threaded server to serve multiple clients
simultaneously in individual thread, eliminating the single-threaded
server limitation that caused the device's mid-OTA reconnect to time
out while the previous connection was still being torn down.

SSL is now wrapped per-connection inside the handler thread (in
setup()) so the main accept loop never blocks on a TLS handshake.

Closes IDFCI-3505

(cherry picked from commit 7647d54271)
 2026-05-15 14:08:39 +05:30
Chen Chen c35eb82724 docs(i2s): add note for the restriction of MCLK on esp32 
Closes https://github.com/espressif/esp-idf/issues/18564
 2026-05-15 16:36:41 +08:00
Jin Cheng ad6f33e9d1 feat(ci): added example tests for HFP using external codec 2026-05-15 16:07:08 +08:00
Jiang Jiang Jian 60b925ffcf Merge branch 'fix/bootloader-hooks-log-v2_v6.0' into 'release/v6.0' 
fix(bootloader_hooks): Fix log_v2 support in bootloader hooks (v6.0)

See merge request espressif/esp-idf!48252
 2026-05-15 15:52:06 +08:00
Jiang Jiang Jian 0f06a3c7e7 Merge branch 'fix_https_request_ci_failure_v6.0' into 'release/v6.0' 
fix(https_request): write host time to NVS to eliminate SNTP dependency in CI (backport v6.0)

See merge request espressif/esp-idf!48415
 2026-05-15 14:11:29 +08:00
Jiang Jiang Jian 91b378565a Merge branch 'feat/test_lp_core_debugging_v6.0' into 'release/v6.0' 
feat(ulp): add pytest for debugging example (v6.0)

See merge request espressif/esp-idf!48255
 2026-05-15 14:08:07 +08:00
Jiang Jiang Jian a7b604fd33 Merge branch 'fix/lp_uart_data_bits_v6.0' into 'release/v6.0' 
fix(ulp/lp_core): fix LP UART data_bits validation and add full word-length test coverage (v6.0)

See merge request espressif/esp-idf!48031
 2026-05-15 14:03:13 +08:00