change: the light-sleep test so an internal-RAM helper task enters light sleep while the PSRAM-stacked Unity task is blocked.Verifies that light sleep succeeds and that the PSRAM-stacked task resumes correctly afterward.Removes the unreliable sleep-callback counter check.
The DRAM and RTC_FAST execute cases race the CPU exception against the PMS or
cache interrupt on ESP32-S3 too, so the panic reason is not deterministic.
change(build): drop BUILD_COMPONENTS support and migrate test_apps to not use it for buildv2
Closes IDF-15859
See merge request espressif/esp-idf!51695
A ULP program is built against ulp_riscv, lp_core or ulp_fsm, each stating its
own sources, dependencies and memory layout. Sources shared with the driver
stay in components/ulp.
sdkconfig.ci.memprot_esp32s3 was built but listed in no CONFIGS_MEMPROT_*, so
the S3 PMS panic path was never exercised.
expect_gme() takes an optional core, for panics with no attributable core.
The BUILD_COMPONENTS build property only exists when building through the
Build system v1 compatibility shim. Query the executable library
interface's linked-components list instead, so the app does not depend on
compatibility-only properties.
The BUILD_COMPONENTS build property only exists when building through the
Build system v1 compatibility shim. Query the executable library
interface's linked-components list instead, so the app does not depend on
compatibility-only properties.
The BUILD_COMPONENTS build property only exists when building through the
Build system v1 compatibility shim. Query the executable library
interface's linked-components list instead, so the app does not depend on
compatibility-only properties.
The bootloader programs only unlocked PMA entries (no PMP), so the layout is
not a bootloader<->application ABI; the application resets all entries, programs
them in ascending order from IRAM, and locks everything. Verified on ESP32-H4 v0.1.
Both PSRAM layouts were mapped as a single RWX window, so everything in external
RAM - the heap included - was executable.
PSRAM used as data only is now RW, and under XIP-from-PSRAM it is split per
section as ESP32-P4 does: .text RX, .rodata read-only, and the MMU-page
alignment gaps and the reclaimed heap RW, so neither is executable.
Both describe the layout that esp_psram_init() produces, and the entries are
locked, so - again as on ESP32-P4 - they are only narrowed when
CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION says that layout applies. Without
it the application owns the region and PSRAM stays RWX.
The per-section entries cost one PMP entry more than the 16 available, so the CPU
subsystem and peripheral windows are chained as TOR entries, taking one entry
instead of three.
soc.h is corrected against the S31 bus address map: the peripheral window base
was 1 MB too low, and the LP peripheral top, derived from a register base plus a
size rather than from the map, was 16 KB short. SOC_NON_CACHEABLE_OFFSET_FLASH
is added.
Trim bootloader size by moving some logs to DEBUG. Allows
compiling bootloader on P4 with CONFIG_ESPTOOLPY_FLASHMODE_QIO
without changing partition table offset
Add test apps for binary size tracking:
- esp_timer size_metrics app with minimal/full sdkconfig variants
- minimal_baseline app to establish the platform binary size floor
