The SoC RC_FAST approximation is a nominal figure that can be off by ~10%
from the clock the LP core actually runs at, which made
ulp_lp_core_delay_us() over-delay by up to 9% and the LP core delay test
flake on ESP32-C5 and ESP32-C6.
Use a measured per-target value instead, and fail the build for targets
that have no measured value so that new chips cannot silently inherit a
wrong one.
Use dual-path macros: C keeps fragment-style designated initializers;
C++ uses GNU statement expressions (ESP_LOG_CONFIG_INIT pattern).
Add compile-only C++ regression tests for LP UART/I2C and ULP RISC-V I2C.
Closes https://github.com/espressif/esp-idf/issues/18369
Co-authored-by: Cursor <cursoragent@cursor.com>
Use the target RC_FAST approximation for LP core delay conversion.
This prevents ESP32-S31 from under-delaying when running from RC_FAST.
Co-authored-by: Cursor <cursoragent@cursor.com>
The test was passing without real I2C communication due to a GPIO
mismatch (slave on GPIO 6/7 vs RTC I2C master on GPIO 2/3), single-byte
zero-coincidence, unchecked ULP return values, and an insufficient
RTC I2C timeout.
Fix slave GPIOs, increase test length, check I2C return values, add
proper assertions, and set an adequate RTC I2C timeout.
Co-authored-by: Cursor <cursoragent@cursor.com>
On SOC_LP_GPIO_MATRIX_SUPPORTED targets, use lp_gpio_matrix_input and
lp_gpio_matrix_output instead of lp_gpio_connect_* so matrix outputs use
rtcio_hal_matrix_out (LP GPIO IOMUX applied in HAL).
LP UART remapped pins: drop rtc_gpio_iomux_func_sel(pin, 1); rtc_gpio_init
already selects RTCIO_LL_PIN_FUNC.
Non-matrix LP I2C: select dedicated LP I2C RTC IOMUX via rtc_gpio_iomux_output
(same mux register write as rtc_gpio_iomux_func_sel; matches HAL naming for
peripheral-owned output enable on dedicated mux functions).
The configured maximum should match each target's fixed LP/RTC
reservations so menuconfig does not advertise values that the linker
cannot support.
Keep the linker failure explicit about CONFIG_ULP_COPROC_RESERVE_MEM
because application RTC sections still share the remaining LP/RTC RAM.
This allows rtc_gpio_deinit to always switch the pad back to GPIO,
regardless of lp io clock enabled or not, so that gpio_config can
always switch the IO back to GPIO use after wakeup from deep sleep.
fix(ulp/lp_core): fix LP UART data_bits validation and add full word-length test coverage
Closes PM-715, PM-660, IDFCI-10410, and IDFCI-10464
See merge request espressif/esp-idf!47432
Add LP SPI HAL LL layer for ESP32-S31 and ESP32-P4, enable the
peripheral in soc_caps, and port the HP-side and LP-core-side SPI
drivers to use the new LL abstraction.
The multi-device LP UART tests were failing on esp32p4 due to several
issues in the test harness:
- LP ROM boot banner: On chips with LP ROM (esp32p4), the LP core emits
a ROM banner on LP UART during startup, corrupting the first bytes of
test data. Set skip_lp_rom_boot=true in the ULP config for write, read
and mismatch tests to suppress this.
- Stale FIFO data: The HP UART RX FIFO could accumulate garbage during
pin mux setup. Add uart_flush_input() after HP UART driver installation
and before each read phase. Call lp_core_uart_clear_buf() before LP-side
read tests to flush the LP UART RX FIFO as well.
- Missing synchronization: The HP reader could start listening before
the LP transmitter was ready (or vice versa), causing data loss at
higher baud rates. Add signal exchange (unity_send_signal /
unity_wait_for_signal) to coordinate LP-to-HP data transfers.
- Short read timeout: The uart_read_bytes() timeout of 10 ms was too
aggressive for slower baud rates. Increase to 100 ms.
Made-with: Cursor
Several LP core pytest files were either hardcoded to specific chip lists
or using a less-precise SOC capability filter:
- test_lp_core_multi_device: was locked to ['esp32c6'] pending a workaround
for LP I2C on esp32p4; all three active LP core chips now have
SOC_LP_I2C_SUPPORTED=1, so switch to soc_filtered_targets.
- test_lp_uart_wakeup_modes: was using SOC_LP_CORE_SUPPORTED which is
semantically wrong for a UART test; change to SOC_ULP_LP_UART_SUPPORTED.
- LP core example pytests (build_system, interrupt, gpio_intr_pulse_counter,
lp_timer_interrupt): replace hardcoded ['esp32c5', 'esp32c6', 'esp32p4']
with soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1') so that new
chips automatically get coverage when their SOC cap is enabled.
Refactor the LP UART multi-device tests to use a single parameterised
helper pair (test_lp_uart_write_cfg / test_lp_uart_read_cfg) instead of
one-off functions per config, and extend coverage to:
- write and read tests for 5-, 6-, 7-bit and even-parity configurations
- negative tests: word-length mismatch (FRAM_ERR recovery on LP side,
garbled receive on HP side)
- LP GPIO Matrix routing tests (SOC_LP_GPIO_MATRIX_SUPPORTED chips only):
swaps the default TX/RX GPIO numbers so both pins go through the LP GPIO
Matrix, covering the lp_gpio_connect_in/out_signal() branch of
lp_uart_config_io() that was previously untested at the data-transfer
level; the same physical cross-wiring as all other LP UART tests is reused
Add rtc_gpio_deinit() cleanup at the end of single-board LP UART tests
so configured pins are returned to HP/digital mode and do not interfere
with subsequent tests that may reuse the same GPIOs.
lp_core_uart_set_pin() unconditionally configured the RTS and CTS GPIO
pins even when flow control was disabled. Only configure the RTS pin
when UART_HW_FLOWCTRL_RTS is set, and the CTS pin when
UART_HW_FLOWCTRL_CTS is set.
On chips with SOC_LP_GPIO_MATRIX_SUPPORTED (esp32p4, esp32s31), when the
default IOMUX pin is used for LP UART, calling rtc_gpio_iomux_func_sel()
alone only selects the IOMUX function on the pad side but does not set
sig_in_sel=0 on the peripheral side. This leaves the LP UART RX input
still reading from the LP GPIO Matrix (where no signal is connected),
causing RX to receive nothing.
Apply the same fix that was already in the HP UART driver: use
rtc_gpio_iomux_input() / rtc_gpio_iomux_output() which additionally
configure the peripheral to bypass the LP GPIO Matrix for IOMUX pins.
