Move the cache profile counter type definitions to hal/cache_types.h so
that
esp_cache_cnt.h can use them without depending on the public soc header
soc/cache_periph.h (which CI rejects as non-public).
The remaining cache_periph.h header and its per-target cache_periph.c
sources
are moved from the soc component into the hal component, with the
sources
organized per target directory as usual for the hal component.
Removes the soc/cache_periph.h dependency from esp_cache_cnt.h and
hal/cache_ll.h by using hal/cache_periph.h instead.
Move the PMU internal voltage calibration related efuse read LL
functions
from efuse_ll.h into pmu_ll.h, renaming them with the pmu_ll prefix.
efuse_ll.h should only contain efuse controller or system-global
functions;
other modules' private efuse bits belong to their own LL layer.
Affected chips: esp32c5, esp32c6, esp32c61, esp32h2, esp32h4, esp32p4.
Moved functions (renamed efuse_ll_get_* -> pmu_ll_get_*):
- get_active_hp_dbias, get_active_lp_dbias
- get_dbias_vol_gap
- get_lslp_dbg, get_dslp_dbg (where present)
- get_lslp_hp_dbias, get_dslp_lp_dbias (where present)
- get_dslp_dbias (esp32h2)
Report whether the SHA peripheral can run the SM3 mode. The LL function
sha_ll_is_sm3_supported() exists on every chip. ESP32-S31 reads the
DIS_SM_CRYPT eFuse, which disables SM2 and SM3 permanently. ESP32-C5 and
ESP32-H4 have SM3 but no such eFuse. All other chips have no SM3.
- Also add RNG LL-APIs for ESP32-C61
- Add SOC_RNG_CLOCK_IS_INDEPENDENT for ESP32-C61: now that
rng_ll_disable() actually clears the RNG clock gate, the application
needs the esp_hw_support startup hook to re-enable the RNG after
bootloader_random_disable()
The PSRAM encryption anti-FI check in mmu_ll_write_entry() pulls in
ESP_FAULT_ASSERT and efuse_hal_chip_revision(), which inflate the
bootloader image size. The check is not meaningful in the bootloader
or in the ESP-TEE build, so guard it out for both.
Applies to esp32c5, esp32c61 and esp32p4.
Rename the internal ULP child-build marker to __ULP_BUILDV2 so component CMake files make the build-system scope explicit.
Document that the marker is currently set only by the IDF_BUILD_V2 ULP child path.
Move the following modules from the hal component into a new dedicated
esp_hal_debug_assist component, following the esp_hal_timg pattern:
- assist_debug (hal + target-specific LL headers)
- debug_probe (types + target-specific LL headers)
- riscv_trace (hal + types + source + target-specific LL headers)
- trace_ll (esp32/esp32s2/esp32s3 target-specific LL headers)
Update the following components to depend on esp_hal_debug_assist:
esp_system, riscv, bootloader_support, esp_hw_support, esp_riscv_trace
Remove riscv_trace_hal.c from the hal component.
Move chip-specific LL headers from the hal component to their respective
component directories:
- lp_spi_ll.h (esp32p4, esp32s31) -> esp_hal_gpspi
- sar_ctrl_ll.h (all chips) -> esp_hal_ana_conv
Move soc_etm_retention_desc_t type definition and soc_etm_retention_info
data from hal component to esp_hw_support component, following the
pattern of other peripheral retention data (e.g. MWDT).
- Create esp_private/etm_retention.h with type and extern declaration
- Create port/<target>/etm_retention.c for each target with retention data
- Remove hal/<target>/etm_periph.c and hal/include/hal/etm_periph.h
- Update esp_etm.c to include the new header
- Update CMakeLists.txt in both components
Move per-target GPSPI regdma retention descriptors out of esp_hal_gpspi
and
into esp_driver_spi so the driver owns its backup scope and restore
sequence.
- add ESP32-S31 debug probe LL, target IDs, capability macros, and GPIO signal mapping
- allow LP probe channels to configure four signal bytes while keeping 16 GPIO outputs
- add HP and LP probe read tests, including LP 32-bit read verification
- keep existing vbat LP probe usage aligned with the new LP channel behavior
