feat(sha): add sha_hal_is_sm3_supported()

Report whether the SHA peripheral can run the SM3 mode. The LL function
sha_ll_is_sm3_supported() exists on every chip. ESP32-S31 reads the
DIS_SM_CRYPT eFuse, which disables SM2 and SM3 permanently. ESP32-C5 and
ESP32-H4 have SM3 but no such eFuse. All other chips have no SM3.

components/esp_hal_security/esp32/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -195,6 +195,18 @@ static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state,
     }
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c2/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -180,6 +180,18 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c3/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -184,6 +184,18 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c5/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -191,6 +191,18 @@ static inline void sha_ll_t_len_set(uint8_t t_len)
     REG_WRITE(SHA_T_LENGTH_REG, t_len);
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no eFuse that disables SM3, so the mode is always available.
+ *
+ * @return true
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return true;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c6/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -170,6 +170,18 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c61/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -169,6 +169,18 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32h2/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -171,6 +171,18 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32h21/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -171,6 +171,18 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32p4/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -206,6 +206,18 @@ static inline void sha_ll_t_len_set(uint8_t t_len)
     REG_WRITE(SHA_T_LENGTH_REG, t_len);
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32s2/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -223,6 +223,18 @@ static inline void sha_ll_t_len_set(uint8_t t_len)
     REG_WRITE(SHA_T_LENGTH_REG, t_len);
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32s3/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -201,6 +201,18 @@ static inline void sha_ll_t_len_set(uint8_t t_len)
     REG_WRITE(SHA_T_LENGTH_REG, t_len);
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no SM3 hardware.
+ *
+ * @return false
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return false;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32s31/include/hal/sha_ll.h

@@ -9,6 +9,7 @@
 #include "hal/sha_types.h"
 #include "soc/hp_sys_clkrst_struct.h"
 #include "soc/hwcrypto_reg.h"
+#include "soc/efuse_struct.h"
 
 /* ESP32-S31 SHA register header uses SHA_2_SM_3_H_MEM/M_MEM naming
  * instead of SHA_H_MEM/M_MEM. Define compatibility macros. */
@@ -211,6 +212,20 @@ static inline void sha_ll_t_len_set(uint8_t t_len)
     REG_WRITE(SHA_T_LENGTH_REG, t_len);
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * The DIS_SM_CRYPT eFuse disables SM2 and SM3 permanently. The function reads
+ * the eFuse shadow register directly, so it reports the real chip state also
+ * when CONFIG_EFUSE_VIRTUAL is enabled.
+ *
+ * @return true if SM3 is available, false if the eFuse disables it
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return !EFUSE.rd_repeat_data1.dis_sm_crypt;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/include/hal/sha_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -73,6 +73,14 @@ void sha_hal_write_digest(esp_sha_type sha_type, void *digest_state);
 void sha_hal_hash_dma(size_t num_blocks, bool first_block);
 #endif
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * @return true if SM3 is available. false if the chip has no SM3 hardware
+ *         or if an eFuse disables it.
+ */
+bool sha_hal_is_sm3_supported(void);
+
 #if SOC_SHA_SUPPORT_SHA512_T
 /**
  * @brief Calculates and sets the initial digiest for SHA512_t

components/esp_hal_security/sha_hal.c

@@ -139,6 +139,11 @@ void sha_hal_write_digest(esp_sha_type sha_type, void *digest_state)
 }
 #endif //SOC_SHA_SUPPORT_RESUME
 
+bool sha_hal_is_sm3_supported(void)
+{
+    return sha_ll_is_sm3_supported();
+}
+
 #if SOC_SHA_SUPPORT_SHA512_T
 
 /* Calculates and sets the initial digiest for SHA512_t */

components/hal/esp32h4/include/hal/sha_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -189,6 +189,18 @@ static inline void sha_ll_t_len_set(uint8_t t_len)
     REG_WRITE(SHA_T_LENGTH_REG, t_len);
 }
 
+/**
+ * @brief Check whether the SHA peripheral can run the SM3 mode.
+ *
+ * This chip has no eFuse that disables SM3, so the mode is always available.
+ *
+ * @return true
+ */
+static inline bool sha_ll_is_sm3_supported(void)
+{
+    return true;
+}
+
 #ifdef __cplusplus
 }
 #endif