Commit Graph

1747 Commits

Author SHA1 Message Date
Erhan Kurubas
b6032a0b1f fix(esp_system): break into the debugger only on the first panic entry 2026-09-05 03:15:58 +08:00
morris
17dabceecf Merge branch 'fix/dualcore_branch_predictor_cache_race_v6.0' into 'release/v6.0'
fix(spi_flash): disable branch prediction on the parked core during flash ops (v6.0)

See merge request espressif/esp-idf!52202
2026-09-04 17:57:09 +08:00
Alexey Gerenkov
2007a7c8db Merge branch 'feature/update-openocd-to-v0.12.0-esp32-20260831_v6.0' into 'release/v6.0'
feat(tools): update openocd version to v0.12.0-esp32-20260831 (v6.0)

See merge request espressif/esp-idf!52392
2026-09-04 17:32:14 +08:00
Fu Hanxi
ddb9fd017c ci: apply idf-ci 1.x 2026-09-03 20:24:50 +02:00
Jiang Jiang Jian
ca6a13e021 Merge branch 'debug/idf-15875-fix_v6.0' into 'release/v6.0'
fix(psram): suspend external cache during CPU freq switch on esp32p4 (v6.0)

See merge request espressif/esp-idf!51685
2026-09-03 19:52:46 +08:00
Erhan Kurubas
1c397699b2 feat(system): add OCD stub bin support for more targets
Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4,
esp32h21 and esp32p4. Update TEE linker scripts with
correct esp_tee_app_config offsets for the 0x3000 stub reservation
2026-09-03 13:04:45 +02:00
Erhan Kurubas
8a1336523a change(system): increase OCD stub memory reservation from 8K to 12K 2026-09-03 13:04:40 +02:00
Roland Dobai
d6ccd2a7df Merge branch 'feature/use_zcmp_by_default_v6.0' into 'release/v6.0'
feat(build): add ZCMP workaround post-build check (v6.0)

See merge request espressif/esp-idf!51326
2026-09-03 09:36:29 +02:00
Ashish Sharma
f91ec54912 fix(spi_flash): disable branch prediction on the parked core during flash ops 2026-08-31 10:42:46 +08:00
Michael.B
7d5f73a0f0 fix(psram): suspend external cache during CPU freq switch on esp32p4
Suspend the external-memory cache around the boot CPU frequency switch so
PSRAM-XIP / write-back cache state cannot be corrupted mid-switch.
2026-08-27 02:21:17 +08:00
harshal.patil
6dd847c8dd refactor(esp_system): deduplicate ROM fast wake RTC digest reservation
The digest length and the condition that reserves it at the end of RTC RAM were
duplicated in seven places. Hold the reservation in a hidden Kconfig value that
is zero when the feature does not apply, so every consumer subtracts it
unconditionally, and derive ESP_SECURE_BOOT_DIGEST_LEN from it.
2026-07-31 10:54:32 +08:00
Alexey Lapshin
fbaf869fb9 feat(build): add RISC-V ZCMP post-link workaround check
Validate linked RISC-V executables when
CONFIG_COMPILER_ENABLE_RISCV_ZCMP is enabled on affected chips.
Disassemble each function and reject mstatus.MIE clears that lack an
earlier mintthresh write of 0xff.

Handle csrrci, csrrw, and register-mask csrrc patterns while ignoring
csrrs. Add build-only coverage for valid and invalid sequences with
CMake v1 and v2.

Stop the hardware stack guard before switching stacks during restart,
and keep ZCMP disabled for TEE test apps that still require the
workaround.
2026-07-30 12:14:54 +07:00
Jiang Jiang Jian
8dec036cdd Merge branch 'feature/adds_ipc_isr_safe_api_v6.0' into 'release/v6.0'
feat(ipc_isr): Adds IPC ISR safe API to stall other CPU (v6.0)

See merge request espressif/esp-idf!50964
2026-07-22 10:44:59 +08:00
Konstantin Kondrashov
6b95e00788 feat(ipc_isr): adds IPC ISR safe API for other CPU stall API 2026-07-20 11:20:23 +03:00
Armando (Dou Yiwen)
19784893df fix: fixed image header segment count check
Signed-off-by: Armando (Dou Yiwen) <douyiwen@espressif.com>
2026-07-20 10:21:49 +08:00
Song Ruo Jing
b5e03248bb fix(stdio): add console input ability when selects ESP_CONSOLE_UART_CUSTOM_NUM_1 2026-07-09 19:24:07 +08:00
morris
1c04de442d Merge branch 'feature/psram_halfsleep_mode_support_v6.0' into 'release/v6.0'
feat(psram): allow PSRAM to enter halfsleep mode during light sleep (v6.0)

See merge request espressif/esp-idf!49759
2026-07-03 11:14:20 +08:00
Mahavir Jain
d5dff24868 Merge branch 'fix/remove_nonexistent_crypto_registers_c61_v6.0' into 'release/v6.0'
Remove non-existent crypto registers (ESP32-C61) (v6.0)

See merge request espressif/esp-idf!49450
2026-06-29 19:01:30 +05:30
Jiang Jiang Jian
08f007f68d Merge branch 'fix-bind_int_wdt_to_cache_livelock_fix_v6.0' into 'release/v6.0'
fix(esp_system): bind int_wdt to cache livelock workaround (v6.0)

See merge request espressif/esp-idf!49169
2026-06-29 15:36:59 +08:00
Jiang Jiang Jian
0855c331d7 Merge branch 'fix/esp32c5_usj_console_stuck_v6.0' into 'release/v6.0'
fix(esp32c5): Do not disable UART0 sclk when USB Serial/JTAG is primary console (v6.0)

See merge request espressif/esp-idf!48874
2026-06-29 15:32:15 +08:00
Marius Vikhammer
3b286227e8 Merge branch 'bugfix/int_wdt_default_psram_v6.0' into 'release/v6.0'
fix(iwdt): increased default timeout if using PSRAM (v6.0)

See merge request espressif/esp-idf!49481
2026-06-29 15:07:05 +08:00
harshal.patil
a9b74b5219 fix(soc): Remove non-existent crypto registers (ESP32-C61) 2026-06-29 12:27:50 +05:30
Marius Vikhammer
08c4e54ec5 fix(iwdt): increased default timeout if using PSRAM
Default timeout for interrupt WDT was increased by default
on ESP32, due to some heap integrity check APIs taking a long
time on large PSRAMs and causing timeouts.

But this adjustment was only done for ESP32, not later chips,
even though they may experience the same issue.

Adjusted to have the same behavior on all chips with PSRAM
enabled, making it consistant with the docs.

Closes https://github.com/espressif/esp-idf/issues/18360
2026-06-29 10:31:38 +08:00
Laukik Hase
00cff977c6 fix(esp_tee): Avoid crypto peripherals reset with esp_restart() from REE
- Reset the crypto peripherals during TEE initialization
2026-06-26 15:07:23 +05:30
harshal.patil
5ed711bc06 fix(esp_common/esp_fault): make ESP_FAULT_ASSERT survive optimization
ESP_FAULT_ASSERT(C) was silently deleted by the optimizer when C is a cached
flag/status already proven by a preceding `if (!C) return/goto`: the compiler
folds C to a constant and drops all three checks, removing the fault-injection
protection with no warning.
2026-06-18 19:41:56 +05:30
wuzhenghui
bc55111320 feat(esp_hw_support): check psram data is not corrupted after lightsleep 2026-06-18 11:50:42 +08:00
harshal.patil
3195c942da fix(mbedtls): validate ECDSA signature range and harden ECC memory power-down 2026-06-09 15:02:59 +05:30
wuzhenghui
df645d9d05 fix(esp_system): update cache livelock workaround bind to interrupt WDT configuration 2026-06-02 17:31:03 +08:00
Peter Dragun
d9e28fe088 fix(esp32c5): Do not disable UART0 sclk when USB Serial/JTAG is primary console
This is a workaround for rom code issue, which can cause the chip to end in infinite loop
when reset is triggered from esptool/idf-monitor. This is only applicable to ESP32-C5 rev <= 1.0.

Closes https://github.com/espressif/esp-idf/issues/18089
2026-05-25 14:48:06 +02:00
wuzhenghui
fcad5f0a1d fix(esp_system): fix build err if int_wdt is not enabled on esp32 2026-05-25 10:35:34 +08:00
wuzhenghui
e99ea90ee8 fix(esp_system): remove intwdt config critical area for chips except esp32 2026-05-25 10:35:30 +08:00
Guillaume Souchere
3e293035e3 fix(esp_system): PSRAM stack crash in esp_restart_noos on RISC-V chips
On RISC-V chips with SPIRAM support (esp32c5, esp32c61, esp32h4, esp32p4,
esp32s31), esp_restart_noos() was disabling the cache while the current
stack pointer could still be in external RAM. Any stack access after cache
disable (function call, local variable spill) would then fault with
"Cache disabled but cached memory region accessed".

Xtensa chips (esp32, esp32s2, esp32s3) already had this guard via the
SET_STACK macro. Add the equivalent for RISC-V:

- Add rv_utils_set_sp() to riscv/rv_utils.h (plain "mv sp, %0" with a
  memory clobber; no window register management needed on RISC-V)
- In each affected system_internal.c, under
  CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM, check whether the current
  SP is in PSRAM and if so switch it to the top of internal BSS before
  any cache disable or writeback operation
- Fix xTaskCreateStaticPinnedToCore() stack size argument in the
  spiram_stack test (was passing bytes instead of word count)
- Mark the null-pointer write in func_do_exception() as volatile to
  prevent the compiler from optimizing it away
- Extend the [spiram_stack] tests to RISC-V by sharing fibonacci() and
  the task/finish helpers across architectures, guarding only the
  Xtensa-specific WINDOWBASE/WINDOWSTART prints
2026-05-15 14:00:36 +08:00
Jiang Jiang Jian
e5191e1612 Merge branch 'bugfix/idf_13957_v6.0' into 'release/v6.0'
bugfix: fix wifi loss packet and missing interrupt issues when switching root clock source

See merge request espressif/esp-idf!48432
2026-05-15 12:32:25 +08:00
sibeibei
51775582e6 bugfix(esp_hw_support):remove ESP32-C5 root clock auto gating bypass in sleep path 2026-05-14 17:16:52 +08:00
Alexey Gerenkov
be24b7c287 fix(build): Fixed constructors placement by Clang for Xtensa
By default Clang puts constructors into '.init_array'.
Close https://github.com/espressif/esp-idf/issues/17990
2026-05-12 17:56:45 +03:00
sibeibei
aa2bd15d46 Revert "fix(esp_hw_support): fix the issue of wifi rx packet loss when switchng soc root clock source"
This reverts commit 45ea08b955.
2026-05-12 15:37:50 +08:00
hebinglin
bce86ecd92 change(esp_system): add iram opt for rtc clk resart cases 2026-05-06 19:29:36 +08:00
Fu Hanxi
ad1d17a794 ci: rename eco tags to revision 2026-04-09 10:43:34 +02:00
Jiang Jiang Jian
9cdd5ebcee Merge branch 'feature/refactor_linker_scripts_v6.0' into 'release/v6.0'
feat(esp_system): refactor linker scripts to reduce duplicated code (v6.0)

See merge request espressif/esp-idf!45728
2026-03-23 14:01:02 +08:00
Jiang Jiang Jian
8c0ab5ce39 Merge branch 'bugfix/esp_task_wdt_v6.0' into 'release/v6.0'
fix(esp_system): Handle failures correctly in esp_task_wdt_reconfigure() (backport v6.0)

See merge request espressif/esp-idf!45897
2026-03-23 11:22:04 +08:00
Alexey Lapshin
8bfe943dbb fix(esp_system): xtensa: refactor linker scripts and reduce binary size for C++ apps 2026-03-23 11:19:22 +08:00
Alexey Lapshin
3a4276afd7 feat(esp_system): riscv: refactor linker scripts to reduce duplicated code 2026-03-23 11:19:22 +08:00
Jiang Jiang Jian
81daeadf9f Merge branch 'esp32h4_debug_asistant_v6.0' into 'release/v6.0'
feat(esp32h4): add assist_debug/bus_monitor support (v6.0)

See merge request espressif/esp-idf!45949
2026-03-23 10:38:51 +08:00
Marius Vikhammer
e741963f13 Merge branch 'ci/common-components-release-v6.0' into 'release/v6.0'
ci: update build-test-rules to use common_components (v6.0)

See merge request espressif/esp-idf!45547
2026-03-23 09:31:28 +08:00
Frantisek Hrbata
fa14a9df47 Merge branch 'feat/cmakev2-backports-v6.0' into 'release/v6.0'
feat(cmakev2): sync pending v6.0 MRs for cmakev2

See merge request espressif/esp-idf!46778
2026-03-21 07:17:43 +01:00
Jiang Jiang Jian
85db04992a Merge branch 'fix/fix_esp32_int_wdt_workaround_break_sleep_process_v6.0' into 'release/v6.0'
fix(esp_system): disable esp32 cache livelock int_wdt workaround in ipc_isr_stall (v6.0)

See merge request espressif/esp-idf!46741
2026-03-21 14:11:21 +08:00
Angus Gratton
2a1481e8e1 fix(esp_system): Allow esp_task_wdt_reconfigure() if timer is stopped
If Task WDT is initialised but not start, the call to esp_timer_stop() in
the reconfigure path returns ESP_ERR_INVALID_STATE and reconfiguring the
Task WDT fails. This isn't the case when the Timer Group is used for Task
WDT.

(This failure cascades into the failure due to disabled interrupts, fixed
in the parent commit.)

Signed-off-by: Angus Gratton <angus@redyak.com.au>
2026-03-20 16:40:24 +08:00
Angus Gratton
5a60192dae fix(esp_system): Handle failures correctly in esp_task_wdt_reconfigure()
- Failures were being masked as function always returned ESP_OK
- In the failure path the spinlock was not unlocked, so interrupts
  became permanently disabled.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
2026-03-20 16:40:24 +08:00
igor.udot
e2a8bbe639 ci: update build-test-rules to use common_components 2026-03-20 15:53:26 +08:00
Marius Vikhammer
ea84e9118d fix(esp_coex): move coex init from esp_system to esp_coex component
CMakev2's DEFERRED mode for idf_component_optional_requires only links
optional components already present in the dependency graph. This caused
esp_coex headers to be unavailable when building minimal examples on
targets with both WiFi and IEEE802154 (e.g. esp32c5, esp32c6).

Moving init_coexist to esp_coex removes the cross-component dependency
and ensures the init function is only compiled when esp_coex itself is
part of the build. A linker hook is added to guarantee the object file
is not silently discarded by the linker.

Made-with: Cursor
2026-03-20 08:16:46 +01:00