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fix(esp32c5): Do not disable UART0 sclk when USB Serial/JTAG is primary console

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This is a workaround for rom code issue, which can cause the chip to end in infinite loop
when reset is triggered from esptool/idf-monitor. This is only applicable to ESP32-C5 rev <= 1.0.

Closes https://github.com/espressif/esp-idf/issues/18089
This commit is contained in:
Peter Dragun
2026-05-25 14:48:06 +02:00
parent 8f3d8b41c3
commit d9e28fe088
1 changed files with 10 additions and 0 deletions
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components/esp_system/port/soc/esp32c5/clk.c
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@@ -251,5 +251,15 @@ __attribute__((weak)) void esp_perip_clk_init(void)
clk_gate_config.disable_pvt_clk = true;
#endif
#if defined(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG) && CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
/* ESP32-C5 rev <= 1.0: Do not disable UART0 sclk when USB Serial/JTAG is primary console.
* Disabling it would cause the chip to end in infinite loop on reset (workaround for rom code issue).
* See: IDFGH-17050
*/
if (efuse_hal_chip_revision() <= 100) {
clk_gate_config.disable_uart0_clk = false;
}
#endif
periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config);
}