HP was asserting a live LP buffer and starting firmware before ADC/GPIO setup.
That produced leftover-high values and print/assert mismatches on pull-down.
Wait 100 ms for analog settle, then wait for completed scans with a wall-clock
timeout (pdMS_TO_TICKS(1) is zero at a 10 ms tick). Copy a local snapshot and
assert it; do not retry until a reading is in range. Deinit on teardown so a
failed raw-read cannot abort the following stress case.
Existing cases used pinned create only as setup for utility queries.
Assert that dynamic and static create keep the task on the requested
core across yields, and that tskNO_AFFINITY stays unpinned.
Tick hook registration lives in esp_system, so its scheduler-suspension
coverage belongs in the esp_system unity test app rather than the
freertos IDF additions suite.
Add KASAN support for detecting heap memory safety bugs (buffer
overflows, underflows, use-after-free) at runtime using compiler
instrumentation and shadow memory. Gated behind
CONFIG_IDF_EXPERIMENTAL_FEATURES, with touch points kept to esp_system
and heap so other components stay untouched.
- Core runtime (esp_system/kasan.c, esp_kasan.h): nibble-based shadow
memory in DRAM, poison/unpoison, per-access validation, and __asan_*
stubs; hot-path stubs in IRAM so they stay valid with the flash cache
off. Shadow init runs before heap bring-up.
- Heap integration (heap/heap_kasan*.c): alloc/free hooks add redzones,
a quarantine FIFO, and shadow updates.
- Panic handling: disable checks once at the panic handler entry so
backtrace and stack dumps can read redzones without nested reports.
- Build system: -fsanitize=kernel-address for app code, with HAL, SoC,
esp_rom, SPI flash, esp_hw_support, bootloader_support, FreeRTOS, and
heap internals excluded from instrumentation.
- Test app (tools/test_apps/system/kasan_test): Unity tests for
overflow, underflow, use-after-free, and all sized __asan_* stubs,
with halt and no-halt configurations.
- Docs: document KASAN in the heap memory debugging guide (EN and CN).
On ESP32-S2/S3 the ULP-RISC-V ADC shares the RTC SAR controller with the
main CPU. ulp_adc_init() sets sar1_en_pad_force = 1 so software selects
the channel, but deep-sleep entry resets it to 0 (ULP/HW control). After
that, the per-read channel selection in ulp_riscv_adc_read_channel() is
ignored and every channel returns the same stale value. Single-channel
worked only because the channel never changed.
Re-assert RTC controller (sar1_en_pad_force = 1) before selecting the
channel on each read so multi-channel sampling works after deep sleep.
ulp_adc_init() could only configure a single ADC channel, so monitoring
several channels from the ULP on one ADC unit was not possible. Add
ulp_adc_multi_channel_init() to configure multiple channels with
per-channel attenuation while keeping the existing single-channel API
unchanged.
Closes https://github.com/espressif/esp-idf/issues/11160
Extends esp_backtrace_print_all_tasks() to RISC-V targets. For running
tasks, registers are captured using UNW_GET_CONTEXT(); for suspended
tasks, the saved RvExcFrame on the task stack is used. Dual-core support
follows the same IPC pattern as the Xtensa implementation.
Backtrace output adapts to the configured backtrace method:
EH-frame, frame-pointer, or register dump (with a hint to enable
frame-pointer mode).
Wrap MWDT-related code under SOC_WDT_SUPPORTED so targets without a main
watchdog can compile.
Add SOC_RTC_WDT_SUPPORTED for RTC watchdog usage (bootloader, slow-clock
paths) and regenerate Kconfig.soc_caps.in. Bootloader RWDT setup stays
under SOC_RTC_WDT_SUPPORTED; MWDT flashboot teardown stays under
SOC_WDT_SUPPORTED.
ESP_INT_WDT, ESP_TASK_WDT_EN, and BOOTLOADER_WDT_ENABLE depend on
SOC_WDT_SUPPORTED where applicable. Build xt_wdt.c only when
SOC_XT_WDT_SUPPORTED. Provide no-op panic WDT helpers when
SOC_WDT_SUPPORTED is disabled.
Updated the documentation of ULP, as we have updated kconfig options
and build files to allow selecting both ULP FSM and ULP RISCV
simultaneously at compile time.
This example shows how to have both ULP FSM and RISCV enabled in kconfig
simultaneously, and use them one after another at run time. A new
parameter TYPE is passed to ulp_embed_binary() function to specify fsm
or riscv in CMakeLists.txt. This way, both ulp_fsm and ulp_riscv source
files can be compiled by their respective toolchains under the same
project.
The example shows ULP FSM incrementing a counter from 0 to 100, ULP
RISC-V incrementing from 100 to 500 and main CPU incrementing from 500
to 1500.
Updated kconfig option type and other supporting changes in build system
to allow enabling both ULP FSM and ULP RISCV simultaneously. Users can
choose at run time which one to initialize and use.
NOTE: Both ULP FSM and ULP RISCV can't be used simultaneously at run
time because they share some common hardware like RTC slow memory space.
Closes https://github.com/espressif/esp-idf/issues/12999
Current implementation of interrupt wait cycle calculation depends on a
delay and local counter method, which is inaccurate in achieving precise
timeouts. This commit updates the implementaion to use CPU cycles
instead, as they are more accurate.
Closes https://github.com/espressif/esp-idf/pull/18208
The existing spinlock mechanism possibly has an overlap of memory
operations during multi core execution, as visible in CI testing. When
running the example inter_cpu_critical_section, shared count increment
stops at 299999 instead of reaching 300000, but this only happens
randomly 1 out of 10 times. It is suspected that a memory operation
happens simultaneously from both core, even though spinlock protection
is in place.
To handle this problem, a memory barrier (fence instruction) is added
at critical places during spinlock acquire and release, to ensure that
all memory operations upto that point are completed and synchronised
before proceeding further.
No further actions for this JIRA ticket are pending. The neccessary test
cases have already been added to verify some additional functionalities.
Hence, removing the TODO reference from code for internal JIRA ticket.
This is a follow up commit on top of below commit:
c061c781a3
This commit further increases the ADC_TEST_LOW_VAL threshold from 2165
to 2200, because some tests were found to be failing with ADC reading
values such as 2171, 2172, 2182 etc. Suspecting the ADC callibration or
surrounding temperature to cause such fluctuations which need higher
threshold to avoid test failures.
Updated the watchdog timer API reference guide to improve explanation
of some existing points.
Also added two new sections in the document:
1. Timeout Stages
2. Common error logs when WDT triggers and possible resolutions
The low power ADC in ESP32P4 sometimes reads the data value as 2160,
2161 or a bit greater than that when running the CI test case named
esp32p4.defaults.test_lp_core -> LP ADC 1 raw read stress test. However,
the test only passes if value stays below the LOW_VAL threshold of 2160.
Hence, updated the LOW_VAL threshold to 2165 keeping some margin,
because ADC readings may differ slightly from board to board, so this
type of small variations in ADC values are expected.
fix(test_rtc_wdt): Fixed CI test failures for RTC WDT by increasing margin
Closes IDFCI-4816, IDFCI-4835, IDFCI-5863, IDFCI-4799, and IDFCI-4817
See merge request espressif/esp-idf!42959
The CI tests for RTC WDT test app were failing because we allowed only
20% margin between configured vs actual timeout of wdt. However, the
RC oscillator accuracy on some boards is very poor and it results in
almost 25% difference between configured and actual timeout. Hence,
increased the failure margin from 20% to 30%. Also some boards like
ESP32P4 have known problem and gives timeout after twice the configured
time. Hence, increased the wdt interrupt wait time to three times the
configured value, so we don't miss the interrupts for such boards.
For the dual core chips like ESP32H4 that are running on slow CPU
clock frequency (96MHz), the number of events getting dispatched in
the test case called "performance test - no dedicated task" were
falling short of expectation because of extra overhead with locks
etc when runing with a non dedicated task. Even for other chips like
ESP32S3, if the main CPU core is running at 80MHz, the result is same.
Hence, added a consideration for CPU clock frequency when deciding
pass criteria for this test case.
Unity based test app configures RTC WDT to verify following features:
1. Verify all 4 stages of RTC WDT are able to trigger timeout and
invoke the pre-configured interrupt service routine
2. Verify RTC WDT can reset the main SYSTEM or main SYSTEM + RTC
Added a pulse counter example code for ulp riscv chips. The example
works by HP core generating high frequency pulses on a GPIO, which
are counted by ULP core to find out the highest possible frequency
of pulses that can be achieved without missing any edges.
lp_core_i2c.h header file has sda and scl pins hardcoded to GPIO6 and
GPIO7 which works only for ESP32C6. ESP32C5 uses GPIO2 and GPIO3 for
I2C SDA and SCL. Hence, added LP_I2C_SCL_IO and LP_I2C_SDA_IO macros
under conditional compilation in library header file, so there is no
need to hardcode I2C GPIO pins and any other test apps or examples
that are including the LP I2C header file can also use Macro directly.
refactor(ulp_riscv): Modify i2c read/write API for better logging and return error code
Closes IDFGH-16269 and IDFGH-15237
See merge request espressif/esp-idf!41342
Updated the i2c read/write APIs ulp_riscv_i2c_master_read_from_device
and ulp_riscv_i2c_master_write_to_device in ulp_riscv component to
return error codes back to the application
Closes https://github.com/espressif/esp-idf/issues/15904
Moved the error logs outside critical section for i2c communication errors
like READ fail, WRITE fail etc. in the ulp_riscv_i2c component
Also changed the error log API from ESP_EARLY_LOG to ESP_LOG, so we can support
tag based filtering and enabling/disabling of logs
Closes https://github.com/espressif/esp-idf/issues/17425
Meet Patel