Commit Graph
222 Commits
Author SHA1 Message Date
Laukik Hase 11fe9fdad6 feat(hal): Add support for flash/PSRAM protection through MSPI PMS 2026-07-10 13:13:09 +05:30
Wu Zheng Hui d26f5682cf Merge branch 'change/change_regdma_malloc_caps' into 'master'
change(heap): reserve DMA pool with low priority MALLOC_CAP_DEFAULT cap

See merge request espressif/esp-idf!50255
2026-07-09 19:32:56 +08:00
C.S.M 048b4dde0c feat(psram): Add unencrypted region for psram for esp32s31 2026-07-07 10:42:45 +08:00
morris 651d6a283f refactor(esp_common): centralize ALIGN_UP/ALIGN_DOWN into esp_macros.h
Remove ~50 duplicate local definitions of ALIGN_UP/ALIGN_DOWN/ALIGN_UP_BY/
ALIGN_DOWN_BY across the codebase and replace them with canonical
ESP_ALIGN_UP/ESP_ALIGN_DOWN from esp_macros.h.
2026-07-06 13:36:06 +08:00
wuzhenghui a3fc0c4b58 change(heap): reserve DMA pool with low priority MALLOC_CAP_DEFAULT caps 2026-07-03 20:54:30 +08:00
Mahavir Jain e16593ebc0 fix(esp_psram): fix unused-but-set-variable warning with GCC 16
GCC 16 flags the volatile accumulator in the cache writeback loops even
though it is volatile, as it is only used to update itself. Drop the
accumulator and rely on the volatile-qualified psram pointer to keep
the cache-line reads from being optimized out.
2026-07-02 07:55:14 +05:30
wuzhenghui ba1df35672 fix(esp_hw_support): fix esp32s31 mpll initialization 2026-06-25 12:20:57 +08:00
Renz Bagaporo ccce50a254 fix(esp_psram): repeated call to init should return invalid state error
Closes https://github.com/espressif/esp-idf/issues/18722
2026-06-18 12:42:38 +09:00
Angus Gratton 443f1bb791 esp_psram: Downgrade "not found" to a warning if "ignore not found" set.
This avoids ~5 errors being logged during boot if the board
has no PSRAM but is configured to boot anyway.

Closes https://github.com/espressif/esp-idf/pull/18705

Signed-off-by: Angus Gratton <angus@redyak.com.au>
2026-06-10 15:15:47 +08:00
morris 87b93ee9ab refactor(flash): move flash error code to the driver layer 2026-06-02 10:38:33 +08:00
Armando (Dou Yiwen) 3905bcecd3 change(psram): changed cs io log to debug level
Signed-off-by: Armando (Dou Yiwen) <douyiwen@espressif.com>
2026-05-27 01:18:58 +00:00
Wu Zheng Hui 2fcaddb700 Merge branch 'fix/fix_psram_data_corrupt_after_lightsleep' into 'master'
fix(esp_hw_support):fix psram data corrupt after lightsleep

Closes PM-941

See merge request espressif/esp-idf!48322
2026-05-22 15:11:41 +08:00
wuzhenghui ecfdeef9d7 feat(esp_psram): wakeup PSRAM by CE# force control instead of dummy write 2026-05-22 14:30:46 +08:00
Mahavir Jain 4811388910 Merge branch 'feat/spiram_enc_exempt' into 'master'
feat(esp_psram): add option to carve unencrypted PSRAM region

Closes IDF-15032

See merge request espressif/esp-idf!48214
2026-05-21 11:36:58 +05:30
armando 6d12e30433 feat(ldo): support s31 psram sdmmc power domain
Move S31 PSRAM/SDMMC power setup onto the common LDO path so shared users can control the domain consistently.
2026-05-21 09:09:14 +08:00
Mahavir Jain 9dff0c23b7 docs(esp_psram): clarify carve-out location is at upper end of PSRAM
The previous wording "top of PSRAM" was ambiguous: the carve-out is
actually mapped at the highest physical addresses of PSRAM (after the
rodata, text, and main heap mappings). Update the Kconfig help text for
SPIRAM_ENC_EXEMPT and SPIRAM_ENC_EXEMPT_SIZE, the External RAM
documentation, and the internal layout comment to say "upper end of PSRAM
(highest physical addresses)" instead.
2026-05-20 10:28:17 +05:30
Mahavir Jain 231dc0e884 feat(esp_psram): add esp_psram_ptr_is_no_enc() helper
Drivers that allocate from the unencrypted PSRAM carve-out via
MALLOC_CAP_SPIRAM_NO_ENC currently have no way to verify after the fact
which pool a buffer came from. This is particularly relevant for callers
using heap_caps_malloc_prefer(MALLOC_CAP_SPIRAM_NO_ENC, MALLOC_CAP_SPIRAM),
where a silent fallback to encrypted PSRAM would still pass the typical
esp_ptr_external_ram() check.

Expose esp_psram_ptr_is_no_enc() in the public esp_psram.h header. It
performs a range check against the carve-out's virtual-address window and
returns false when PSRAM is not initialized or CONFIG_SPIRAM_ENC_EXEMPT is
disabled, so callers do not need to guard the call site with #if.

Also reference the helper from the External RAM documentation alongside
the heap_caps_malloc(MALLOC_CAP_SPIRAM_NO_ENC) usage example.
2026-05-20 10:28:06 +05:30
Mahavir Jain 99fe60f404 fix(esp_psram): handle carve-out vaddr exhaustion and add region to self-test
If the virtual-address pool is exhausted when reserving the unencrypted
PSRAM carve-out (the warning at L388 may already have fired for the main
mapping), esp_mmu_map_reserve_block_with_caps() returns an error rather
than aborting. Convert the previous assert() into a logged fallback that
disables the carve-out for this boot, mirroring the SPIRAM_ENC_EXEMPT_SIZE
>= psram_available_size path.

Also extend esp_psram_extram_test() to run the standard memory test on
the carve-out region when CONFIG_SPIRAM_ENC_EXEMPT is enabled, so the
unencrypted mapping is exercised on startup like the other PSRAM regions.
2026-05-20 10:24:28 +05:30
harshal.patil b4517542ae change(esp_psram): Consider all PSRAM regions in PMP protection 2026-05-19 21:32:29 +05:30
wuzhenghui 858ecf6f70 feat(esp_hw_support): check psram data is not corrupted after lightsleep 2026-05-19 21:01:21 +08:00
Mahavir Jain ac3de1ded7 docs(esp_psram): document MALLOC_CAP_SPIRAM_NO_ENC carve-out
Extends the External RAM encryption section to describe
CONFIG_SPIRAM_ENC_EXEMPT and the MALLOC_CAP_SPIRAM_NO_ENC heap
capability, including a security warning and a typical DMA-alignment
use case. Mirrors the change in zh_CN.
2026-05-14 19:22:29 +05:30
Mahavir Jain 23aba459f5 feat(esp_psram): add option to carve unencrypted PSRAM region
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.

PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
2026-05-14 19:21:18 +05:30
armando 669be4a664 fix(psram): enable psram power xpd 2026-05-14 08:59:54 +00:00
Xiao Xufeng a671c83b0b fix(mspi): fixed possible boot failure in some builds when psram is enabled
A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.

The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.

This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
2026-05-13 16:46:20 +08:00
armando 80db6f440c ci(psram): enable xip psram test on h4 2026-04-28 09:37:03 +08:00
Armando (Dou Yiwen) 9501efde96 Merge branch 'feat/mmu_configurable_page_size_s31' into 'master'
mmu: supported configurable page size on s31

See merge request espressif/esp-idf!47193
2026-04-21 03:31:16 +00:00
armando ab026ecc01 feat(mmu): configurable page size s31 support 2026-04-20 16:58:29 +08:00
Chen Jichang 6e206dd173 refactor(clk_tree): use general api to enable the clk 2026-04-16 20:03:06 +08:00
armando 37e7808223 feat(psram): support psram 100mhz 2026-04-03 10:01:31 +08:00
C.S.M 62d5f34b53 feat(ldo): Add ldo support for psram on esp32s31 2026-04-01 16:31:35 +08:00
armando ebbd9cdb59 feat(psram): support psram device driver 2026-03-31 13:56:43 +08:00
Marius Vikhammer c1256efd67 docs: clarify PSRAM default allocation behavior
Clarify that MALLOC_CAP_DEFAULT describes a memory capability
rather than the malloc() placement policy, so PSRAM-backed
capability allocations are documented correctly when malloc()
remains internal-only by default.

Closes https://github.com/espressif/esp-idf/issues/18391

Made-with: Cursor
2026-03-25 15:35:21 +08:00
armando c96f69faef change(mem): deprecated tcm and added scp memory utils 2026-03-11 11:18:15 +08:00
Song Ruo Jing 69def0c3ea feat(psram): allow PSRAM to enter halfsleep mode during light sleep 2026-02-28 22:33:34 +08:00
Song Ruo Jing 29d62fa6ae feat(mspi): add clear log in psram mspi intr isr for addr misaligned error 2026-02-26 16:38:06 +08:00
armando 9ca37ed6db test(mspi): add flash api run on psram stack test for xip_psram case 2026-01-28 01:27:37 +00:00
Igor Udot f4cb052666 Merge branch 'ci/base_components' into 'master'
ci: use common_components in depends_components

See merge request espressif/esp-idf!45070
2026-01-26 09:08:11 +08:00
morris 0469db2f83 refactor(rcc): unify the usage of clock control macros for peripherals
- Removed conditional definitions for various RCC_ATOMIC macros across
multiple files, replacing them with a unified PERIPH_RCC_ATOMIC() macro.
- Updated instances where specific RCC_ATOMIC macros were used to ensure
consistent usage of PERIPH_RCC_ATOMIC().
- Deleted unused uart_share_hw_ctrl.h file as its functionality is now
integrated into the new structure.
2026-01-23 18:28:13 +08:00
igor.udot 4c26ab876b ci: update build-test-rules to use common_components 2026-01-23 10:14:09 +08:00
Michael (XIAO Xufeng) b61f940191 Merge branch 'fix/min_rev_usage' into 'master'
fix: fix wrong REV_MIN usage for security, bt, efuse

See merge request espressif/esp-idf!45219
2026-01-22 21:25:57 +08:00
Song Ruo Jing 526bf6176e Merge branch 'feature/esp32c61_flash_psram_timing_tuning' into 'master'
feat(mspi): support 120MHz flash and psram for esp32c61

Closes IDF-9256, IDF-14918, and IDFCI-3240

See merge request espressif/esp-idf!45012
2026-01-22 16:36:25 +08:00
Xiao Xufeng 3cf69d2889 fix(psram): cleanup PSRAM_MSPI_MB_WORKAROUND to avoid future issue 2026-01-22 02:55:12 +08:00
Michael (XIAO Xufeng) 7b3042ebf1 Merge branch 'fix/p4_min_rev_usage' into 'master'
P4: fix wrong rev_min usage in rom and other places

See merge request espressif/esp-idf!45222
2026-01-21 15:28:56 +08:00
Song Ruo Jing fc4f07abd6 feat(mspi): support 120MHz flash and psram for esp32c61 2026-01-21 14:38:04 +08:00
Xiao Xufeng 59313eb01f fix: fix psram, rtc_clk on P4 v3.1 2026-01-19 22:32:20 +08:00
Xiao Xufeng e644aed729 fix(esp32p4): fix efuse, encryption and other rev_min usage 2026-01-19 16:58:16 +08:00
armando ee3faa1654 fix(psram): fixed requirement on esp_driver_gpspi on esp32 2026-01-19 01:23:14 +00:00
morris cf33484844 fix(dma): add PSRAM memory barrier for external RAM buffers 2026-01-15 10:11:25 +08:00
armando 41e854d7df fix(mspi): fixed mspi dma burst timing issue 2026-01-09 10:37:49 +08:00
Song Ruo Jing 215c9993bf fix(clk): update H4 to use 64MHz clock for mspi
And add pll clock ref count
2026-01-04 14:07:01 +08:00