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feat(mspi): add clear log in psram mspi intr isr for addr misaligned error

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This commit is contained in:
Song Ruo Jing
2026-02-11 15:37:12 +08:00
parent 67290da88f
commit 29d62fa6ae
6 changed files with 12 additions and 2 deletions
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1
components/esp_hal_mspi/esp32c5/include/hal/psram_ctrlr_ll.h
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@@ -38,6 +38,7 @@ extern "C" {
#define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1)
#define PSRAM_CTRLR_LL_PMS_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_EVENT_SLV_ST_END (1<<3)
#define PSRAM_CTRLR_LL_EVENT_MST_ST_END (1<<4)
#define PSRAM_CTRLR_LL_EVENT_ECC_ERR (1<<5)

1
components/esp_hal_mspi/esp32c61/include/hal/psram_ctrlr_ll.h
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@@ -38,6 +38,7 @@ extern "C" {
#define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1)
#define PSRAM_CTRLR_LL_PMS_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_EVENT_SLV_ST_END (1<<3)
#define PSRAM_CTRLR_LL_EVENT_MST_ST_END (1<<4)
#define PSRAM_CTRLR_LL_EVENT_ECC_ERR (1<<5)

1
components/esp_hal_mspi/esp32h4/include/hal/psram_ctrlr_ll.h
View File

@@ -38,6 +38,7 @@ extern "C" {
#define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1)
#define PSRAM_CTRLR_LL_PMS_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_EVENT_SLV_ST_END (1<<3)
#define PSRAM_CTRLR_LL_EVENT_MST_ST_END (1<<4)
#define PSRAM_CTRLR_LL_EVENT_ECC_ERR (1<<5)

1
components/esp_hal_mspi/esp32p4/include/hal/psram_ctrlr_ll.h
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@@ -44,6 +44,7 @@ extern "C" {
#define PSRAM_CTRLR_LL_THRESH_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_PMS_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED 1
#define PSRAM_CTRLR_LL_EVENT_SLV_ST_END (1<<3)
#define PSRAM_CTRLR_LL_EVENT_MST_ST_END (1<<4)
#define PSRAM_CTRLR_LL_EVENT_ECC_ERR (1<<5)

4
components/esp_hw_support/mspi/mspi_intr/mspi_intr.c
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@@ -47,7 +47,7 @@ static void MSPI_ISR_ATTR mspi_isr_handler(void *arg)
#if MSPI_LL_ECC_INT_SUPPORTED
if (intr_events & MSPI_LL_EVENT_ECC_ERR) {
ESP_DRAM_LOGD(TAG, "ecc error");
ESP_DRAM_LOGE(TAG, "ecc error");
is_ecc_error = true;
}
#endif
@@ -58,7 +58,7 @@ static void MSPI_ISR_ATTR mspi_isr_handler(void *arg)
#endif
#if MSPI_LL_ADDR_INT_SUPPORTED
if (intr_events & MSPI_LL_EVENT_AXI_RADDR_ERR) {
ESP_DRAM_LOGE(TAG, "read addr error");
ESP_DRAM_LOGE(TAG, "read address invalid or misaligned");
}
if (intr_events & MSPI_LL_EVENT_AXI_WADDR_ERR) {
ESP_DRAM_LOGE(TAG, "write addr error");

6
components/esp_psram/system_layer/esp_psram_mspi.c
View File

@@ -45,6 +45,11 @@ static void PSRAM_ISR_ATTR mspi_psram_isr_handler(void *arg, uint32_t intr_event
ESP_DRAM_LOGE(TAG, "psram pms reject");
}
#endif
#if PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED
if (intr_events & PSRAM_CTRLR_LL_EVENT_AXI_RADDR_ERR) {
ESP_DRAM_LOGE(TAG, "psram read address invalid or misaligned");
}
#endif
#if PSRAM_CTRLR_LL_THRESH_INT_SUPPORTED
if (intr_events & PSRAM_CTRLR_LL_EVENT_RX_TRANS_OVF) {
ESP_DRAM_LOGE(TAG, "psram rx trans overflow");
@@ -67,6 +72,7 @@ static void PSRAM_ISR_ATTR mspi_psram_isr_handler_wrapper(void *arg)
psram_ctrlr_ll_clear_intr(PSRAM_CTRLR_LL_MSPI_ID_SYSTEM, intr_events);
ESP_DRAM_LOGE(TAG, "MSPI PSRAM error");
ESP_DRAM_LOGD(TAG, "intr_events: 0x%" PRIx32, intr_events);
mspi_psram_isr_handler(arg, intr_events);