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Merge branch 'doc/esp_idf_flash_pwr_description' into 'master'
docs(pm): add flash sleep strategy recommendations See merge request espressif/esp-idf!45689
This commit is contained in:
He Binglin
@@ -84,6 +84,7 @@ menu "Hardware Settings"
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select ESP_REGI2C_CTRL_FUNC_IN_IRAM
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depends on !SPIRAM || ESP_LDO_RESERVE_PSRAM || SOC_PSRAM_HAS_DEDICATED_LDO
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depends on !(IDF_TARGET_ESP32P4 && (ESP32P4_REV_MIN_FULL < 100))
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depends on !SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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default n
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help
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If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs
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@@ -227,7 +228,7 @@ menu "Hardware Settings"
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config ESP_SLEEP_SET_FLASH_DPD
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bool "Set SPI flash to deep power-down mode in light sleep"
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depends on (!APP_BUILD_TYPE_PURE_RAM_APP && !ESP_SLEEP_POWER_DOWN_FLASH && !SPI_FLASH_ROM_IMPL)
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default y if (IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H21)
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default y if SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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default y if (IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3)
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default n
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help
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@@ -237,11 +238,10 @@ menu "Hardware Settings"
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which will reduce the sleep current by about 10uA. And you can also use this option to reduce power
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consumption when using PSRAM
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NOTE: We have conducted sufficient testing on ESP32H21, ESP32H4 and ESP32P4(less v3). If you plan to
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use a customized flash chip, or if you are working with other ESP32-series chips, please make sure to
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check the corresponding flash datasheet or consult us directly. This is to ensure that using the B9h
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command to enter Deep Power-Down mode and ABh to exit Deep Power-Down mode will not introduce any
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potential issues.
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NOTE: We have conducted sufficient testing on ESP32-C5, ESP32-C61, ESP32-H21, ESP32-H4 and
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ESP32-P4 (less v3). If you plan to use a customized flash chip, or if you are working with other
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ESP32-series chips, please make sure to check the corresponding flash datasheet or consult us
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directly. This is to ensure that using the B9h command to enter Deep Power-Down mode and ABh to exit.
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config ESP_SLEEP_SPI_FLASH_ENTER_DPD_MODE_DELAY
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int "SPI Flash enter deep power-down time delay (in us)"
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@@ -1575,6 +1575,7 @@ esp_err_t esp_light_sleep_start(void)
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* will be set in `sleep_flags`.
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*/
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if (sleep_flags & RTC_SLEEP_PD_VDDSDIO) {
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#if !SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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/*
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* When VDD_SDIO power domain has to be turned off, the minimum sleep time of the
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* system needs to meet the sum below:
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@@ -1610,8 +1611,13 @@ esp_err_t esp_light_sleep_start(void)
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s_config.sleep_time_adjustment -= flash_enable_time_us;
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}
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}
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} else if (!(sleep_flags & RTC_SLEEP_PD_VDDSDIO)) {
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#else
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sleep_flags &= ~RTC_SLEEP_PD_VDDSDIO;
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#endif
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}
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#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
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if (!(sleep_flags & RTC_SLEEP_PD_VDDSDIO) && (sleep_flags & RTC_SLEEP_FLASH_DPD)) {
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const uint32_t flash_enable_dpd_us = spi_flash_dpd_get_enter_duration() + spi_flash_dpd_get_exit_duration();
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if (s_config.sleep_duration > flash_enable_dpd_us) {
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if (s_config.sleep_time_overhead_out < flash_enable_dpd_us) {
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@@ -1626,8 +1632,8 @@ esp_err_t esp_light_sleep_start(void)
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s_config.sleep_time_adjustment -= flash_enable_dpd_us;
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}
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}
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#endif
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}
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#endif
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periph_inform_out_light_sleep_overhead(s_config.sleep_time_adjustment - sleep_time_overhead_in);
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@@ -2955,9 +2961,20 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
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#endif
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#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
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if (!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
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// Flash power domain will disable DPD mode.
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pd_flags |= RTC_SLEEP_FLASH_DPD;
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{
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uint32_t pd_flags_for_dpd = pd_flags;
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#if SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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/* Light sleep never powers down the flash supply on these targets; an app may still set VDDSDIO
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* domain to OFF manually, and we later strip RTC_SLEEP_PD_VDDSDIO.
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* Mask the bit when deriving DPD so flash deep power-down is not suppressed. */
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pd_flags_for_dpd &= ~RTC_SLEEP_PD_VDDSDIO;
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#endif
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if (!(pd_flags_for_dpd & RTC_SLEEP_PD_VDDSDIO)) {
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// Flash power domain will disable DPD mode.
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pd_flags |= RTC_SLEEP_FLASH_DPD;
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} else {
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ESP_LOGW(TAG, "Flash DPD mode cannot be enabled when VDDSDIO is configured to power down.");
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}
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}
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#endif
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@@ -1463,6 +1463,10 @@ config SOC_PM_RETENTION_MODULE_NUM
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int
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default 32
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config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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bool
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default y
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config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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bool
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default y
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@@ -593,6 +593,8 @@
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#define SOC_PM_RETENTION_MODULE_NUM (32)
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#define SOC_PM_FLASH_KEEP_POWER_IN_LSLP (1) /*!<Keep flash on in light sleep to reduce wake latency and current leakage*/
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
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@@ -1103,6 +1103,10 @@ config SOC_PM_RETENTION_MODULE_NUM
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int
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default 32
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config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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bool
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default y
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config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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bool
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default y
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@@ -456,6 +456,8 @@
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#define SOC_PM_RETENTION_MODULE_NUM (32)
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#define SOC_PM_FLASH_KEEP_POWER_IN_LSLP (1) /*!<Keep flash on in light sleep to reduce wake latency and current leakage*/
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
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@@ -1023,6 +1023,10 @@ config SOC_PM_SUPPORT_PMU_CLK_ICG
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bool
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default y
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config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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bool
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default y
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config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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bool
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default y
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@@ -468,6 +468,8 @@
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#define SOC_PM_SUPPORT_PMU_CLK_ICG (1)
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#define SOC_PM_FLASH_KEEP_POWER_IN_LSLP (1) /*!<Keep flash on in light sleep to reduce wake latency*/
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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@@ -1231,6 +1231,10 @@ config SOC_PM_MODEM_LOCK_CLK_WORKAROUND
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bool
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default y
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config SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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bool
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default y
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config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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bool
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default y
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@@ -518,6 +518,8 @@
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#define SOC_PM_BBPLL_PD_IN_MODEM_STATE (1)
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#define SOC_PM_MODEM_LOCK_CLK_WORKAROUND (1) // In ESP32H4, the modem lock will lock the xtalx2, bbpll and other xpd state during modem2active.
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#define SOC_PM_FLASH_KEEP_POWER_IN_LSLP (1) /*!<Keep flash on in light sleep to reduce wake latency*/
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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@@ -282,15 +282,17 @@ This section introduces the recommended configuration and configuration steps fo
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.. only:: SOC_PM_SUPPORT_VDDSDIO_PD
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- Power down flash in light sleep (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
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.. only:: SOC_PM_SUPPORT_VDDSDIO_PD and not SOC_PM_FLASH_KEEP_POWER_IN_LSLP
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.. only:: SOC_SPIRAM_SUPPORTED
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- Power down flash in light sleep (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
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Due to the shared power pins between flash and PSRAM, cutting power to PSRAM would result in data loss. Therefore, to ensure light sleep does not disrupt program execution, enabling this option requires that the system does not utilize PSRAM.
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.. only:: SOC_SPIRAM_SUPPORTED
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Due to the shared power pins between flash and PSRAM, cutting power to PSRAM would result in data loss. Therefore, to ensure light sleep does not disrupt program execution, enabling this option requires that the system does not utilize PSRAM.
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.. only:: SOC_PM_SUPPORT_TOP_PD
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- Power down Digital Peripheral modules and all child power domains under the TOP power domain in light sleep (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
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- Power down Digital Peripheral modules and all child power domains under the TOP power domain in light sleep (:ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`)
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.. only:: SOC_PM_SUPPORT_RTC_PERIPH_PD
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@@ -343,7 +345,7 @@ Configuration Steps:
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Recommended Configuration
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+++++++++++++++++++++++++++++
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.. only:: esp32c6 or esp32c5
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.. only:: esp32c6
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.. list-table::
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:header-rows: 1
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@@ -400,6 +402,63 @@ Recommended Configuration
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.. note::
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Configurations not mentioned in the above table are set to default.
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.. only:: esp32c5
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.. list-table::
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:header-rows: 1
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:widths: 30 15
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* - Configuration Name
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- Configuration Status
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* - Enable power management component (:ref:`CONFIG_PM_ENABLE`)
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- ON
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* - Enable RTOS Tickless IDLE mode (:ref:`CONFIG_FREERTOS_USE_TICKLESS_IDLE`)
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- ON
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* - RTOS Tick rate (Hz) (:ref:`CONFIG_FREERTOS_HZ`)
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- 1000
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* - Minimum IDLE Tick count before entering sleep mode (:ref:`CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP`)
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- 3
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* - Put light sleep related codes in IRAM (:ref:`CONFIG_PM_SLP_IRAM_OPT`)
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- ON
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* - Put RTOS IDLE related codes in IRAM (:ref:`CONFIG_PM_RTOS_IDLE_OPT`)
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- OFF
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* - RTC slow clock source (:ref:`CONFIG_RTC_CLK_SRC`)
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- Internal 150 kHz OSC
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* - Disable all GPIO when chip at sleep (:ref:`CONFIG_PM_SLP_DISABLE_GPIO`)
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- ON
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* - Power down MAC and baseband (:ref:`CONFIG_ESP_PHY_MAC_BB_PD`)
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- ON
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* - Power down CPU (:ref:`CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP`)
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- ON
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* - Set flash into deep power-down mode in light sleep (:ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`)
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- ON
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* - ``max_freq_mhz``
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- The maximum CPU frequency supported by {IDF_TARGET_NAME}
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* - ``min_freq_mhz``
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- {CONFIG_XTAL_FREQ}
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* - ``light_sleep_enable``
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- true
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.. note::
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Configurations not mentioned in the above table are set to default.
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.. note::
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On {IDF_TARGET_NAME}, SPI flash need remains powered during light sleep and :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` is not available.
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.. only:: esp32s3
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.. list-table::
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@@ -491,47 +491,106 @@ By default, :cpp:func:`esp_deep_sleep_start` and :cpp:func:`esp_light_sleep_star
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In {IDF_TARGET_NAME}, there is only RTC FAST memory, so if some variables in the program are marked by ``RTC_DATA_ATTR``, ``RTC_SLOW_ATTR`` or ``RTC_FAST_ATTR`` attributes, all of them go to RTC FAST memory. It will be kept powered on by default. This can be overridden using :cpp:func:`esp_sleep_pd_config` function, if desired.
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Power-down of Flash
|
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^^^^^^^^^^^^^^^^^^^
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.. _spi_flash_power_down_dpd:
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By default, to avoid potential issues, :cpp:func:`esp_light_sleep_start` function does **not** power down flash. To be more specific, it takes time to power down the flash and during this period the system may be woken up, which then actually powers up the flash before this flash could be powered down completely. As a result, there is a chance that the flash may not work properly.
|
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Flash Entering Deep Power-Down Mode
|
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
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So, in theory, it is ok if you only wake up the system after the flash is completely powered down. However, in reality, the flash power-down period can be hard to predict (for example, this period can be much longer when you add filter capacitors to the flash's power supply circuit) and uncontrollable (for example, the asynchronous wake-up signals make the actual sleep time uncontrollable).
|
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For Light-sleep, ESP-IDF recommends lowering SPI Flash sleep current using **Deep Power-Down (DPD)** first: enable :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD` so the SPI Flash enters its deep power-down command mode while the supply rail remains on. Current draw is typically very low (often below 1 µA for many SPI Flash devices), without the wake-up delay of fully cycling the SPI Flash supply.
|
||||
|
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In almost all use cases, DPD offers better overall trade-offs than cutting SPI Flash supply power—both safer for execution and still very low power.
|
||||
|
||||
.. note::
|
||||
**Mutually exclusive strategies:** Power-down SPI Flash during Light-sleep (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` or ``esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_OFF)``) **cannot be combined** with DPD. Kconfig exposes :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD` only when :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` is disabled.
|
||||
|
||||
.. warning::
|
||||
|
||||
If a filter capacitor is added to your flash power supply circuit, please do everything possible to avoid powering down flash.
|
||||
Before using this feature, check the datasheet of the SPI Flash device used on your chip to ensure it supports the Deep Power-Down mode.
|
||||
|
||||
Therefore, it is recommended not to power down flash when using ESP-IDF. For power-sensitive applications, it is recommended to use Kconfig option :ref:`CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND` to reduce the power consumption of the flash during Light-sleep, instead of powering down the flash.
|
||||
.. _spi_flash_power_down:
|
||||
|
||||
Power-down of Flash
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
By default, to avoid potential issues, :cpp:func:`esp_light_sleep_start` function does **not** power down SPI Flash. To be more specific, it takes time to power down the SPI Flash and during this period the system may be woken up, which then actually powers up the SPI Flash before this SPI Flash could be powered down completely. As a result, there is a chance that the SPI Flash may not work properly.
|
||||
|
||||
So, in theory, it is ok if you only wake up the system after the SPI Flash is completely powered down. However, in reality, the SPI Flash power-down period can be hard to predict (for example, this period can be much longer when you add filter capacitors to the SPI Flash's power supply circuit) and uncontrollable (for example, the asynchronous wake-up signals make the actual sleep time uncontrollable).
|
||||
|
||||
.. warning::
|
||||
|
||||
If a filter capacitor is added to your SPI Flash power supply circuit, please do everything possible to avoid powering down SPI Flash.
|
||||
|
||||
Therefore, it is recommended not to power down SPI Flash when using ESP-IDF. For power-sensitive applications, it is recommended to use Kconfig option :ref:`CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND` to reduce the power consumption of the SPI Flash during Light-sleep, instead of powering down the SPI Flash.
|
||||
|
||||
.. only:: SOC_SPIRAM_SUPPORTED
|
||||
|
||||
It is worth mentioning that PSRAM has a similar Kconfig option :ref:`CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND`.
|
||||
|
||||
However, for those who have fully understood the risk and are still willing to power down the flash to further reduce the power consumption, please check the following mechanisms:
|
||||
However, for those who have fully understood the risk and are still willing to power down the SPI Flash to further reduce the power consumption, please check the following mechanisms:
|
||||
|
||||
.. list::
|
||||
|
||||
- Setting Kconfig option :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` only powers down the flash when the RTC timer is the only wake-up source **and** the sleep time is longer than the flash power-down period.
|
||||
- Calling ``esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_OFF)`` powers down flash when the RTC timer is not enabled as a wakeup source **or** the sleep time is longer than the flash power-down period.
|
||||
- Setting Kconfig option :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` only powers down the SPI Flash when the RTC timer is the only wake-up source **and** the sleep time is longer than the SPI Flash power-down period.
|
||||
- Calling ``esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_OFF)`` powers down SPI Flash when the RTC timer is not enabled as a wakeup source **or** the sleep time is longer than the SPI Flash power-down period.
|
||||
|
||||
.. note::
|
||||
|
||||
.. list::
|
||||
|
||||
- ESP-IDF does not provide any mechanism that can power down the flash in all conditions when Light-sleep.
|
||||
- :cpp:func:`esp_deep_sleep_start` function forces power down flash regardless of user configuration.
|
||||
- ESP-IDF does not provide any mechanism that can power down the SPI Flash in all conditions when Light-sleep.
|
||||
- :cpp:func:`esp_deep_sleep_start` function forces power down SPI Flash regardless of user configuration.
|
||||
|
||||
Flash Entering Deep Power-Down Mode
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. _spi_flash_sleep_strategy_recommendations:
|
||||
|
||||
In addition to reducing power consumption by completely powering off the flash, you can further lower flash power usage during sleep by enabling the Kconfig option :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`. Compared with fully cutting off the flash power, this feature avoids the extra delay caused by re-powering the flash when the chip wakes up from sleep, while still achieving extremely low power consumption. Most flashes draw less than 1 µA when entering Deep Power-Down (DPD) mode.
|
||||
Flash Sleep Strategy Recommendations
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
In almost all use cases, using DPD mode provides better overall benefits than fully powering off the flash, offering both improved safety and lower power consumption.
|
||||
In sleep scenarios, the SPI Flash handling method directly affects system safety, and power consumption. Different application scenarios prioritize these factors differently, so it is important to choose an appropriate SPI Flash sleep strategy.
|
||||
|
||||
.. warning::
|
||||
Keep Flash Powered On
|
||||
"""""""""""""""""""""""""""""
|
||||
|
||||
Before using this feature, check the datasheet of the flash device used on your chip to ensure it supports the Deep Power-Down mode.
|
||||
The standby power consumption of different SPI Flash varies. In ESP series chips, the standby power consumption of SPI Flash is typically below 30 µA. In the following scenarios, it is recommended to keep the SPI Flash powered on:
|
||||
|
||||
1. The system has extremely high stability requirements and cannot accept any potential risks from SPI Flash power-off.
|
||||
|
||||
2. Sleep duration is short or unpredictable, for example, when asynchronous wake-up sources exist (GPIO, UART, etc.).
|
||||
|
||||
3. Large filter capacitors exist in the SPI Flash power supply circuit, making it difficult to estimate the actual SPI Flash power-down time.
|
||||
|
||||
In the above cases, keeping the SPI Flash powered on is the most conservative and safest choice, but note that its standby power consumption is relatively high (about 10-30 µA).
|
||||
|
||||
Flash Entering Deep Power-Down (DPD) Mode
|
||||
"""""""""""""""""""""""""""""""""""""""""
|
||||
|
||||
When standby power is still too high, prefer **Deep Power-Down** via :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`; see :ref:`spi_flash_power_down_dpd` for figures, timings, and how to enable it.
|
||||
|
||||
DPD mode is suitable for the following scenarios:
|
||||
|
||||
1. Significant reduction in SPI Flash power consumption during sleep is needed, but the risk of SPI Flash re-powering should be avoided.
|
||||
|
||||
2. Sleep duration is short or unpredictable, for example, when asynchronous wake-up sources exist (GPIO, UART, etc.).
|
||||
|
||||
3. SPI Flash chip used explicitly supports Deep Power-Down mode.
|
||||
|
||||
.. only:: not SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
|
||||
Power Down Flash
|
||||
""""""""""""""""""""
|
||||
|
||||
You can refer to :ref:`spi_flash_power_down` to power down the SPI Flash during sleep. After the following conditions are met or after thorough evaluation, you may consider this strategy:
|
||||
|
||||
1. The application has strict requirements for extremely low power consumption.
|
||||
|
||||
2. Wake-up sources are controllable, typically only RTC timer wake-up sources are enabled.
|
||||
|
||||
3. It can be ensured that the actual sleep time is greater than the time required for the SPI Flash to completely power down. For ESP series chips, the time required for the SPI Flash to completely power down may be greater than 300ms. If parallel capacitors exist in the SPI Flash power supply circuit, longer sleep time may be required.
|
||||
|
||||
4. If the sleep time is too short, the power consumption during the SPI Flash power-on and power-down processes may exceed the power consumption when keeping it powered on.
|
||||
|
||||
5. There is sufficient control over SPI Flash power supply and IO states to avoid SPI Flash leakage due to pin pull-up during sleep.
|
||||
|
||||
Since the SPI Flash power-down process is greatly affected by hardware design, IO impedance characteristics, power supply, and environmental factors, ESP-IDF cannot guarantee that the SPI Flash will be safely powered down in Light-sleep mode. Therefore, this method is only suitable for scenarios with controllable risks and thorough verification.
|
||||
|
||||
Configuring IOs (Deep-sleep Only)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
@@ -282,11 +282,13 @@ Light-sleep 模式配置
|
||||
|
||||
.. only:: SOC_PM_SUPPORT_VDDSDIO_PD
|
||||
|
||||
- 在 light sleep 状态关闭 flash 供电 (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
|
||||
.. only:: SOC_PM_SUPPORT_VDDSDIO_PD and not SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
|
||||
.. only:: SOC_SPIRAM_SUPPORTED
|
||||
- 在 light sleep 状态关闭 flash 供电 (:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`)
|
||||
|
||||
由于 flash 和 PSRAM 共用供电管脚，PSRAM 关闭供电将会导致数据丢失，因此，为保证 light sleep 不破坏程序运行状态，启用该选项的前提是系统没有使用 PSRAM。
|
||||
.. only:: SOC_SPIRAM_SUPPORTED
|
||||
|
||||
由于 flash 和 PSRAM 共用供电管脚，PSRAM 关闭供电将会导致数据丢失，因此，为保证 light sleep 不破坏程序运行状态，启用该选项的前提是系统没有使用 PSRAM。
|
||||
|
||||
.. only:: SOC_PM_SUPPORT_TOP_PD
|
||||
|
||||
@@ -343,7 +345,7 @@ Light-sleep 模式配置
|
||||
推荐配置
|
||||
+++++++++
|
||||
|
||||
.. only:: esp32c6 or esp32c5
|
||||
.. only:: esp32c6
|
||||
|
||||
.. list-table::
|
||||
:header-rows: 1
|
||||
@@ -400,6 +402,63 @@ Light-sleep 模式配置
|
||||
.. note::
|
||||
上表中不涉及的配置均是默认。
|
||||
|
||||
.. only:: esp32c5
|
||||
|
||||
.. list-table::
|
||||
:header-rows: 1
|
||||
:widths: 30 15
|
||||
|
||||
* - 配置名称
|
||||
- 设置情况
|
||||
|
||||
* - 启用电源管理组件 (:ref:`CONFIG_PM_ENABLE`)
|
||||
- ON
|
||||
|
||||
* - 启用 Tickless IDLE 模式 (:ref:`CONFIG_FREERTOS_USE_TICKLESS_IDLE`)
|
||||
- ON
|
||||
|
||||
* - RTOS Tick rate (Hz) (:ref:`CONFIG_FREERTOS_HZ`)
|
||||
- 1000
|
||||
|
||||
* - 进入睡眠模式前最小 IDLE Tick 数 (:ref:`CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP`)
|
||||
- 3
|
||||
|
||||
* - 将 light sleep 相关代码放置在片内 RAM 中 (:ref:`CONFIG_PM_SLP_IRAM_OPT`)
|
||||
- ON
|
||||
|
||||
* - 将 RTOS IDLE 相关代码放置在片内 RAM 中 (:ref:`CONFIG_PM_RTOS_IDLE_OPT`)
|
||||
- OFF
|
||||
|
||||
* - RTC 慢速时钟源 (:ref:`CONFIG_RTC_CLK_SRC`)
|
||||
- 内部 150 kHz 振荡器
|
||||
|
||||
* - 芯片休眠时禁用所有 GPIO (:ref:`CONFIG_PM_SLP_DISABLE_GPIO`)
|
||||
- ON
|
||||
|
||||
* - 关闭 MAC 和基带 (:ref:`CONFIG_ESP_PHY_MAC_BB_PD`)
|
||||
- ON
|
||||
|
||||
* - 关闭 CPU (:ref:`CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP`)
|
||||
- ON
|
||||
|
||||
* - 在 light sleep 状态配置 flash 进入 deep power-down 模式 (:ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`)
|
||||
- ON
|
||||
|
||||
* - ``max_freq_mhz``
|
||||
- {IDF_TARGET_NAME} 支持的最大 CPU 频率
|
||||
|
||||
* - ``min_freq_mhz``
|
||||
- {CONFIG_XTAL_FREQ}
|
||||
|
||||
* - ``light_sleep_enable``
|
||||
- true
|
||||
|
||||
.. note::
|
||||
上表中不涉及的配置均是默认。
|
||||
|
||||
.. note::
|
||||
在 {IDF_TARGET_NAME} 上，light sleep 期间 SPI flash 供电需保持开启，不提供 :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH`。
|
||||
|
||||
.. only:: esp32s3
|
||||
|
||||
.. list-table::
|
||||
|
||||
@@ -491,47 +491,106 @@ RTC 外设和内存断电
|
||||
|
||||
{IDF_TARGET_NAME} 中只有 RTC 高速内存，因此，如果程序中的某些值被标记为 ``RTC_DATA_ATTR``、``RTC_SLOW_ATTR`` 或 ``RTC_FAST_ATTR`` 属性，那么所有这些值都将被存入 RTC 高速内存，默认情况下保持供电。如有需要，也可以使用函数 :cpp:func:`esp_sleep_pd_config` 对其进行修改。
|
||||
|
||||
flash 断电
|
||||
^^^^^^^^^^
|
||||
.. _spi_flash_power_down_dpd:
|
||||
|
||||
默认情况下，调用函数 :cpp:func:`esp_light_sleep_start` 后，flash **不会** 断电，因为在 sleep 过程中断电 flash 存在风险。具体而言，flash 断电需要时间，但是在此期间，系统有可能被唤醒，导致 flash 重新被上电。此时，断电尚未完成又重新上电的硬件行为有可能导致 flash 无法正常工作。
|
||||
SPI Flash 进入 deep power-down 模式
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
理论上讲，在 flash 完全断电后可以仅唤醒系统，然而现实情况是 flash 断电所需的时间很难预测。如果用户为 flash 供电电路添加了滤波电容，断电所需时间可能会更长。此外，即使可以预知 flash 彻底断电所需的时间，有时也不能通过设置足够长的睡眠时间来确保 flash 断电的安全（比如，突发的异步唤醒源会使得实际的睡眠时间不可控）。
|
||||
为降低 Light-sleep 期间 SPI Flash 的功耗，ESP-IDF **优先推荐**采用 **Deep Power-Down（DPD）**：通过启用配置项 :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`，令 SPI Flash 在供电保持开启的前提下进入器件内部的深度休眠指令状态。多数 SPI Flash 在 DPD 下电流可降至极低水平（常低于 1 µA），同时可避免反复上下电带来的唤醒延迟。
|
||||
|
||||
在几乎所有应用场景中，相较彻底切断 SPI Flash 供电，DPD 在安全性与功耗之间通常是更好的折中。
|
||||
|
||||
.. note::
|
||||
**两种方式互斥：** Light-sleep 下的 SPI Flash **断电**（:ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` 或通过 ``esp_sleep_pd_config`` 将 ``ESP_PD_DOMAIN_VDDSDIO`` 置为关闭）与 **DPD** **不可同时使用**， 在 menuconfig 中仅能在禁用 :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` 后再启用 :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`。
|
||||
|
||||
.. warning::
|
||||
|
||||
如果在 flash 的供电电路上添加了滤波电容，那么应当尽一切可能避免 flash 断电。
|
||||
使用该功能前需要查阅使用芯片所搭载的 SPI Flash 的技术手册是否支持 deep power-down 模式。
|
||||
|
||||
因为这些不可控的因素，ESP-IDF 很难保证 flash 断电的绝对安全。因此 ESP-IDF 不推荐用户断电 flash。对于一些功耗敏感型应用，可以通过设置 Kconfig 配置项 :ref:`CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND` 来减少 Light-sleep 期间 flash 的功耗。这种方式在几乎所有场景下都要比断电 flash 更好，兼顾了安全性和功耗。
|
||||
.. _spi_flash_power_down:
|
||||
|
||||
SPI Flash 断电
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
默认情况下，调用函数 :cpp:func:`esp_light_sleep_start` 后，SPI Flash **不会** 断电，因为在 sleep 过程中断电 SPI Flash 存在风险。具体而言，SPI Flash 断电需要时间，但是在此期间，系统有可能被唤醒，导致 SPI Flash 重新被上电。此时，断电尚未完成又重新上电的硬件行为有可能导致 SPI Flash 无法正常工作。
|
||||
|
||||
理论上讲，在 SPI Flash 完全断电后可以仅唤醒系统，然而现实情况是 SPI Flash 断电所需的时间很难预测。如果用户为 SPI Flash 供电电路添加了滤波电容，断电所需时间可能会更长。此外，即使可以预知 SPI Flash 彻底断电所需的时间，有时也不能通过设置足够长的睡眠时间来确保 SPI Flash 断电的安全（比如，突发的异步唤醒源会使得实际的睡眠时间不可控）。
|
||||
|
||||
.. warning::
|
||||
|
||||
如果在 SPI Flash 的供电电路上添加了滤波电容，那么应当尽一切可能避免 SPI Flash 断电。
|
||||
|
||||
因为这些不可控的因素，ESP-IDF 很难保证 SPI Flash 断电的绝对安全。因此 ESP-IDF 不推荐用户断电 SPI Flash。对于一些功耗敏感型应用，可以通过设置 Kconfig 配置项 :ref:`CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND` 来减少 Light-sleep 期间 SPI Flash 的功耗。这种方式在几乎所有场景下都要比断电 SPI Flash 更好，兼顾了安全性和功耗。
|
||||
|
||||
.. only:: SOC_SPIRAM_SUPPORTED
|
||||
|
||||
值得一提的是，PSRAM 也有一个类似的 Kconfig 配置项 :ref:`CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND`。
|
||||
|
||||
考虑到有些用户能够充分评估断电 flash 的风险，并希望通过断电 flash 来获得更低的功耗，因此 ESP-IDF 提供了两种断电 flash 的机制：
|
||||
考虑到有些用户能够充分评估断电 SPI Flash 的风险，并希望通过断电 SPI Flash 来获得更低的功耗，因此 ESP-IDF 提供了两种断电 SPI Flash 的机制：
|
||||
|
||||
.. list::
|
||||
|
||||
- 设置 Kconfig 配置项 :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` 将使 ESP-IDF 以一个严格的条件来断电 flash。严格的条件具体指的是，RTC timer 是唯一的唤醒源 **且** 睡眠时间比 flash 彻底断电所需时间更长。
|
||||
- 调用函数 ``esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_OFF)`` 将使 ESP-IDF 以一个宽松的条件来断电 flash。宽松的条件具体指的是 RTC timer 唤醒源未被使能 **或** 睡眠时间比 flash 彻底断电所需时间更长。
|
||||
- 设置 Kconfig 配置项 :ref:`CONFIG_ESP_SLEEP_POWER_DOWN_FLASH` 将使 ESP-IDF 以一个严格的条件来断电 SPI Flash。严格的条件具体指的是，RTC timer 是唯一的唤醒源 **且** 睡眠时间比 SPI Flash 彻底断电所需时间更长。
|
||||
- 调用函数 ``esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_OFF)`` 将使 ESP-IDF 以一个宽松的条件来断电 SPI Flash。宽松的条件具体指的是 RTC timer 唤醒源未被使能 **或** 睡眠时间比 SPI Flash 彻底断电所需时间更长。
|
||||
|
||||
.. note::
|
||||
|
||||
.. list::
|
||||
|
||||
- Light-sleep 模式下，ESP-IDF 没有提供保证 flash 一定会被断电的机制。
|
||||
- 不管用户的配置如何，函数 :cpp:func:`esp_deep_sleep_start` 都会强制断电 flash。
|
||||
- Light-sleep 模式下，ESP-IDF 没有提供保证 SPI Flash 一定会被断电的机制。
|
||||
- 不管用户的配置如何，函数 :cpp:func:`esp_deep_sleep_start` 都会强制断电 SPI Flash
|
||||
|
||||
flash 进入 deep power-down 模式
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. _spi_flash_sleep_strategy_recommendations:
|
||||
|
||||
除了通过让 flash 完全断电来降低芯片功耗之外，还可以通过启用 Kconfig 配置项 :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD`，进一步减少休眠期间 flash 的功耗。与直接对 flash 断电相比，该功能能够避免芯片从休眠唤醒时 flash 重新上电所带来的额外延迟，同时也能保持极低的功耗。大多数 flash 在进入 Deep Power-Down（DPD）模式后电流消耗低于 1 µA。
|
||||
SPI Flash 休眠策略选择建议
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
在几乎所有应用场景中，使用 DPD 模式都比直接断电 flash 更具优势，兼顾了安全性与低功耗表现。
|
||||
在休眠场景下，SPI Flash 的处理方式直接影响系统的安全性、功耗。不同应用场景对这些因素的侧重不同，因此需要选择合适的 SPI Flash 休眠策略。
|
||||
|
||||
.. warning::
|
||||
SPI Flash 不掉电
|
||||
""""""""""""""""""""
|
||||
|
||||
使用该功能前需要查阅使用芯片所搭载的 flash 的技术手册是否支持 deep power-down 模式。
|
||||
不同 SPI Flash 的待机功耗不一致，在 ESP 系列芯片中，SPI Flash 的待机功耗通常低于 30 µA，在以下场景中，建议保持 SPI Flash 不掉电：
|
||||
|
||||
1. 系统对稳定性要求极高，无法接受 SPI Flash 掉电带来的任何潜在风险。
|
||||
|
||||
2. 休眠时间较短或不可预测，例如存在异步唤醒源（GPIO、UART 等）。
|
||||
|
||||
3. SPI Flash 供电电路中存在较大的滤波电容，导致 SPI Flash 实际断电时间难以估计。
|
||||
|
||||
在上述情况下，保持 SPI Flash 供电是最保守、也是最安全的选择，但需要注意其待机功耗相对较高 (约 10-30 µA)。
|
||||
|
||||
SPI Flash 进入 deep power-down（DPD）模式
|
||||
""""""""""""""""""""""""""""""""""""""""""
|
||||
|
||||
若待机功耗仍偏高，应优先采用 **Deep Power-Down（DPD）**，通过 :ref:`CONFIG_ESP_SLEEP_SET_FLASH_DPD` 降低休眠电流；功耗数据、时序及启用方式参见前文 :ref:`spi_flash_power_down_dpd`。
|
||||
|
||||
DPD 模式适用于以下场景：
|
||||
|
||||
1. 需要显著降低休眠期间 SPI Flash 的功耗，但又希望避免 SPI Flash 重新上电的风险。
|
||||
|
||||
2. 休眠时间较短或不可预测，例如存在异步唤醒源（GPIO、UART 等）。
|
||||
|
||||
3. 使用的 SPI Flash 芯片明确支持 Deep Power-Down 模式。
|
||||
|
||||
.. only:: not SOC_PM_FLASH_KEEP_POWER_IN_LSLP
|
||||
|
||||
SPI Flash 掉电
|
||||
"""""""""""""""""
|
||||
|
||||
可以参考 :ref:`spi_flash_power_down` 实现在休眠中掉电 SPI Flash。在以下条件满足或经过充分评估后，可以考虑该策略：
|
||||
|
||||
1. 应用对极低功耗有严格要求。
|
||||
|
||||
2. 唤醒源可控，通常仅启用 RTC timer 唤醒源。
|
||||
|
||||
3. 能够确保实际睡眠时间大于 SPI Flash 彻底断电所需时间。对于 ESP 系列芯片，SPI Flash 彻底断电所需时间可能大于 300ms。如果 SPI Flash 供电电路中存在并联电容，可能需要更长的睡眠时间。
|
||||
|
||||
4. 如果休眠时间过短，SPI Flash 上电和下电过程所消耗的功耗可能会超过保持供电时的功耗。
|
||||
|
||||
5. 对 SPI Flash 供电及 IO 状态有充分控制，休眠时避免因为管脚上拉导致 SPI Flash 漏电。
|
||||
|
||||
由于 SPI Flash 的断电过程受硬件设计、IO 阻抗特性、供电以及环境因素影响较大，ESP-IDF 无法保证在 Light-sleep 模式下 SPI Flash 一定能够安全断电，因此该方式仅适用于风险可控且经过充分验证的场景。
|
||||
|
||||
配置 IO（仅适用于 Deep-sleep）
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Reference in New Issue
Block a user