mirror of
https://github.com/espressif/esp-idf.git
synced 2026-05-28 16:46:31 +03:00
feat(gdma): move gdma sleep retention info from esp_hal_dma to esp_driver_dma
This commit is contained in:
morris
@@ -10,7 +10,8 @@ set(srcs "src/esp_dma_utils.c" "src/gdma_link.c")
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if(CONFIG_SOC_GDMA_SUPPORTED)
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list(APPEND srcs "src/gdma.c")
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if(CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION AND CONFIG_SOC_PAU_SUPPORTED)
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list(APPEND srcs "src/gdma_sleep_retention.c")
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list(APPEND srcs "src/gdma_sleep.c")
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list(APPEND srcs "${target}/gdma_retention.c")
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endif()
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if(CONFIG_SOC_GDMA_SUPPORT_ETM)
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list(APPEND srcs "src/gdma_etm.c")
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@@ -40,6 +41,7 @@ endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS ${public_include}
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PRIV_INCLUDE_DIRS "src"
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REQUIRES ${requires}
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PRIV_REQUIRES esp_mm efuse
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LDFRAGMENTS "linker.lf"
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144
components/esp_driver_dma/esp32c5/gdma_retention.c
Normal file
144
components/esp_driver_dma/esp32c5/gdma_retention.c
Normal file
@@ -0,0 +1,144 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "gdma_priv.h"
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#include "soc/ahb_dma_reg.h"
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/* AHB_DMA Channel (Group0, Pair0) Registers Context
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Include: AHB_DMA_MISC_CONF_REG
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AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
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AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
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AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
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AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG
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AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG
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AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
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AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
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AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
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AHB_DMA_MODULE_CLK_EN_REG
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*/
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#define G0P0_RETENTION_REGS_CNT_0 13
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#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
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#define G0P0_RETENTION_REGS_CNT_1 11
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#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x2dc)
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static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
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static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0x0c900000, 0x601, 0x0};
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static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
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[0] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
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G0P0_RETENTION_REGS_CNT_0, 0, 0, \
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g0p0_regs_map0[0], g0p0_regs_map0[1], \
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g0p0_regs_map0[2], g0p0_regs_map0[3]), \
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.owner = GDMA_RETENTION_ENTRY
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}, \
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[1] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
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G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
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G0P0_RETENTION_REGS_CNT_1, 0, 0, \
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g0p0_regs_map1[0], g0p0_regs_map1[1], \
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g0p0_regs_map1[2], g0p0_regs_map1[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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};
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/* AHB_DMA Channel (Group0, Pair1) Registers Context
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Include: AHB_DMA_MISC_CONF_REG
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AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
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AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
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AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
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AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG
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AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG
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AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
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AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
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AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
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AHB_DMA_MODULE_CLK_EN_REG
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*/
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#define G0P1_RETENTION_REGS_CNT_0 13
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#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
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#define G0P1_RETENTION_REGS_CNT_1 11
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#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x304)
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static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
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static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x434800, 0x18, 0x0};
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static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
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[0] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
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G0P1_RETENTION_REGS_CNT_0, 0, 0, \
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g0p1_regs_map0[0], g0p1_regs_map0[1], \
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g0p1_regs_map0[2], g0p1_regs_map0[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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[1] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
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G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
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G0P1_RETENTION_REGS_CNT_1, 0, 0, \
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g0p1_regs_map1[0], g0p1_regs_map1[1], \
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g0p1_regs_map1[2], g0p1_regs_map1[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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};
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/* AHB_DMA Channel (Group0, Pair2) Registers Context
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Include: AHB_DMA_MISC_CONF_REG
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AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
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AHB_DMA_IN_PERI_SEL_CH2_REG
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AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_PRI_CH2_REG
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AHB_DMA_OUT_PERI_SEL_CH2_REG
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AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG
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AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG
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AHB_DMA_RX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH2_REG
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AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
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AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
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AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
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AHB_DMA_MODULE_CLK_EN_REG
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*/
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#define G0P2_RETENTION_REGS_CNT_0 8
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#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
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#define G0P2_RETENTION_REGS_CNT_1 16
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#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x250)
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static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x604c0000};
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static const uint32_t g0p2_regs_map1[4] = {0x1813, 0x1800000, 0x72600000, 0x3008};
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static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
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[0] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
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G0P2_RETENTION_REGS_CNT_0, 0, 0, \
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g0p2_regs_map0[0], g0p2_regs_map0[1], \
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g0p2_regs_map0[2], g0p2_regs_map0[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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[1] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
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G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
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G0P2_RETENTION_REGS_CNT_1, 0, 0, \
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g0p2_regs_map1[0], g0p2_regs_map1[1], \
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g0p2_regs_map1[2], g0p2_regs_map1[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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};
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const gdma_retention_desc_t gdma_retention_infos[1][3] = {
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[0] = {
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[0] = {
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gdma_g0p0_regs_retention,
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ARRAY_SIZE(gdma_g0p0_regs_retention),
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SLEEP_RETENTION_MODULE_GDMA_CH0,
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},
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[1] = {
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gdma_g0p1_regs_retention,
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ARRAY_SIZE(gdma_g0p1_regs_retention),
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SLEEP_RETENTION_MODULE_GDMA_CH1,
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},
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[2] = {
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gdma_g0p2_regs_retention,
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ARRAY_SIZE(gdma_g0p2_regs_retention),
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SLEEP_RETENTION_MODULE_GDMA_CH2,
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}
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}
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};
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99
components/esp_driver_dma/esp32c6/gdma_retention.c
Normal file
99
components/esp_driver_dma/esp32c6/gdma_retention.c
Normal file
@@ -0,0 +1,99 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "gdma_priv.h"
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#include "soc/gdma_reg.h"
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/* GDMA Channel (Group0, Pair0) Registers Context
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Include: GDMA_MISC_CONF_REG /
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GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
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GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
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GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
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*/
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#define G0P0_RETENTION_REGS_CNT 13
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#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG
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static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
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static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
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[0] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
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G0P0_RETENTION_REGS_CNT, 0, 0, \
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g0p0_regs_map[0], g0p0_regs_map[1], \
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g0p0_regs_map[2], g0p0_regs_map[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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};
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/* GDMA Channel (Group0, Pair1) Registers Context
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Include: GDMA_MISC_CONF_REG /
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GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
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GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
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GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
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*/
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#define G0P1_RETENTION_REGS_CNT 13
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#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG
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static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
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static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
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[0] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
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G0P1_RETENTION_REGS_CNT, 0, 0, \
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g0p1_regs_map[0], g0p1_regs_map[1], \
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g0p1_regs_map[2], g0p1_regs_map[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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};
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/* GDMA Channel (Group0, Pair2) Registers Context
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Include: GDMA_MISC_CONF_REG /
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GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
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GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
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GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
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*/
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#define G0P2_RETENTION_REGS_CNT_0 6
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#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
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#define G0P2_RETENTION_REGS_CNT_1 7
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#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
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static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
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static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
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static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
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[0] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
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G0P2_RETENTION_REGS_CNT_0, 0, 0, \
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g0p2_regs_map0[0], g0p2_regs_map0[1], \
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g0p2_regs_map0[2], g0p2_regs_map0[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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[1] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
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G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
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G0P2_RETENTION_REGS_CNT_1, 0, 0, \
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g0p2_regs_map1[0], g0p2_regs_map1[1], \
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g0p2_regs_map1[2], g0p2_regs_map1[3]), \
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.owner = GDMA_RETENTION_ENTRY
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},
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};
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const gdma_retention_desc_t gdma_retention_infos[1][3] = {
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[0] = {
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[0] = {
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gdma_g0p0_regs_retention,
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ARRAY_SIZE(gdma_g0p0_regs_retention),
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SLEEP_RETENTION_MODULE_GDMA_CH0,
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},
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[1] = {
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gdma_g0p1_regs_retention,
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ARRAY_SIZE(gdma_g0p1_regs_retention),
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SLEEP_RETENTION_MODULE_GDMA_CH1,
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},
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[2] = {
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gdma_g0p2_regs_retention,
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ARRAY_SIZE(gdma_g0p2_regs_retention),
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SLEEP_RETENTION_MODULE_GDMA_CH2,
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},
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}
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};
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99
components/esp_driver_dma/esp32c61/gdma_retention.c
Normal file
99
components/esp_driver_dma/esp32c61/gdma_retention.c
Normal file
@@ -0,0 +1,99 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "gdma_priv.h"
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#include "soc/ahb_dma_reg.h"
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/* AHB_DMA Channel (Group0, Pair0) Registers Context
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Include: AHB_DMA_MISC_CONF_REG
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||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
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||||
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AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG
|
||||
AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
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||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
|
||||
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT_0 13
|
||||
#define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG
|
||||
#define G0P0_RETENTION_REGS_CNT_1 12
|
||||
#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG
|
||||
static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
|
||||
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
|
||||
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p0_regs_map0[0], g0p0_regs_map0[1], \
|
||||
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
|
||||
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p0_regs_map1[0], g0p0_regs_map1[1], \
|
||||
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
|
||||
|
||||
AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG
|
||||
AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
|
||||
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
*/
|
||||
#define G0P1_RETENTION_REGS_CNT_0 13
|
||||
#define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG
|
||||
#define G0P1_RETENTION_REGS_CNT_1 12
|
||||
#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG
|
||||
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
|
||||
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
|
||||
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p1_regs_map0[0], g0p1_regs_map0[1], \
|
||||
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
|
||||
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p1_regs_map1[0], g0p1_regs_map1[1], \
|
||||
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_retention_desc_t gdma_retention_infos[1][2] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
}
|
||||
};
|
||||
99
components/esp_driver_dma/esp32h2/gdma_retention.c
Normal file
99
components/esp_driver_dma/esp32h2/gdma_retention.c
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "gdma_priv.h"
|
||||
#include "soc/gdma_reg.h"
|
||||
|
||||
/* GDMA Channel (Group0, Pair0) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
|
||||
GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
|
||||
GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT 13
|
||||
#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG
|
||||
static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
|
||||
G0P0_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p0_regs_map[0], g0p0_regs_map[1], \
|
||||
g0p0_regs_map[2], g0p0_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair1) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
|
||||
GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
|
||||
GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
|
||||
*/
|
||||
#define G0P1_RETENTION_REGS_CNT 13
|
||||
#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG
|
||||
static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
|
||||
G0P1_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p1_regs_map[0], g0p1_regs_map[1], \
|
||||
g0p1_regs_map[2], g0p1_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair2) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
|
||||
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
|
||||
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 6
|
||||
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
|
||||
#define G0P2_RETENTION_REGS_CNT_1 7
|
||||
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_retention_desc_t gdma_retention_infos[1][3] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
gdma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2,
|
||||
}
|
||||
}
|
||||
};
|
||||
99
components/esp_driver_dma/esp32h21/gdma_retention.c
Normal file
99
components/esp_driver_dma/esp32h21/gdma_retention.c
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "gdma_priv.h"
|
||||
#include "soc/gdma_reg.h"
|
||||
|
||||
/* GDMA Channel (Group0, Pair0) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
|
||||
GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
|
||||
GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT 13
|
||||
#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG
|
||||
static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
|
||||
G0P0_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p0_regs_map[0], g0p0_regs_map[1], \
|
||||
g0p0_regs_map[2], g0p0_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair1) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
|
||||
GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
|
||||
GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
|
||||
*/
|
||||
#define G0P1_RETENTION_REGS_CNT 13
|
||||
#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG
|
||||
static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
|
||||
G0P1_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p1_regs_map[0], g0p1_regs_map[1], \
|
||||
g0p1_regs_map[2], g0p1_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair2) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
|
||||
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
|
||||
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 6
|
||||
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
|
||||
#define G0P2_RETENTION_REGS_CNT_1 7
|
||||
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_retention_desc_t gdma_retention_infos[1][3] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
gdma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2,
|
||||
}
|
||||
}
|
||||
};
|
||||
275
components/esp_driver_dma/esp32h4/gdma_retention.c
Normal file
275
components/esp_driver_dma/esp32h4/gdma_retention.c
Normal file
@@ -0,0 +1,275 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "gdma_priv.h"
|
||||
#include "soc/ahb_dma_reg.h"
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair0) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG
|
||||
AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG
|
||||
AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT_0 19
|
||||
#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
|
||||
#define G0P0_RETENTION_REGS_CNT_1 4
|
||||
#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c};
|
||||
static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
|
||||
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p0_regs_map0[0], g0p0_regs_map0[1], \
|
||||
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
|
||||
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p0_regs_map1[0], g0p0_regs_map1[1], \
|
||||
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG
|
||||
AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG
|
||||
AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
|
||||
#define G0P1_RETENTION_REGS_CNT_0 3
|
||||
#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
|
||||
#define G0P1_RETENTION_REGS_CNT_1 16
|
||||
#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200)
|
||||
#define G0P1_RETENTION_REGS_CNT_2 4
|
||||
#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
|
||||
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p1_regs_map0[0], g0p1_regs_map0[1], \
|
||||
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
|
||||
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p1_regs_map1[0], g0p1_regs_map1[1], \
|
||||
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \
|
||||
G0P1_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p1_regs_map2[0], g0p1_regs_map2[1], \
|
||||
g0p1_regs_map2[2], g0p1_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair2) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG
|
||||
AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG
|
||||
AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 3
|
||||
#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
|
||||
#define G0P2_RETENTION_REGS_CNT_1 16
|
||||
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300)
|
||||
#define G0P2_RETENTION_REGS_CNT_2 4
|
||||
#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x0, 0x0, 0x0};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \
|
||||
G0P2_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p2_regs_map2[0], g0p2_regs_map2[1], \
|
||||
g0p2_regs_map2[2], g0p2_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair3) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG
|
||||
AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG
|
||||
AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG
|
||||
AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG
|
||||
AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG
|
||||
AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P3_RETENTION_REGS_CNT_0 3
|
||||
#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38)
|
||||
#define G0P3_RETENTION_REGS_CNT_1 16
|
||||
#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400)
|
||||
#define G0P3_RETENTION_REGS_CNT_2 4
|
||||
#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x0, 0x0, 0x0};
|
||||
static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p3_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \
|
||||
G0P3_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p3_regs_map0[0], g0p3_regs_map0[1], \
|
||||
g0p3_regs_map0[2], g0p3_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \
|
||||
G0P3_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p3_regs_map1[0], g0p3_regs_map1[1], \
|
||||
g0p3_regs_map1[2], g0p3_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \
|
||||
G0P3_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p3_regs_map2[0], g0p3_regs_map2[1], \
|
||||
g0p3_regs_map2[2], g0p3_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair4) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG
|
||||
AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG
|
||||
AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG
|
||||
AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG
|
||||
AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG
|
||||
AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P4_RETENTION_REGS_CNT_0 3
|
||||
#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48)
|
||||
#define G0P4_RETENTION_REGS_CNT_1 20
|
||||
#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500)
|
||||
static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x0, 0x0, 0x0};
|
||||
static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p4_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \
|
||||
G0P4_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p4_regs_map0[0], g0p4_regs_map0[1], \
|
||||
g0p4_regs_map0[2], g0p4_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \
|
||||
G0P4_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p4_regs_map1[0], g0p4_regs_map1[1], \
|
||||
g0p4_regs_map1[2], g0p4_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
const gdma_retention_desc_t gdma_retention_infos[1][5] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
gdma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2,
|
||||
},
|
||||
[3] = {
|
||||
gdma_g0p3_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p3_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH3,
|
||||
},
|
||||
[4] = {
|
||||
gdma_g0p4_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p4_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH4,
|
||||
},
|
||||
}
|
||||
};
|
||||
265
components/esp_driver_dma/esp32p4/gdma_retention.c
Normal file
265
components/esp_driver_dma/esp32p4/gdma_retention.c
Normal file
@@ -0,0 +1,265 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "gdma_priv.h"
|
||||
#include "soc/ahb_dma_reg.h"
|
||||
#include "soc/axi_dma_reg.h"
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair0) Registers Context
|
||||
Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
AHB_DMA_MISC_CONF_REG /
|
||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AHB_DMA_G0P0_RETENTION_REGS_CNT_0 13
|
||||
#define AHB_DMA_G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG
|
||||
#define AHB_DMA_G0P0_RETENTION_REGS_CNT_1 12
|
||||
#define AHB_DMA_G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG
|
||||
static const uint32_t ahb_dma_g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
|
||||
static const uint32_t ahb_dma_g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AHB_DMA_G0P0_RETENTION_MAP_BASE_0, AHB_DMA_G0P0_RETENTION_MAP_BASE_0, \
|
||||
AHB_DMA_G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
ahb_dma_g0p0_regs_map0[0], ahb_dma_g0p0_regs_map0[1], \
|
||||
ahb_dma_g0p0_regs_map0[2], ahb_dma_g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AHB_DMA_G0P0_RETENTION_MAP_BASE_1, AHB_DMA_G0P0_RETENTION_MAP_BASE_1, \
|
||||
AHB_DMA_G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
ahb_dma_g0p0_regs_map1[0], ahb_dma_g0p0_regs_map1[1], \
|
||||
ahb_dma_g0p0_regs_map1[2], ahb_dma_g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
AHB_DMA_MISC_CONF_REG /
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AHB_DMA_G0P1_RETENTION_REGS_CNT_0 13
|
||||
#define AHB_DMA_G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG
|
||||
#define AHB_DMA_G0P1_RETENTION_REGS_CNT_1 12
|
||||
#define AHB_DMA_G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG
|
||||
static const uint32_t ahb_dma_g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604};
|
||||
static const uint32_t ahb_dma_g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AHB_DMA_G0P1_RETENTION_MAP_BASE_0, AHB_DMA_G0P1_RETENTION_MAP_BASE_0, \
|
||||
AHB_DMA_G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
ahb_dma_g0p1_regs_map0[0], ahb_dma_g0p1_regs_map0[1], \
|
||||
ahb_dma_g0p1_regs_map0[2], ahb_dma_g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AHB_DMA_G0P1_RETENTION_MAP_BASE_1, AHB_DMA_G0P1_RETENTION_MAP_BASE_1, \
|
||||
AHB_DMA_G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
ahb_dma_g0p1_regs_map1[0], ahb_dma_g0p1_regs_map1[1], \
|
||||
ahb_dma_g0p1_regs_map1[2], ahb_dma_g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair2) Registers Context
|
||||
Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
AHB_DMA_MISC_CONF_REG /
|
||||
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_IN_PRI_CH2_REG
|
||||
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AHB_DMA_G0P2_RETENTION_REGS_CNT_0 6
|
||||
#define AHB_DMA_G0P2_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH2_REG
|
||||
#define AHB_DMA_G0P2_RETENTION_REGS_CNT_1 19
|
||||
#define AHB_DMA_G0P2_RETENTION_MAP_BASE_1 AHB_DMA_IN_PRI_CH2_REG
|
||||
static const uint32_t ahb_dma_g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
|
||||
static const uint32_t ahb_dma_g0p2_regs_map1[4] = {0x3026003, 0x0, 0x30, 0xfe4c};
|
||||
static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AHB_DMA_G0P2_RETENTION_MAP_BASE_0, AHB_DMA_G0P2_RETENTION_MAP_BASE_0, \
|
||||
AHB_DMA_G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
ahb_dma_g0p2_regs_map0[0], ahb_dma_g0p2_regs_map0[1], \
|
||||
ahb_dma_g0p2_regs_map0[2], ahb_dma_g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AHB_DMA_G0P2_RETENTION_MAP_BASE_1, AHB_DMA_G0P2_RETENTION_MAP_BASE_1, \
|
||||
AHB_DMA_G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
ahb_dma_g0p2_regs_map1[0], ahb_dma_g0p2_regs_map1[1], \
|
||||
ahb_dma_g0p2_regs_map1[2], ahb_dma_g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair0) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG
|
||||
AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG
|
||||
AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG
|
||||
#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \
|
||||
axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \
|
||||
axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair1) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG
|
||||
AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG
|
||||
AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG
|
||||
#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \
|
||||
axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \
|
||||
axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair2) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG
|
||||
AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG
|
||||
AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG
|
||||
#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \
|
||||
axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \
|
||||
axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_retention_desc_t gdma_retention_infos[2][3] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
ahb_dma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
ahb_dma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
ahb_dma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH2,
|
||||
},
|
||||
},
|
||||
[1] = {
|
||||
[0] = {
|
||||
axi_dma_g1p0_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
axi_dma_g1p1_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
axi_dma_g1p2_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH2,
|
||||
},
|
||||
}
|
||||
};
|
||||
396
components/esp_driver_dma/esp32s31/gdma_retention.c
Normal file
396
components/esp_driver_dma/esp32s31/gdma_retention.c
Normal file
@@ -0,0 +1,396 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "gdma_priv.h"
|
||||
#include "soc/ahb_dma_reg.h"
|
||||
#include "soc/axi_dma_reg.h"
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair0) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG
|
||||
AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG
|
||||
AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT_0 19
|
||||
#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
|
||||
#define G0P0_RETENTION_REGS_CNT_1 4
|
||||
#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c};
|
||||
static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
|
||||
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p0_regs_map0[0], g0p0_regs_map0[1], \
|
||||
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
|
||||
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p0_regs_map1[0], g0p0_regs_map1[1], \
|
||||
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG
|
||||
AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG
|
||||
AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
|
||||
#define G0P1_RETENTION_REGS_CNT_0 3
|
||||
#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
|
||||
#define G0P1_RETENTION_REGS_CNT_1 16
|
||||
#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200)
|
||||
#define G0P1_RETENTION_REGS_CNT_2 4
|
||||
#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
|
||||
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p1_regs_map0[0], g0p1_regs_map0[1], \
|
||||
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
|
||||
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p1_regs_map1[0], g0p1_regs_map1[1], \
|
||||
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \
|
||||
G0P1_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p1_regs_map2[0], g0p1_regs_map2[1], \
|
||||
g0p1_regs_map2[2], g0p1_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair2) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG
|
||||
AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG
|
||||
AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 3
|
||||
#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
|
||||
#define G0P2_RETENTION_REGS_CNT_1 16
|
||||
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300)
|
||||
#define G0P2_RETENTION_REGS_CNT_2 4
|
||||
#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x0, 0x0, 0x0};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \
|
||||
G0P2_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p2_regs_map2[0], g0p2_regs_map2[1], \
|
||||
g0p2_regs_map2[2], g0p2_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair3) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG
|
||||
AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG
|
||||
AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG
|
||||
AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG
|
||||
AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG
|
||||
AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P3_RETENTION_REGS_CNT_0 3
|
||||
#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38)
|
||||
#define G0P3_RETENTION_REGS_CNT_1 16
|
||||
#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400)
|
||||
#define G0P3_RETENTION_REGS_CNT_2 4
|
||||
#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x0, 0x0, 0x0};
|
||||
static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p3_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \
|
||||
G0P3_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p3_regs_map0[0], g0p3_regs_map0[1], \
|
||||
g0p3_regs_map0[2], g0p3_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \
|
||||
G0P3_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p3_regs_map1[0], g0p3_regs_map1[1], \
|
||||
g0p3_regs_map1[2], g0p3_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \
|
||||
G0P3_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p3_regs_map2[0], g0p3_regs_map2[1], \
|
||||
g0p3_regs_map2[2], g0p3_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair4) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG
|
||||
AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG
|
||||
AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG
|
||||
AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG
|
||||
AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG
|
||||
AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P4_RETENTION_REGS_CNT_0 3
|
||||
#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48)
|
||||
#define G0P4_RETENTION_REGS_CNT_1 20
|
||||
#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500)
|
||||
static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x0, 0x0, 0x0};
|
||||
static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p4_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \
|
||||
G0P4_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p4_regs_map0[0], g0p4_regs_map0[1], \
|
||||
g0p4_regs_map0[2], g0p4_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \
|
||||
G0P4_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p4_regs_map1[0], g0p4_regs_map1[1], \
|
||||
g0p4_regs_map1[2], g0p4_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair0) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG
|
||||
AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG
|
||||
AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
*/
|
||||
#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG
|
||||
#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \
|
||||
axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \
|
||||
axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair1) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG
|
||||
AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG
|
||||
AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
*/
|
||||
#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG
|
||||
#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \
|
||||
axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \
|
||||
axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair2) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG
|
||||
AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG
|
||||
AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
*/
|
||||
#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG
|
||||
#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \
|
||||
axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \
|
||||
axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_retention_desc_t gdma_retention_infos[3][5] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
ahb_dma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
ahb_dma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
ahb_dma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH2,
|
||||
},
|
||||
[3] = {
|
||||
ahb_dma_g0p3_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p3_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH3,
|
||||
},
|
||||
[4] = {
|
||||
ahb_dma_g0p4_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p4_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH4,
|
||||
},
|
||||
},
|
||||
[1] = {
|
||||
[0] = {
|
||||
axi_dma_g1p0_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
axi_dma_g1p1_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
axi_dma_g1p2_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH2,
|
||||
},
|
||||
}
|
||||
// LP_AHB_DMA (Group2) has no retention configuration because LP_AHB_DMA won't be powered off during light sleep
|
||||
};
|
||||
@@ -38,6 +38,16 @@
|
||||
#include "esp_private/sleep_retention.h"
|
||||
#include "esp_efuse.h"
|
||||
|
||||
#if CI_TEST_SW_RETENTION
|
||||
#define GDMA_RETENTION_ENTRY REGDMA_SW_TRIGGER_ENTRY
|
||||
#else
|
||||
#if SOC_PHY_SUPPORTED
|
||||
#define GDMA_RETENTION_ENTRY (ENTRY(0) | ENTRY(2))
|
||||
#else
|
||||
#define GDMA_RETENTION_ENTRY (ENTRY(0))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if CONFIG_GDMA_OBJ_DRAM_SAFE
|
||||
#define GDMA_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
|
||||
#else
|
||||
@@ -100,9 +110,20 @@ struct gdma_rx_channel_t {
|
||||
gdma_rx_event_callbacks_t cbs; // RX event callbacks
|
||||
};
|
||||
|
||||
#if SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED
|
||||
typedef struct {
|
||||
const regdma_entries_config_t *link_list;
|
||||
uint32_t link_num;
|
||||
const periph_retention_module_t module_id;
|
||||
} gdma_retention_desc_t;
|
||||
|
||||
extern const gdma_retention_desc_t gdma_retention_infos[GDMA_LL_GET(INST_NUM)][GDMA_LL_GET(PAIRS_PER_INST)];
|
||||
|
||||
void gdma_acquire_sleep_retention(gdma_pair_t* pair);
|
||||
void gdma_release_sleep_retention(gdma_pair_t* pair);
|
||||
|
||||
#endif // SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -19,9 +19,9 @@ static esp_err_t sleep_gdma_channel_retention_init(void *arg)
|
||||
int group_id = pair->group->group_id;
|
||||
int pair_id = pair->pair_id;
|
||||
|
||||
sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id;
|
||||
esp_err_t err = sleep_retention_entries_create(gdma_chx_regs_retention[group_id][pair_id].link_list,
|
||||
gdma_chx_regs_retention[group_id][pair_id].link_num,
|
||||
sleep_retention_module_t module = gdma_retention_infos[group_id][pair_id].module_id;
|
||||
esp_err_t err = sleep_retention_entries_create(gdma_retention_infos[group_id][pair_id].link_list,
|
||||
gdma_retention_infos[group_id][pair_id].link_num,
|
||||
REGDMA_LINK_PRI_GDMA, module);
|
||||
if (err == ESP_OK) {
|
||||
ESP_LOGD(TAG, "retention link created for pair (%d, %d)", group_id, pair_id);
|
||||
@@ -39,7 +39,7 @@ void gdma_acquire_sleep_retention(gdma_pair_t* pair)
|
||||
.cbs = { .create = { .handle = sleep_gdma_channel_retention_init, .arg = pair } },
|
||||
.depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_SYSTEM)
|
||||
};
|
||||
sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id;
|
||||
sleep_retention_module_t module = gdma_retention_infos[group_id][pair_id].module_id;
|
||||
|
||||
_lock_acquire(&gdma_sleep_retention_lock);
|
||||
// First time acquiring this pair, initialize the module
|
||||
@@ -63,7 +63,7 @@ void gdma_release_sleep_retention(gdma_pair_t* pair)
|
||||
{
|
||||
int group_id = pair->group->group_id;
|
||||
int pair_id = pair->pair_id;
|
||||
sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id;
|
||||
sleep_retention_module_t module = gdma_retention_infos[group_id][pair_id].module_id;
|
||||
|
||||
_lock_acquire(&gdma_sleep_retention_lock);
|
||||
pair_ref_counts[group_id][pair_id]--;
|
||||
@@ -26,6 +26,6 @@ idf_component_register(SRCS ${srcs}
|
||||
PRIV_REQUIRES unity esp_mm esp_driver_gpio esp_psram esp_driver_dma efuse
|
||||
WHOLE_ARCHIVE)
|
||||
|
||||
idf_component_get_property(lib_name esp_hal_dma COMPONENT_LIB)
|
||||
idf_component_get_property(lib_name esp_driver_dma COMPONENT_LIB)
|
||||
# Test GDMA retention correctness with software retention feature
|
||||
target_compile_definitions(${lib_name} PRIVATE "CI_TEST_SW_RETENTION=1")
|
||||
|
||||
@@ -30,139 +30,3 @@ const gdma_signal_conn_t gdma_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair0) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
|
||||
|
||||
AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG
|
||||
AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
AHB_DMA_MODULE_CLK_EN_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT_0 13
|
||||
#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
|
||||
#define G0P0_RETENTION_REGS_CNT_1 11
|
||||
#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x2dc)
|
||||
static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
|
||||
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0x0c900000, 0x601, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
|
||||
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p0_regs_map0[0], g0p0_regs_map0[1], \
|
||||
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
|
||||
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p0_regs_map1[0], g0p0_regs_map1[1], \
|
||||
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
|
||||
|
||||
AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG
|
||||
AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
AHB_DMA_MODULE_CLK_EN_REG
|
||||
*/
|
||||
#define G0P1_RETENTION_REGS_CNT_0 13
|
||||
#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
|
||||
#define G0P1_RETENTION_REGS_CNT_1 11
|
||||
#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x304)
|
||||
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
|
||||
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x434800, 0x18, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
|
||||
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p1_regs_map0[0], g0p1_regs_map0[1], \
|
||||
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
|
||||
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p1_regs_map1[0], g0p1_regs_map1[1], \
|
||||
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair2) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
|
||||
AHB_DMA_IN_PERI_SEL_CH2_REG
|
||||
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_PRI_CH2_REG
|
||||
|
||||
AHB_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH2_REG
|
||||
AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
AHB_DMA_MODULE_CLK_EN_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 8
|
||||
#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
|
||||
#define G0P2_RETENTION_REGS_CNT_1 16
|
||||
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x250)
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x604c0000};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x1813, 0x1800000, 0x72600000, 0x3008};
|
||||
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
gdma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
@@ -30,94 +30,3 @@ const gdma_signal_conn_t gdma_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair0) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
|
||||
GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
|
||||
GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT 13
|
||||
#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG
|
||||
static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
|
||||
G0P0_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p0_regs_map[0], g0p0_regs_map[1], \
|
||||
g0p0_regs_map[2], g0p0_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair1) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
|
||||
GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
|
||||
GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
|
||||
*/
|
||||
#define G0P1_RETENTION_REGS_CNT 13
|
||||
#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG
|
||||
static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
|
||||
G0P1_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p1_regs_map[0], g0p1_regs_map[1], \
|
||||
g0p1_regs_map[2], g0p1_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair2) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
|
||||
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
|
||||
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 6
|
||||
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
|
||||
#define G0P2_RETENTION_REGS_CNT_1 7
|
||||
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
gdma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
@@ -25,94 +25,3 @@ const gdma_signal_conn_t gdma_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair0) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
|
||||
|
||||
AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG
|
||||
AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
|
||||
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT_0 13
|
||||
#define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG
|
||||
#define G0P0_RETENTION_REGS_CNT_1 12
|
||||
#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG
|
||||
static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
|
||||
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
|
||||
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p0_regs_map0[0], g0p0_regs_map0[1], \
|
||||
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
|
||||
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p0_regs_map1[0], g0p0_regs_map1[1], \
|
||||
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
|
||||
|
||||
AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG
|
||||
AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
|
||||
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
*/
|
||||
#define G0P1_RETENTION_REGS_CNT_0 13
|
||||
#define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG
|
||||
#define G0P1_RETENTION_REGS_CNT_1 12
|
||||
#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG
|
||||
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
|
||||
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
|
||||
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p1_regs_map0[0], g0p1_regs_map0[1], \
|
||||
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
|
||||
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p1_regs_map1[0], g0p1_regs_map1[1], \
|
||||
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][2] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
@@ -30,94 +30,3 @@ const gdma_signal_conn_t gdma_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair0) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
|
||||
GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
|
||||
GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT 13
|
||||
#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG
|
||||
static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
|
||||
G0P0_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p0_regs_map[0], g0p0_regs_map[1], \
|
||||
g0p0_regs_map[2], g0p0_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair1) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
|
||||
GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
|
||||
GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
|
||||
*/
|
||||
#define G0P1_RETENTION_REGS_CNT 13
|
||||
#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG
|
||||
static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
|
||||
G0P1_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p1_regs_map[0], g0p1_regs_map[1], \
|
||||
g0p1_regs_map[2], g0p1_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair2) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
|
||||
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
|
||||
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 6
|
||||
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
|
||||
#define G0P2_RETENTION_REGS_CNT_1 7
|
||||
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
gdma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
@@ -30,96 +30,3 @@ const gdma_signal_conn_t gdma_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#if SOC_PAU_SUPPORTED
|
||||
/* GDMA Channel (Group0, Pair0) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
|
||||
GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
|
||||
GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT 13
|
||||
#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG
|
||||
static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
|
||||
G0P0_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p0_regs_map[0], g0p0_regs_map[1], \
|
||||
g0p0_regs_map[2], g0p0_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair1) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
|
||||
GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
|
||||
GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
|
||||
*/
|
||||
#define G0P1_RETENTION_REGS_CNT 13
|
||||
#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG
|
||||
static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
|
||||
G0P1_RETENTION_REGS_CNT, 0, 0, \
|
||||
g0p1_regs_map[0], g0p1_regs_map[1], \
|
||||
g0p1_regs_map[2], g0p1_regs_map[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* GDMA Channel (Group0, Pair2) Registers Context
|
||||
Include: GDMA_MISC_CONF_REG /
|
||||
GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
|
||||
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
|
||||
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 6
|
||||
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
|
||||
#define G0P2_RETENTION_REGS_CNT_1 7
|
||||
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
|
||||
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
gdma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2,
|
||||
}
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -40,272 +40,3 @@ const gdma_signal_conn_t gdma_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#if SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION
|
||||
/* AHB_DMA Channel (Group0, Pair0) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG
|
||||
AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG
|
||||
AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT_0 19
|
||||
#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
|
||||
#define G0P0_RETENTION_REGS_CNT_1 4
|
||||
#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c};
|
||||
static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
|
||||
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p0_regs_map0[0], g0p0_regs_map0[1], \
|
||||
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
|
||||
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p0_regs_map1[0], g0p0_regs_map1[1], \
|
||||
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG
|
||||
AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG
|
||||
AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
|
||||
#define G0P1_RETENTION_REGS_CNT_0 3
|
||||
#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
|
||||
#define G0P1_RETENTION_REGS_CNT_1 16
|
||||
#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200)
|
||||
#define G0P1_RETENTION_REGS_CNT_2 4
|
||||
#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
|
||||
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p1_regs_map0[0], g0p1_regs_map0[1], \
|
||||
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
|
||||
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p1_regs_map1[0], g0p1_regs_map1[1], \
|
||||
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \
|
||||
G0P1_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p1_regs_map2[0], g0p1_regs_map2[1], \
|
||||
g0p1_regs_map2[2], g0p1_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair2) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG
|
||||
AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG
|
||||
AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 3
|
||||
#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
|
||||
#define G0P2_RETENTION_REGS_CNT_1 16
|
||||
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300)
|
||||
#define G0P2_RETENTION_REGS_CNT_2 4
|
||||
#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \
|
||||
G0P2_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p2_regs_map2[0], g0p2_regs_map2[1], \
|
||||
g0p2_regs_map2[2], g0p2_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair3) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG
|
||||
AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG
|
||||
AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG
|
||||
AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG
|
||||
AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG
|
||||
AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P3_RETENTION_REGS_CNT_0 3
|
||||
#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38)
|
||||
#define G0P3_RETENTION_REGS_CNT_1 16
|
||||
#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400)
|
||||
#define G0P3_RETENTION_REGS_CNT_2 4
|
||||
#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p3_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \
|
||||
G0P3_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p3_regs_map0[0], g0p3_regs_map0[1], \
|
||||
g0p3_regs_map0[2], g0p3_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \
|
||||
G0P3_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p3_regs_map1[0], g0p3_regs_map1[1], \
|
||||
g0p3_regs_map1[2], g0p3_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \
|
||||
G0P3_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p3_regs_map2[0], g0p3_regs_map2[1], \
|
||||
g0p3_regs_map2[2], g0p3_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair4) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG
|
||||
AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG
|
||||
AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG
|
||||
AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG
|
||||
AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG
|
||||
AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P4_RETENTION_REGS_CNT_0 3
|
||||
#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48)
|
||||
#define G0P4_RETENTION_REGS_CNT_1 20
|
||||
#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500)
|
||||
static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0};
|
||||
static const regdma_entries_config_t gdma_g0p4_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \
|
||||
G0P4_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p4_regs_map0[0], g0p4_regs_map0[1], \
|
||||
g0p4_regs_map0[2], g0p4_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \
|
||||
G0P4_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p4_regs_map1[0], g0p4_regs_map1[1], \
|
||||
g0p4_regs_map1[2], g0p4_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][5] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
gdma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
gdma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
gdma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2,
|
||||
},
|
||||
[3] = {
|
||||
gdma_g0p3_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p3_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH3,
|
||||
},
|
||||
[4] = {
|
||||
gdma_g0p4_regs_retention,
|
||||
ARRAY_SIZE(gdma_g0p4_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH4,
|
||||
},
|
||||
}
|
||||
};
|
||||
#endif // SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION
|
||||
|
||||
@@ -50,259 +50,3 @@ const gdma_signal_conn_t gdma_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair0) Registers Context
|
||||
Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
AHB_DMA_MISC_CONF_REG /
|
||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AHB_DMA_G0P0_RETENTION_REGS_CNT_0 13
|
||||
#define AHB_DMA_G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG
|
||||
#define AHB_DMA_G0P0_RETENTION_REGS_CNT_1 12
|
||||
#define AHB_DMA_G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG
|
||||
static const uint32_t ahb_dma_g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
|
||||
static const uint32_t ahb_dma_g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AHB_DMA_G0P0_RETENTION_MAP_BASE_0, AHB_DMA_G0P0_RETENTION_MAP_BASE_0, \
|
||||
AHB_DMA_G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
ahb_dma_g0p0_regs_map0[0], ahb_dma_g0p0_regs_map0[1], \
|
||||
ahb_dma_g0p0_regs_map0[2], ahb_dma_g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AHB_DMA_G0P0_RETENTION_MAP_BASE_1, AHB_DMA_G0P0_RETENTION_MAP_BASE_1, \
|
||||
AHB_DMA_G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
ahb_dma_g0p0_regs_map1[0], ahb_dma_g0p0_regs_map1[1], \
|
||||
ahb_dma_g0p0_regs_map1[2], ahb_dma_g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
AHB_DMA_MISC_CONF_REG /
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AHB_DMA_G0P1_RETENTION_REGS_CNT_0 13
|
||||
#define AHB_DMA_G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG
|
||||
#define AHB_DMA_G0P1_RETENTION_REGS_CNT_1 12
|
||||
#define AHB_DMA_G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG
|
||||
static const uint32_t ahb_dma_g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604};
|
||||
static const uint32_t ahb_dma_g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AHB_DMA_G0P1_RETENTION_MAP_BASE_0, AHB_DMA_G0P1_RETENTION_MAP_BASE_0, \
|
||||
AHB_DMA_G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
ahb_dma_g0p1_regs_map0[0], ahb_dma_g0p1_regs_map0[1], \
|
||||
ahb_dma_g0p1_regs_map0[2], ahb_dma_g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AHB_DMA_G0P1_RETENTION_MAP_BASE_1, AHB_DMA_G0P1_RETENTION_MAP_BASE_1, \
|
||||
AHB_DMA_G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
ahb_dma_g0p1_regs_map1[0], ahb_dma_g0p1_regs_map1[1], \
|
||||
ahb_dma_g0p1_regs_map1[2], ahb_dma_g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair2) Registers Context
|
||||
Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
|
||||
AHB_DMA_MISC_CONF_REG /
|
||||
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_IN_PRI_CH2_REG
|
||||
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AHB_DMA_G0P2_RETENTION_REGS_CNT_0 6
|
||||
#define AHB_DMA_G0P2_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH2_REG
|
||||
#define AHB_DMA_G0P2_RETENTION_REGS_CNT_1 19
|
||||
#define AHB_DMA_G0P2_RETENTION_MAP_BASE_1 AHB_DMA_IN_PRI_CH2_REG
|
||||
static const uint32_t ahb_dma_g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
|
||||
static const uint32_t ahb_dma_g0p2_regs_map1[4] = {0x3026003, 0x0, 0x30, 0xfe4c};
|
||||
static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AHB_DMA_G0P2_RETENTION_MAP_BASE_0, AHB_DMA_G0P2_RETENTION_MAP_BASE_0, \
|
||||
AHB_DMA_G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
ahb_dma_g0p2_regs_map0[0], ahb_dma_g0p2_regs_map0[1], \
|
||||
ahb_dma_g0p2_regs_map0[2], ahb_dma_g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AHB_DMA_G0P2_RETENTION_MAP_BASE_1, AHB_DMA_G0P2_RETENTION_MAP_BASE_1, \
|
||||
AHB_DMA_G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
ahb_dma_g0p2_regs_map1[0], ahb_dma_g0p2_regs_map1[1], \
|
||||
ahb_dma_g0p2_regs_map1[2], ahb_dma_g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair0) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG
|
||||
AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG
|
||||
AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG
|
||||
#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \
|
||||
axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \
|
||||
axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair1) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG
|
||||
AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG
|
||||
AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG
|
||||
#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \
|
||||
axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \
|
||||
axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair2) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG
|
||||
AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG
|
||||
AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
|
||||
Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore.
|
||||
*/
|
||||
#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG
|
||||
#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \
|
||||
axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \
|
||||
axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[2][3] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
ahb_dma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
ahb_dma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
ahb_dma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH2,
|
||||
},
|
||||
},
|
||||
[1] = {
|
||||
[0] = {
|
||||
axi_dma_g1p0_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
axi_dma_g1p1_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
axi_dma_g1p2_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH2,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
@@ -72,391 +72,3 @@ const gdma_signal_conn_t gdma_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#if SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION
|
||||
/* AHB_DMA Channel (Group0, Pair0) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG
|
||||
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG
|
||||
AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG
|
||||
AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
|
||||
AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P0_RETENTION_REGS_CNT_0 19
|
||||
#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
|
||||
#define G0P0_RETENTION_REGS_CNT_1 4
|
||||
#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c};
|
||||
static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
|
||||
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p0_regs_map0[0], g0p0_regs_map0[1], \
|
||||
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
|
||||
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p0_regs_map1[0], g0p0_regs_map1[1], \
|
||||
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair1) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG
|
||||
AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG
|
||||
AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
|
||||
AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
|
||||
#define G0P1_RETENTION_REGS_CNT_0 3
|
||||
#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
|
||||
#define G0P1_RETENTION_REGS_CNT_1 16
|
||||
#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200)
|
||||
#define G0P1_RETENTION_REGS_CNT_2 4
|
||||
#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
|
||||
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p1_regs_map0[0], g0p1_regs_map0[1], \
|
||||
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
|
||||
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p1_regs_map1[0], g0p1_regs_map1[1], \
|
||||
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \
|
||||
G0P1_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p1_regs_map2[0], g0p1_regs_map2[1], \
|
||||
g0p1_regs_map2[2], g0p1_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair2) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG
|
||||
AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG
|
||||
AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
|
||||
AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P2_RETENTION_REGS_CNT_0 3
|
||||
#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
|
||||
#define G0P2_RETENTION_REGS_CNT_1 16
|
||||
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300)
|
||||
#define G0P2_RETENTION_REGS_CNT_2 4
|
||||
#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
|
||||
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p2_regs_map0[0], g0p2_regs_map0[1], \
|
||||
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
|
||||
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p2_regs_map1[0], g0p2_regs_map1[1], \
|
||||
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \
|
||||
G0P2_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p2_regs_map2[0], g0p2_regs_map2[1], \
|
||||
g0p2_regs_map2[2], g0p2_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair3) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG
|
||||
AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG
|
||||
AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG
|
||||
AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG
|
||||
AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG
|
||||
AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG
|
||||
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P3_RETENTION_REGS_CNT_0 3
|
||||
#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38)
|
||||
#define G0P3_RETENTION_REGS_CNT_1 16
|
||||
#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400)
|
||||
#define G0P3_RETENTION_REGS_CNT_2 4
|
||||
#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
|
||||
static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
|
||||
static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p3_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \
|
||||
G0P3_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p3_regs_map0[0], g0p3_regs_map0[1], \
|
||||
g0p3_regs_map0[2], g0p3_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \
|
||||
G0P3_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p3_regs_map1[0], g0p3_regs_map1[1], \
|
||||
g0p3_regs_map1[2], g0p3_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \
|
||||
G0P3_RETENTION_REGS_CNT_2, 0, 0, \
|
||||
g0p3_regs_map2[0], g0p3_regs_map2[1], \
|
||||
g0p3_regs_map2[2], g0p3_regs_map2[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AHB_DMA Channel (Group0, Pair4) Registers Context
|
||||
Include: AHB_DMA_MISC_CONF_REG
|
||||
AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG
|
||||
|
||||
AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG
|
||||
AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG
|
||||
AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG
|
||||
AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG
|
||||
AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG
|
||||
AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG
|
||||
AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG
|
||||
AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG
|
||||
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
|
||||
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
|
||||
*/
|
||||
#define G0P4_RETENTION_REGS_CNT_0 3
|
||||
#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48)
|
||||
#define G0P4_RETENTION_REGS_CNT_1 20
|
||||
#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500)
|
||||
static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x8, 0x0, 0x0};
|
||||
static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0};
|
||||
static const regdma_entries_config_t ahb_dma_g0p4_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \
|
||||
G0P4_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
g0p4_regs_map0[0], g0p4_regs_map0[1], \
|
||||
g0p4_regs_map0[2], g0p4_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
|
||||
G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \
|
||||
G0P4_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
g0p4_regs_map1[0], g0p4_regs_map1[1], \
|
||||
g0p4_regs_map1[2], g0p4_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
}, \
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair0) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG
|
||||
AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG
|
||||
AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
*/
|
||||
#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG
|
||||
#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \
|
||||
axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \
|
||||
axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair1) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG
|
||||
AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG
|
||||
AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
*/
|
||||
#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG
|
||||
#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \
|
||||
axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \
|
||||
axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
/* AXI_DMA Channel (Group1, Pair2) Registers Context
|
||||
Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG
|
||||
AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG
|
||||
AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG
|
||||
AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG
|
||||
AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG
|
||||
AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG
|
||||
AXI_DMA_MISC_CONF_REG
|
||||
*/
|
||||
#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14
|
||||
#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG
|
||||
#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8
|
||||
#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG
|
||||
static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0};
|
||||
static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = {
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
|
||||
AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \
|
||||
AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \
|
||||
axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \
|
||||
axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
|
||||
AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \
|
||||
AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \
|
||||
axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \
|
||||
axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \
|
||||
.owner = GDMA_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[2][5] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
ahb_dma_g0p0_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
ahb_dma_g0p1_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
ahb_dma_g0p2_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH2,
|
||||
},
|
||||
[3] = {
|
||||
ahb_dma_g0p3_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p3_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH3,
|
||||
},
|
||||
[4] = {
|
||||
ahb_dma_g0p4_regs_retention,
|
||||
ARRAY_SIZE(ahb_dma_g0p4_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AHB_DMA_CH4,
|
||||
},
|
||||
},
|
||||
[1] = {
|
||||
[0] = {
|
||||
axi_dma_g1p0_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p0_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH0,
|
||||
},
|
||||
[1] = {
|
||||
axi_dma_g1p1_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p1_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH1,
|
||||
},
|
||||
[2] = {
|
||||
axi_dma_g1p2_regs_retention,
|
||||
ARRAY_SIZE(axi_dma_g1p2_regs_retention),
|
||||
SLEEP_RETENTION_MODULE_AXI_DMA_CH2,
|
||||
},
|
||||
}
|
||||
};
|
||||
#endif // SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -8,23 +8,9 @@
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "soc/regdma.h"
|
||||
#if SOC_HAS(GDMA)
|
||||
#include "hal/gdma_ll.h"
|
||||
#endif
|
||||
#if SOC_HAS(PAU)
|
||||
#include "soc/retention_periph_defs.h"
|
||||
#endif
|
||||
|
||||
#if CI_TEST_SW_RETENTION
|
||||
#define GDMA_RETENTION_ENTRY REGDMA_SW_TRIGGER_ENTRY
|
||||
#else
|
||||
#if SOC_PHY_SUPPORTED
|
||||
#define GDMA_RETENTION_ENTRY (ENTRY(0) | ENTRY(2))
|
||||
#else
|
||||
#define GDMA_RETENTION_ENTRY (ENTRY(0))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -46,16 +32,6 @@ typedef struct {
|
||||
|
||||
extern const gdma_signal_conn_t gdma_periph_signals;
|
||||
|
||||
#if SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_LIGHT_SLEEP_SUPPORTED
|
||||
typedef struct {
|
||||
const regdma_entries_config_t *link_list;
|
||||
uint32_t link_num;
|
||||
const periph_retention_module_t module_id;
|
||||
} gdma_chx_reg_ctx_link_t;
|
||||
|
||||
extern const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[GDMA_LL_GET(INST_NUM)][GDMA_LL_GET(PAIRS_PER_INST)];
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -41,6 +41,8 @@ bool peripheral_domain_pd_allowed(void)
|
||||
RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH0);
|
||||
RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH1);
|
||||
RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH2);
|
||||
RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH3);
|
||||
RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH4);
|
||||
|
||||
// ESP32H4 supports PAU and I2S sleep retention
|
||||
RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2S0);
|
||||
|
||||
Reference in New Issue
Block a user