From d318aeaafb4e18b2e9679b9f8963e982da699dfe Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 24 Apr 2026 15:35:35 +0800 Subject: [PATCH] feat(gdma): move gdma sleep retention info from esp_hal_dma to esp_driver_dma --- components/esp_driver_dma/CMakeLists.txt | 4 +- .../esp_driver_dma/esp32c5/gdma_retention.c | 144 +++++++ .../esp_driver_dma/esp32c6/gdma_retention.c | 99 +++++ .../esp_driver_dma/esp32c61/gdma_retention.c | 99 +++++ .../esp_driver_dma/esp32h2/gdma_retention.c | 99 +++++ .../esp_driver_dma/esp32h21/gdma_retention.c | 99 +++++ .../esp_driver_dma/esp32h4/gdma_retention.c | 275 ++++++++++++ .../esp_driver_dma/esp32p4/gdma_retention.c | 265 ++++++++++++ .../esp_driver_dma/esp32s31/gdma_retention.c | 396 ++++++++++++++++++ components/esp_driver_dma/src/gdma_priv.h | 21 + .../{gdma_sleep_retention.c => gdma_sleep.c} | 10 +- .../test_apps/dma/main/CMakeLists.txt | 2 +- components/esp_hal_dma/esp32c5/gdma_periph.c | 136 ------ components/esp_hal_dma/esp32c6/gdma_periph.c | 91 ---- components/esp_hal_dma/esp32c61/gdma_periph.c | 91 ---- components/esp_hal_dma/esp32h2/gdma_periph.c | 91 ---- components/esp_hal_dma/esp32h21/gdma_periph.c | 93 ---- components/esp_hal_dma/esp32h4/gdma_periph.c | 269 ------------ components/esp_hal_dma/esp32p4/gdma_periph.c | 256 ----------- components/esp_hal_dma/esp32s31/gdma_periph.c | 388 ----------------- .../esp_hal_dma/include/hal/gdma_periph.h | 26 +- .../port/esp32h4/peripheral_domain_pd.c | 2 + 22 files changed, 1509 insertions(+), 1447 deletions(-) create mode 100644 components/esp_driver_dma/esp32c5/gdma_retention.c create mode 100644 components/esp_driver_dma/esp32c6/gdma_retention.c create mode 100644 components/esp_driver_dma/esp32c61/gdma_retention.c create mode 100644 components/esp_driver_dma/esp32h2/gdma_retention.c create mode 100644 components/esp_driver_dma/esp32h21/gdma_retention.c create mode 100644 components/esp_driver_dma/esp32h4/gdma_retention.c create mode 100644 components/esp_driver_dma/esp32p4/gdma_retention.c create mode 100644 components/esp_driver_dma/esp32s31/gdma_retention.c rename components/esp_driver_dma/src/{gdma_sleep_retention.c => gdma_sleep.c} (85%) diff --git a/components/esp_driver_dma/CMakeLists.txt b/components/esp_driver_dma/CMakeLists.txt index a36fa937780..ec28f99c5c0 100644 --- a/components/esp_driver_dma/CMakeLists.txt +++ b/components/esp_driver_dma/CMakeLists.txt @@ -10,7 +10,8 @@ set(srcs "src/esp_dma_utils.c" "src/gdma_link.c") if(CONFIG_SOC_GDMA_SUPPORTED) list(APPEND srcs "src/gdma.c") if(CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION AND CONFIG_SOC_PAU_SUPPORTED) - list(APPEND srcs "src/gdma_sleep_retention.c") + list(APPEND srcs "src/gdma_sleep.c") + list(APPEND srcs "${target}/gdma_retention.c") endif() if(CONFIG_SOC_GDMA_SUPPORT_ETM) list(APPEND srcs "src/gdma_etm.c") @@ -40,6 +41,7 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} + PRIV_INCLUDE_DIRS "src" REQUIRES ${requires} PRIV_REQUIRES esp_mm efuse LDFRAGMENTS "linker.lf" diff --git a/components/esp_driver_dma/esp32c5/gdma_retention.c b/components/esp_driver_dma/esp32c5/gdma_retention.c new file mode 100644 index 00000000000..a9e7b16b37f --- /dev/null +++ b/components/esp_driver_dma/esp32c5/gdma_retention.c @@ -0,0 +1,144 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gdma_priv.h" +#include "soc/ahb_dma_reg.h" + +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG + + AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG + AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG + AHB_DMA_MODULE_CLK_EN_REG +*/ +#define G0P0_RETENTION_REGS_CNT_0 13 +#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) +#define G0P0_RETENTION_REGS_CNT_1 11 +#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x2dc) +static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; +static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0x0c900000, 0x601, 0x0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG + + AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG + AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG + AHB_DMA_MODULE_CLK_EN_REG +*/ +#define G0P1_RETENTION_REGS_CNT_0 13 +#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) +#define G0P1_RETENTION_REGS_CNT_1 11 +#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x304) +static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; +static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x434800, 0x18, 0x0}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AHB_DMA Channel (Group0, Pair2) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG + AHB_DMA_IN_PERI_SEL_CH2_REG + AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_PRI_CH2_REG + + AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG + AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH2_REG + AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG + AHB_DMA_MODULE_CLK_EN_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 8 +#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) +#define G0P2_RETENTION_REGS_CNT_1 16 +#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x250) +static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x604c0000}; +static const uint32_t g0p2_regs_map1[4] = {0x1813, 0x1800000, 0x72600000, 0x3008}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +const gdma_retention_desc_t gdma_retention_infos[1][3] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + } + } +}; diff --git a/components/esp_driver_dma/esp32c6/gdma_retention.c b/components/esp_driver_dma/esp32c6/gdma_retention.c new file mode 100644 index 00000000000..268b51522b4 --- /dev/null +++ b/components/esp_driver_dma/esp32c6/gdma_retention.c @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gdma_priv.h" +#include "soc/gdma_reg.h" + +/* GDMA Channel (Group0, Pair0) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG + GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG + GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG +*/ +#define G0P0_RETENTION_REGS_CNT 13 +#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG +static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ + G0P0_RETENTION_REGS_CNT, 0, 0, \ + g0p0_regs_map[0], g0p0_regs_map[1], \ + g0p0_regs_map[2], g0p0_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* GDMA Channel (Group0, Pair1) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG + GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG + GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG +*/ +#define G0P1_RETENTION_REGS_CNT 13 +#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG +static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ + G0P1_RETENTION_REGS_CNT, 0, 0, \ + g0p1_regs_map[0], g0p1_regs_map[1], \ + g0p1_regs_map[2], g0p1_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* GDMA Channel (Group0, Pair2) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG + GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG + GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 6 +#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG +#define G0P2_RETENTION_REGS_CNT_1 7 +#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG +static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; +static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +const gdma_retention_desc_t gdma_retention_infos[1][3] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + }, + } +}; diff --git a/components/esp_driver_dma/esp32c61/gdma_retention.c b/components/esp_driver_dma/esp32c61/gdma_retention.c new file mode 100644 index 00000000000..ca784c30055 --- /dev/null +++ b/components/esp_driver_dma/esp32c61/gdma_retention.c @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gdma_priv.h" +#include "soc/ahb_dma_reg.h" + +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG + + AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG + AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG + AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG +*/ +#define G0P0_RETENTION_REGS_CNT_0 13 +#define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG +#define G0P0_RETENTION_REGS_CNT_1 12 +#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG +static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; +static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG + + AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG + AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG + AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG +*/ +#define G0P1_RETENTION_REGS_CNT_0 13 +#define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG +#define G0P1_RETENTION_REGS_CNT_1 12 +#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG +static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; +static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +const gdma_retention_desc_t gdma_retention_infos[1][2] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + } +}; diff --git a/components/esp_driver_dma/esp32h2/gdma_retention.c b/components/esp_driver_dma/esp32h2/gdma_retention.c new file mode 100644 index 00000000000..77475a2b915 --- /dev/null +++ b/components/esp_driver_dma/esp32h2/gdma_retention.c @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gdma_priv.h" +#include "soc/gdma_reg.h" + +/* GDMA Channel (Group0, Pair0) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG + GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG + GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG +*/ +#define G0P0_RETENTION_REGS_CNT 13 +#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG +static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ + G0P0_RETENTION_REGS_CNT, 0, 0, \ + g0p0_regs_map[0], g0p0_regs_map[1], \ + g0p0_regs_map[2], g0p0_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* GDMA Channel (Group0, Pair1) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG + GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG + GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG +*/ +#define G0P1_RETENTION_REGS_CNT 13 +#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG +static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ + G0P1_RETENTION_REGS_CNT, 0, 0, \ + g0p1_regs_map[0], g0p1_regs_map[1], \ + g0p1_regs_map[2], g0p1_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* GDMA Channel (Group0, Pair2) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG + GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG + GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 6 +#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG +#define G0P2_RETENTION_REGS_CNT_1 7 +#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG +static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; +static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +const gdma_retention_desc_t gdma_retention_infos[1][3] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + } + } +}; diff --git a/components/esp_driver_dma/esp32h21/gdma_retention.c b/components/esp_driver_dma/esp32h21/gdma_retention.c new file mode 100644 index 00000000000..77475a2b915 --- /dev/null +++ b/components/esp_driver_dma/esp32h21/gdma_retention.c @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gdma_priv.h" +#include "soc/gdma_reg.h" + +/* GDMA Channel (Group0, Pair0) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG + GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG + GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG +*/ +#define G0P0_RETENTION_REGS_CNT 13 +#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG +static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ + G0P0_RETENTION_REGS_CNT, 0, 0, \ + g0p0_regs_map[0], g0p0_regs_map[1], \ + g0p0_regs_map[2], g0p0_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* GDMA Channel (Group0, Pair1) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG + GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG + GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG +*/ +#define G0P1_RETENTION_REGS_CNT 13 +#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG +static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ + G0P1_RETENTION_REGS_CNT, 0, 0, \ + g0p1_regs_map[0], g0p1_regs_map[1], \ + g0p1_regs_map[2], g0p1_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* GDMA Channel (Group0, Pair2) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG + GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG + GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 6 +#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG +#define G0P2_RETENTION_REGS_CNT_1 7 +#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG +static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; +static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +const gdma_retention_desc_t gdma_retention_infos[1][3] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + } + } +}; diff --git a/components/esp_driver_dma/esp32h4/gdma_retention.c b/components/esp_driver_dma/esp32h4/gdma_retention.c new file mode 100644 index 00000000000..79a265ea5ae --- /dev/null +++ b/components/esp_driver_dma/esp32h4/gdma_retention.c @@ -0,0 +1,275 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gdma_priv.h" +#include "soc/ahb_dma_reg.h" + +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG + AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG + AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG + AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG + AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P0_RETENTION_REGS_CNT_0 19 +#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) +#define G0P0_RETENTION_REGS_CNT_1 4 +#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c}; +static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG + + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG + AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG + AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG + AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG + AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ + +#define G0P1_RETENTION_REGS_CNT_0 3 +#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) +#define G0P1_RETENTION_REGS_CNT_1 16 +#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200) +#define G0P1_RETENTION_REGS_CNT_2 4 +#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0}; +static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \ + G0P1_RETENTION_REGS_CNT_2, 0, 0, \ + g0p1_regs_map2[0], g0p1_regs_map2[1], \ + g0p1_regs_map2[2], g0p1_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair2) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG + + AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG + AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG + AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG + AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG + AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG + AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 3 +#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) +#define G0P2_RETENTION_REGS_CNT_1 16 +#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300) +#define G0P2_RETENTION_REGS_CNT_2 4 +#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x0, 0x0, 0x0}; +static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \ + G0P2_RETENTION_REGS_CNT_2, 0, 0, \ + g0p2_regs_map2[0], g0p2_regs_map2[1], \ + g0p2_regs_map2[2], g0p2_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair3) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG + + AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG + AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG + AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG + AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG + AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG + AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P3_RETENTION_REGS_CNT_0 3 +#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38) +#define G0P3_RETENTION_REGS_CNT_1 16 +#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400) +#define G0P3_RETENTION_REGS_CNT_2 4 +#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x0, 0x0, 0x0}; +static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p3_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \ + G0P3_RETENTION_REGS_CNT_0, 0, 0, \ + g0p3_regs_map0[0], g0p3_regs_map0[1], \ + g0p3_regs_map0[2], g0p3_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \ + G0P3_RETENTION_REGS_CNT_1, 0, 0, \ + g0p3_regs_map1[0], g0p3_regs_map1[1], \ + g0p3_regs_map1[2], g0p3_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \ + G0P3_RETENTION_REGS_CNT_2, 0, 0, \ + g0p3_regs_map2[0], g0p3_regs_map2[1], \ + g0p3_regs_map2[2], g0p3_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair4) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG + + AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG + AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG + AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG + AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG + AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG + AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P4_RETENTION_REGS_CNT_0 3 +#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48) +#define G0P4_RETENTION_REGS_CNT_1 20 +#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500) +static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x0, 0x0, 0x0}; +static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0}; +static const regdma_entries_config_t gdma_g0p4_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \ + G0P4_RETENTION_REGS_CNT_0, 0, 0, \ + g0p4_regs_map0[0], g0p4_regs_map0[1], \ + g0p4_regs_map0[2], g0p4_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \ + G0P4_RETENTION_REGS_CNT_1, 0, 0, \ + g0p4_regs_map1[0], g0p4_regs_map1[1], \ + g0p4_regs_map1[2], g0p4_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +const gdma_retention_desc_t gdma_retention_infos[1][5] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + }, + [3] = { + gdma_g0p3_regs_retention, + ARRAY_SIZE(gdma_g0p3_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH3, + }, + [4] = { + gdma_g0p4_regs_retention, + ARRAY_SIZE(gdma_g0p4_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH4, + }, + } +}; diff --git a/components/esp_driver_dma/esp32p4/gdma_retention.c b/components/esp_driver_dma/esp32p4/gdma_retention.c new file mode 100644 index 00000000000..ed9586bc2c0 --- /dev/null +++ b/components/esp_driver_dma/esp32p4/gdma_retention.c @@ -0,0 +1,265 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gdma_priv.h" +#include "soc/ahb_dma_reg.h" +#include "soc/axi_dma_reg.h" + +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_MISC_CONF_REG / + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_IN_PRI_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AHB_DMA_G0P0_RETENTION_REGS_CNT_0 13 +#define AHB_DMA_G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG +#define AHB_DMA_G0P0_RETENTION_REGS_CNT_1 12 +#define AHB_DMA_G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG +static const uint32_t ahb_dma_g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; +static const uint32_t ahb_dma_g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P0_RETENTION_MAP_BASE_0, AHB_DMA_G0P0_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p0_regs_map0[0], ahb_dma_g0p0_regs_map0[1], \ + ahb_dma_g0p0_regs_map0[2], ahb_dma_g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P0_RETENTION_MAP_BASE_1, AHB_DMA_G0P0_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p0_regs_map1[0], ahb_dma_g0p0_regs_map1[1], \ + ahb_dma_g0p0_regs_map1[2], ahb_dma_g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_MISC_CONF_REG / + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_IN_PRI_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AHB_DMA_G0P1_RETENTION_REGS_CNT_0 13 +#define AHB_DMA_G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG +#define AHB_DMA_G0P1_RETENTION_REGS_CNT_1 12 +#define AHB_DMA_G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG +static const uint32_t ahb_dma_g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604}; +static const uint32_t ahb_dma_g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P1_RETENTION_MAP_BASE_0, AHB_DMA_G0P1_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p1_regs_map0[0], ahb_dma_g0p1_regs_map0[1], \ + ahb_dma_g0p1_regs_map0[2], ahb_dma_g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P1_RETENTION_MAP_BASE_1, AHB_DMA_G0P1_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p1_regs_map1[0], ahb_dma_g0p1_regs_map1[1], \ + ahb_dma_g0p1_regs_map1[2], ahb_dma_g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AHB_DMA Channel (Group0, Pair2) Registers Context + Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_MISC_CONF_REG / + AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_IN_PRI_CH2_REG + AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AHB_DMA_G0P2_RETENTION_REGS_CNT_0 6 +#define AHB_DMA_G0P2_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH2_REG +#define AHB_DMA_G0P2_RETENTION_REGS_CNT_1 19 +#define AHB_DMA_G0P2_RETENTION_MAP_BASE_1 AHB_DMA_IN_PRI_CH2_REG +static const uint32_t ahb_dma_g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; +static const uint32_t ahb_dma_g0p2_regs_map1[4] = {0x3026003, 0x0, 0x30, 0xfe4c}; +static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P2_RETENTION_MAP_BASE_0, AHB_DMA_G0P2_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p2_regs_map0[0], ahb_dma_g0p2_regs_map0[1], \ + ahb_dma_g0p2_regs_map0[2], ahb_dma_g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P2_RETENTION_MAP_BASE_1, AHB_DMA_G0P2_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p2_regs_map1[0], ahb_dma_g0p2_regs_map1[1], \ + ahb_dma_g0p2_regs_map1[2], ahb_dma_g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AXI_DMA Channel (Group1, Pair0) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG + AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG + AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG + AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG +#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \ + axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \ + axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AXI_DMA Channel (Group1, Pair1) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG + AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG + AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG + AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG +#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \ + axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \ + axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AXI_DMA Channel (Group1, Pair2) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG + AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG + AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG + AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG +#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \ + axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \ + axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +const gdma_retention_desc_t gdma_retention_infos[2][3] = { + [0] = { + [0] = { + ahb_dma_g0p0_regs_retention, + ARRAY_SIZE(ahb_dma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH0, + }, + [1] = { + ahb_dma_g0p1_regs_retention, + ARRAY_SIZE(ahb_dma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH1, + }, + [2] = { + ahb_dma_g0p2_regs_retention, + ARRAY_SIZE(ahb_dma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH2, + }, + }, + [1] = { + [0] = { + axi_dma_g1p0_regs_retention, + ARRAY_SIZE(axi_dma_g1p0_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH0, + }, + [1] = { + axi_dma_g1p1_regs_retention, + ARRAY_SIZE(axi_dma_g1p1_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH1, + }, + [2] = { + axi_dma_g1p2_regs_retention, + ARRAY_SIZE(axi_dma_g1p2_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH2, + }, + } +}; diff --git a/components/esp_driver_dma/esp32s31/gdma_retention.c b/components/esp_driver_dma/esp32s31/gdma_retention.c new file mode 100644 index 00000000000..86dc49c3358 --- /dev/null +++ b/components/esp_driver_dma/esp32s31/gdma_retention.c @@ -0,0 +1,396 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gdma_priv.h" +#include "soc/ahb_dma_reg.h" +#include "soc/axi_dma_reg.h" + +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG + AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG + AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG + AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG + AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P0_RETENTION_REGS_CNT_0 19 +#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) +#define G0P0_RETENTION_REGS_CNT_1 4 +#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c}; +static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG + + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG + AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG + AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG + AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG + AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ + +#define G0P1_RETENTION_REGS_CNT_0 3 +#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) +#define G0P1_RETENTION_REGS_CNT_1 16 +#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200) +#define G0P1_RETENTION_REGS_CNT_2 4 +#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0}; +static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \ + G0P1_RETENTION_REGS_CNT_2, 0, 0, \ + g0p1_regs_map2[0], g0p1_regs_map2[1], \ + g0p1_regs_map2[2], g0p1_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair2) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG + + AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG + AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG + AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG + AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG + AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG + AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 3 +#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) +#define G0P2_RETENTION_REGS_CNT_1 16 +#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300) +#define G0P2_RETENTION_REGS_CNT_2 4 +#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x0, 0x0, 0x0}; +static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \ + G0P2_RETENTION_REGS_CNT_2, 0, 0, \ + g0p2_regs_map2[0], g0p2_regs_map2[1], \ + g0p2_regs_map2[2], g0p2_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair3) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG + + AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG + AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG + AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG + AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG + AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG + AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG + + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P3_RETENTION_REGS_CNT_0 3 +#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38) +#define G0P3_RETENTION_REGS_CNT_1 16 +#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400) +#define G0P3_RETENTION_REGS_CNT_2 4 +#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) +static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x0, 0x0, 0x0}; +static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p3_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \ + G0P3_RETENTION_REGS_CNT_0, 0, 0, \ + g0p3_regs_map0[0], g0p3_regs_map0[1], \ + g0p3_regs_map0[2], g0p3_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \ + G0P3_RETENTION_REGS_CNT_1, 0, 0, \ + g0p3_regs_map1[0], g0p3_regs_map1[1], \ + g0p3_regs_map1[2], g0p3_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \ + G0P3_RETENTION_REGS_CNT_2, 0, 0, \ + g0p3_regs_map2[0], g0p3_regs_map2[1], \ + g0p3_regs_map2[2], g0p3_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AHB_DMA Channel (Group0, Pair4) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG + + AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG + AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG + AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG + AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG + AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG + AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG +*/ +#define G0P4_RETENTION_REGS_CNT_0 3 +#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48) +#define G0P4_RETENTION_REGS_CNT_1 20 +#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500) +static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x0, 0x0, 0x0}; +static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p4_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \ + G0P4_RETENTION_REGS_CNT_0, 0, 0, \ + g0p4_regs_map0[0], g0p4_regs_map0[1], \ + g0p4_regs_map0[2], g0p4_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \ + G0P4_RETENTION_REGS_CNT_1, 0, 0, \ + g0p4_regs_map1[0], g0p4_regs_map1[1], \ + g0p4_regs_map1[2], g0p4_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* AXI_DMA Channel (Group1, Pair0) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG + AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG + AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG + AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG +*/ +#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG +#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \ + axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \ + axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AXI_DMA Channel (Group1, Pair1) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG + AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG + AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG + AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG +*/ +#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG +#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \ + axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \ + axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* AXI_DMA Channel (Group1, Pair2) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG + AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG + AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG + AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG +*/ +#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG +#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \ + axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \ + axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +const gdma_retention_desc_t gdma_retention_infos[3][5] = { + [0] = { + [0] = { + ahb_dma_g0p0_regs_retention, + ARRAY_SIZE(ahb_dma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH0, + }, + [1] = { + ahb_dma_g0p1_regs_retention, + ARRAY_SIZE(ahb_dma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH1, + }, + [2] = { + ahb_dma_g0p2_regs_retention, + ARRAY_SIZE(ahb_dma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH2, + }, + [3] = { + ahb_dma_g0p3_regs_retention, + ARRAY_SIZE(ahb_dma_g0p3_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH3, + }, + [4] = { + ahb_dma_g0p4_regs_retention, + ARRAY_SIZE(ahb_dma_g0p4_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH4, + }, + }, + [1] = { + [0] = { + axi_dma_g1p0_regs_retention, + ARRAY_SIZE(axi_dma_g1p0_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH0, + }, + [1] = { + axi_dma_g1p1_regs_retention, + ARRAY_SIZE(axi_dma_g1p1_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH1, + }, + [2] = { + axi_dma_g1p2_regs_retention, + ARRAY_SIZE(axi_dma_g1p2_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH2, + }, + } + // LP_AHB_DMA (Group2) has no retention configuration because LP_AHB_DMA won't be powered off during light sleep +}; diff --git a/components/esp_driver_dma/src/gdma_priv.h b/components/esp_driver_dma/src/gdma_priv.h index a6a2a4bfcf7..6f268f5c811 100644 --- a/components/esp_driver_dma/src/gdma_priv.h +++ b/components/esp_driver_dma/src/gdma_priv.h @@ -38,6 +38,16 @@ #include "esp_private/sleep_retention.h" #include "esp_efuse.h" +#if CI_TEST_SW_RETENTION +#define GDMA_RETENTION_ENTRY REGDMA_SW_TRIGGER_ENTRY +#else +#if SOC_PHY_SUPPORTED +#define GDMA_RETENTION_ENTRY (ENTRY(0) | ENTRY(2)) +#else +#define GDMA_RETENTION_ENTRY (ENTRY(0)) +#endif +#endif + #if CONFIG_GDMA_OBJ_DRAM_SAFE #define GDMA_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #else @@ -100,9 +110,20 @@ struct gdma_rx_channel_t { gdma_rx_event_callbacks_t cbs; // RX event callbacks }; +#if SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED +typedef struct { + const regdma_entries_config_t *link_list; + uint32_t link_num; + const periph_retention_module_t module_id; +} gdma_retention_desc_t; + +extern const gdma_retention_desc_t gdma_retention_infos[GDMA_LL_GET(INST_NUM)][GDMA_LL_GET(PAIRS_PER_INST)]; + void gdma_acquire_sleep_retention(gdma_pair_t* pair); void gdma_release_sleep_retention(gdma_pair_t* pair); +#endif // SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_dma/src/gdma_sleep_retention.c b/components/esp_driver_dma/src/gdma_sleep.c similarity index 85% rename from components/esp_driver_dma/src/gdma_sleep_retention.c rename to components/esp_driver_dma/src/gdma_sleep.c index a5f27b365dd..35243416c02 100644 --- a/components/esp_driver_dma/src/gdma_sleep_retention.c +++ b/components/esp_driver_dma/src/gdma_sleep.c @@ -19,9 +19,9 @@ static esp_err_t sleep_gdma_channel_retention_init(void *arg) int group_id = pair->group->group_id; int pair_id = pair->pair_id; - sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id; - esp_err_t err = sleep_retention_entries_create(gdma_chx_regs_retention[group_id][pair_id].link_list, - gdma_chx_regs_retention[group_id][pair_id].link_num, + sleep_retention_module_t module = gdma_retention_infos[group_id][pair_id].module_id; + esp_err_t err = sleep_retention_entries_create(gdma_retention_infos[group_id][pair_id].link_list, + gdma_retention_infos[group_id][pair_id].link_num, REGDMA_LINK_PRI_GDMA, module); if (err == ESP_OK) { ESP_LOGD(TAG, "retention link created for pair (%d, %d)", group_id, pair_id); @@ -39,7 +39,7 @@ void gdma_acquire_sleep_retention(gdma_pair_t* pair) .cbs = { .create = { .handle = sleep_gdma_channel_retention_init, .arg = pair } }, .depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_SYSTEM) }; - sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id; + sleep_retention_module_t module = gdma_retention_infos[group_id][pair_id].module_id; _lock_acquire(&gdma_sleep_retention_lock); // First time acquiring this pair, initialize the module @@ -63,7 +63,7 @@ void gdma_release_sleep_retention(gdma_pair_t* pair) { int group_id = pair->group->group_id; int pair_id = pair->pair_id; - sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id; + sleep_retention_module_t module = gdma_retention_infos[group_id][pair_id].module_id; _lock_acquire(&gdma_sleep_retention_lock); pair_ref_counts[group_id][pair_id]--; diff --git a/components/esp_driver_dma/test_apps/dma/main/CMakeLists.txt b/components/esp_driver_dma/test_apps/dma/main/CMakeLists.txt index f3c9e24bd1a..abb60644b69 100644 --- a/components/esp_driver_dma/test_apps/dma/main/CMakeLists.txt +++ b/components/esp_driver_dma/test_apps/dma/main/CMakeLists.txt @@ -26,6 +26,6 @@ idf_component_register(SRCS ${srcs} PRIV_REQUIRES unity esp_mm esp_driver_gpio esp_psram esp_driver_dma efuse WHOLE_ARCHIVE) -idf_component_get_property(lib_name esp_hal_dma COMPONENT_LIB) +idf_component_get_property(lib_name esp_driver_dma COMPONENT_LIB) # Test GDMA retention correctness with software retention feature target_compile_definitions(${lib_name} PRIVATE "CI_TEST_SW_RETENTION=1") diff --git a/components/esp_hal_dma/esp32c5/gdma_periph.c b/components/esp_hal_dma/esp32c5/gdma_periph.c index 831387cebb5..34014155e2f 100644 --- a/components/esp_hal_dma/esp32c5/gdma_periph.c +++ b/components/esp_hal_dma/esp32c5/gdma_periph.c @@ -30,139 +30,3 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; - -/* AHB_DMA Channel (Group0, Pair0) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG - AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG - AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG - - AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG - AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG - AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG - AHB_DMA_MODULE_CLK_EN_REG -*/ -#define G0P0_RETENTION_REGS_CNT_0 13 -#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) -#define G0P0_RETENTION_REGS_CNT_1 11 -#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x2dc) -static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; -static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0x0c900000, 0x601, 0x0}; -static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ - G0P0_RETENTION_REGS_CNT_0, 0, 0, \ - g0p0_regs_map0[0], g0p0_regs_map0[1], \ - g0p0_regs_map0[2], g0p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ - G0P0_RETENTION_REGS_CNT_1, 0, 0, \ - g0p0_regs_map1[0], g0p0_regs_map1[1], \ - g0p0_regs_map1[2], g0p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AHB_DMA Channel (Group0, Pair1) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG - AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG - AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG - - AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG - AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG - AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG - AHB_DMA_MODULE_CLK_EN_REG -*/ -#define G0P1_RETENTION_REGS_CNT_0 13 -#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) -#define G0P1_RETENTION_REGS_CNT_1 11 -#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x304) -static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; -static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x434800, 0x18, 0x0}; -static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ - G0P1_RETENTION_REGS_CNT_0, 0, 0, \ - g0p1_regs_map0[0], g0p1_regs_map0[1], \ - g0p1_regs_map0[2], g0p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ - G0P1_RETENTION_REGS_CNT_1, 0, 0, \ - g0p1_regs_map1[0], g0p1_regs_map1[1], \ - g0p1_regs_map1[2], g0p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AHB_DMA Channel (Group0, Pair2) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG - AHB_DMA_IN_PERI_SEL_CH2_REG - AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_PRI_CH2_REG - - AHB_DMA_OUT_PERI_SEL_CH2_REG - AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG - AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG - AHB_DMA_RX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH2_REG - AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG - AHB_DMA_MODULE_CLK_EN_REG -*/ -#define G0P2_RETENTION_REGS_CNT_0 8 -#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) -#define G0P2_RETENTION_REGS_CNT_1 16 -#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x250) -static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x604c0000}; -static const uint32_t g0p2_regs_map1[4] = {0x1813, 0x1800000, 0x72600000, 0x3008}; -static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = { - [0] = { - [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, - [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, - [2] = { - gdma_g0p2_regs_retention, - ARRAY_SIZE(gdma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH2, - } - } -}; diff --git a/components/esp_hal_dma/esp32c6/gdma_periph.c b/components/esp_hal_dma/esp32c6/gdma_periph.c index 559ec806c4d..8bd210336f3 100644 --- a/components/esp_hal_dma/esp32c6/gdma_periph.c +++ b/components/esp_hal_dma/esp32c6/gdma_periph.c @@ -30,94 +30,3 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; - -/* GDMA Channel (Group0, Pair0) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG - GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG - GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG -*/ -#define G0P0_RETENTION_REGS_CNT 13 -#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG -static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; -static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ - G0P0_RETENTION_REGS_CNT, 0, 0, \ - g0p0_regs_map[0], g0p0_regs_map[1], \ - g0p0_regs_map[2], g0p0_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* GDMA Channel (Group0, Pair1) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG - GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG - GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG -*/ -#define G0P1_RETENTION_REGS_CNT 13 -#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG -static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; -static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ - G0P1_RETENTION_REGS_CNT, 0, 0, \ - g0p1_regs_map[0], g0p1_regs_map[1], \ - g0p1_regs_map[2], g0p1_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* GDMA Channel (Group0, Pair2) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG - GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG - GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG -*/ -#define G0P2_RETENTION_REGS_CNT_0 6 -#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG -#define G0P2_RETENTION_REGS_CNT_1 7 -#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG -static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; -static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; -static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = { - [0] = { - [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, - [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, - [2] = { - gdma_g0p2_regs_retention, - ARRAY_SIZE(gdma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH2, - }, - } -}; diff --git a/components/esp_hal_dma/esp32c61/gdma_periph.c b/components/esp_hal_dma/esp32c61/gdma_periph.c index aa9e0f5973e..e255e488946 100644 --- a/components/esp_hal_dma/esp32c61/gdma_periph.c +++ b/components/esp_hal_dma/esp32c61/gdma_periph.c @@ -25,94 +25,3 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; - -/* AHB_DMA Channel (Group0, Pair0) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG - AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG - AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG - - AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG - AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG - AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG - AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG -*/ -#define G0P0_RETENTION_REGS_CNT_0 13 -#define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG -#define G0P0_RETENTION_REGS_CNT_1 12 -#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG -static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; -static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; -static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ - G0P0_RETENTION_REGS_CNT_0, 0, 0, \ - g0p0_regs_map0[0], g0p0_regs_map0[1], \ - g0p0_regs_map0[2], g0p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ - G0P0_RETENTION_REGS_CNT_1, 0, 0, \ - g0p0_regs_map1[0], g0p0_regs_map1[1], \ - g0p0_regs_map1[2], g0p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AHB_DMA Channel (Group0, Pair1) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG - AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG - AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG - - AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG - AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG - AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG - AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG -*/ -#define G0P1_RETENTION_REGS_CNT_0 13 -#define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG -#define G0P1_RETENTION_REGS_CNT_1 12 -#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG -static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; -static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; -static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ - G0P1_RETENTION_REGS_CNT_0, 0, 0, \ - g0p1_regs_map0[0], g0p1_regs_map0[1], \ - g0p1_regs_map0[2], g0p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ - G0P1_RETENTION_REGS_CNT_1, 0, 0, \ - g0p1_regs_map1[0], g0p1_regs_map1[1], \ - g0p1_regs_map1[2], g0p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][2] = { - [0] = { - [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, - [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, - } -}; diff --git a/components/esp_hal_dma/esp32h2/gdma_periph.c b/components/esp_hal_dma/esp32h2/gdma_periph.c index 521706a645a..8bd210336f3 100644 --- a/components/esp_hal_dma/esp32h2/gdma_periph.c +++ b/components/esp_hal_dma/esp32h2/gdma_periph.c @@ -30,94 +30,3 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; - -/* GDMA Channel (Group0, Pair0) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG - GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG - GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG -*/ -#define G0P0_RETENTION_REGS_CNT 13 -#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG -static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; -static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ - G0P0_RETENTION_REGS_CNT, 0, 0, \ - g0p0_regs_map[0], g0p0_regs_map[1], \ - g0p0_regs_map[2], g0p0_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* GDMA Channel (Group0, Pair1) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG - GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG - GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG -*/ -#define G0P1_RETENTION_REGS_CNT 13 -#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG -static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; -static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ - G0P1_RETENTION_REGS_CNT, 0, 0, \ - g0p1_regs_map[0], g0p1_regs_map[1], \ - g0p1_regs_map[2], g0p1_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* GDMA Channel (Group0, Pair2) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG - GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG - GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG -*/ -#define G0P2_RETENTION_REGS_CNT_0 6 -#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG -#define G0P2_RETENTION_REGS_CNT_1 7 -#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG -static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; -static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; -static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = { - [0] = { - [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, - [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, - [2] = { - gdma_g0p2_regs_retention, - ARRAY_SIZE(gdma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH2, - } - } -}; diff --git a/components/esp_hal_dma/esp32h21/gdma_periph.c b/components/esp_hal_dma/esp32h21/gdma_periph.c index d6cc76dedfe..b5ec35f241f 100644 --- a/components/esp_hal_dma/esp32h21/gdma_periph.c +++ b/components/esp_hal_dma/esp32h21/gdma_periph.c @@ -30,96 +30,3 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; - -#if SOC_PAU_SUPPORTED -/* GDMA Channel (Group0, Pair0) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG - GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG - GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG -*/ -#define G0P0_RETENTION_REGS_CNT 13 -#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG -static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; -static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ - G0P0_RETENTION_REGS_CNT, 0, 0, \ - g0p0_regs_map[0], g0p0_regs_map[1], \ - g0p0_regs_map[2], g0p0_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* GDMA Channel (Group0, Pair1) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG - GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG - GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG -*/ -#define G0P1_RETENTION_REGS_CNT 13 -#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG -static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; -static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ - G0P1_RETENTION_REGS_CNT, 0, 0, \ - g0p1_regs_map[0], g0p1_regs_map[1], \ - g0p1_regs_map[2], g0p1_regs_map[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* GDMA Channel (Group0, Pair2) Registers Context - Include: GDMA_MISC_CONF_REG / - GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG - GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG - GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG -*/ -#define G0P2_RETENTION_REGS_CNT_0 6 -#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG -#define G0P2_RETENTION_REGS_CNT_1 7 -#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG -static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; -static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; -static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][3] = { - [0] = { - [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, - [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, - [2] = { - gdma_g0p2_regs_retention, - ARRAY_SIZE(gdma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH2, - } - } -}; -#endif diff --git a/components/esp_hal_dma/esp32h4/gdma_periph.c b/components/esp_hal_dma/esp32h4/gdma_periph.c index 26f8c3d4cd1..2f67a5d2969 100644 --- a/components/esp_hal_dma/esp32h4/gdma_periph.c +++ b/components/esp_hal_dma/esp32h4/gdma_periph.c @@ -40,272 +40,3 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; - -#if SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION -/* AHB_DMA Channel (Group0, Pair0) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG - AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG - AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG - AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG - AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG - AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG - AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG - - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ -#define G0P0_RETENTION_REGS_CNT_0 19 -#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) -#define G0P0_RETENTION_REGS_CNT_1 4 -#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600) -static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c}; -static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ - G0P0_RETENTION_REGS_CNT_0, 0, 0, \ - g0p0_regs_map0[0], g0p0_regs_map0[1], \ - g0p0_regs_map0[2], g0p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ - G0P0_RETENTION_REGS_CNT_1, 0, 0, \ - g0p0_regs_map1[0], g0p0_regs_map1[1], \ - g0p0_regs_map1[2], g0p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AHB_DMA Channel (Group0, Pair1) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG - - AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG - AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG - AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG - AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG - AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG - AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG - - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ - -#define G0P1_RETENTION_REGS_CNT_0 3 -#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) -#define G0P1_RETENTION_REGS_CNT_1 16 -#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200) -#define G0P1_RETENTION_REGS_CNT_2 4 -#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) -static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0}; -static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; -static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ - G0P1_RETENTION_REGS_CNT_0, 0, 0, \ - g0p1_regs_map0[0], g0p1_regs_map0[1], \ - g0p1_regs_map0[2], g0p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ - G0P1_RETENTION_REGS_CNT_1, 0, 0, \ - g0p1_regs_map1[0], g0p1_regs_map1[1], \ - g0p1_regs_map1[2], g0p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \ - G0P1_RETENTION_REGS_CNT_2, 0, 0, \ - g0p1_regs_map2[0], g0p1_regs_map2[1], \ - g0p1_regs_map2[2], g0p1_regs_map2[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AHB_DMA Channel (Group0, Pair2) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG - - AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG - AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG - AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG - AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG - AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG - AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG - - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ -#define G0P2_RETENTION_REGS_CNT_0 3 -#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) -#define G0P2_RETENTION_REGS_CNT_1 16 -#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300) -#define G0P2_RETENTION_REGS_CNT_2 4 -#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) -static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x8, 0x0, 0x0}; -static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; -static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \ - G0P2_RETENTION_REGS_CNT_2, 0, 0, \ - g0p2_regs_map2[0], g0p2_regs_map2[1], \ - g0p2_regs_map2[2], g0p2_regs_map2[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AHB_DMA Channel (Group0, Pair3) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG - - AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG - AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG - AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG - AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG - AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG - AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG - - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ -#define G0P3_RETENTION_REGS_CNT_0 3 -#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38) -#define G0P3_RETENTION_REGS_CNT_1 16 -#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400) -#define G0P3_RETENTION_REGS_CNT_2 4 -#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) -static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x8, 0x0, 0x0}; -static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; -static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t gdma_g0p3_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \ - G0P3_RETENTION_REGS_CNT_0, 0, 0, \ - g0p3_regs_map0[0], g0p3_regs_map0[1], \ - g0p3_regs_map0[2], g0p3_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \ - G0P3_RETENTION_REGS_CNT_1, 0, 0, \ - g0p3_regs_map1[0], g0p3_regs_map1[1], \ - g0p3_regs_map1[2], g0p3_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \ - G0P3_RETENTION_REGS_CNT_2, 0, 0, \ - g0p3_regs_map2[0], g0p3_regs_map2[1], \ - g0p3_regs_map2[2], g0p3_regs_map2[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AHB_DMA Channel (Group0, Pair4) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG - - AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG - AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG - AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG - AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG - AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG - AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ -#define G0P4_RETENTION_REGS_CNT_0 3 -#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48) -#define G0P4_RETENTION_REGS_CNT_1 20 -#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500) -static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x8, 0x0, 0x0}; -static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0}; -static const regdma_entries_config_t gdma_g0p4_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \ - G0P4_RETENTION_REGS_CNT_0, 0, 0, \ - g0p4_regs_map0[0], g0p4_regs_map0[1], \ - g0p4_regs_map0[2], g0p4_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \ - G0P4_RETENTION_REGS_CNT_1, 0, 0, \ - g0p4_regs_map1[0], g0p4_regs_map1[1], \ - g0p4_regs_map1[2], g0p4_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[1][5] = { - [0] = { - [0] = { - gdma_g0p0_regs_retention, - ARRAY_SIZE(gdma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH0, - }, - [1] = { - gdma_g0p1_regs_retention, - ARRAY_SIZE(gdma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH1, - }, - [2] = { - gdma_g0p2_regs_retention, - ARRAY_SIZE(gdma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH2, - }, - [3] = { - gdma_g0p3_regs_retention, - ARRAY_SIZE(gdma_g0p3_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH3, - }, - [4] = { - gdma_g0p4_regs_retention, - ARRAY_SIZE(gdma_g0p4_regs_retention), - SLEEP_RETENTION_MODULE_GDMA_CH4, - }, - } -}; -#endif // SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION diff --git a/components/esp_hal_dma/esp32p4/gdma_periph.c b/components/esp_hal_dma/esp32p4/gdma_periph.c index ac33c2c5eb5..4bc6071eda0 100644 --- a/components/esp_hal_dma/esp32p4/gdma_periph.c +++ b/components/esp_hal_dma/esp32p4/gdma_periph.c @@ -50,259 +50,3 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; - -/* AHB_DMA Channel (Group0, Pair0) Registers Context - Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG - AHB_DMA_MISC_CONF_REG / - AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG - AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_IN_PRI_CH0_REG - AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG - - Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. -*/ -#define AHB_DMA_G0P0_RETENTION_REGS_CNT_0 13 -#define AHB_DMA_G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG -#define AHB_DMA_G0P0_RETENTION_REGS_CNT_1 12 -#define AHB_DMA_G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG -static const uint32_t ahb_dma_g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; -static const uint32_t ahb_dma_g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; -static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AHB_DMA_G0P0_RETENTION_MAP_BASE_0, AHB_DMA_G0P0_RETENTION_MAP_BASE_0, \ - AHB_DMA_G0P0_RETENTION_REGS_CNT_0, 0, 0, \ - ahb_dma_g0p0_regs_map0[0], ahb_dma_g0p0_regs_map0[1], \ - ahb_dma_g0p0_regs_map0[2], ahb_dma_g0p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AHB_DMA_G0P0_RETENTION_MAP_BASE_1, AHB_DMA_G0P0_RETENTION_MAP_BASE_1, \ - AHB_DMA_G0P0_RETENTION_REGS_CNT_1, 0, 0, \ - ahb_dma_g0p0_regs_map1[0], ahb_dma_g0p0_regs_map1[1], \ - ahb_dma_g0p0_regs_map1[2], ahb_dma_g0p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AHB_DMA Channel (Group0, Pair1) Registers Context - Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG - AHB_DMA_MISC_CONF_REG / - AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG - AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_IN_PRI_CH1_REG - AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG - - Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. -*/ -#define AHB_DMA_G0P1_RETENTION_REGS_CNT_0 13 -#define AHB_DMA_G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG -#define AHB_DMA_G0P1_RETENTION_REGS_CNT_1 12 -#define AHB_DMA_G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG -static const uint32_t ahb_dma_g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604}; -static const uint32_t ahb_dma_g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; -static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AHB_DMA_G0P1_RETENTION_MAP_BASE_0, AHB_DMA_G0P1_RETENTION_MAP_BASE_0, \ - AHB_DMA_G0P1_RETENTION_REGS_CNT_0, 0, 0, \ - ahb_dma_g0p1_regs_map0[0], ahb_dma_g0p1_regs_map0[1], \ - ahb_dma_g0p1_regs_map0[2], ahb_dma_g0p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AHB_DMA_G0P1_RETENTION_MAP_BASE_1, AHB_DMA_G0P1_RETENTION_MAP_BASE_1, \ - AHB_DMA_G0P1_RETENTION_REGS_CNT_1, 0, 0, \ - ahb_dma_g0p1_regs_map1[0], ahb_dma_g0p1_regs_map1[1], \ - ahb_dma_g0p1_regs_map1[2], ahb_dma_g0p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AHB_DMA Channel (Group0, Pair2) Registers Context - Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG - AHB_DMA_MISC_CONF_REG / - AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG - AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_IN_PRI_CH2_REG - AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG - - Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. -*/ -#define AHB_DMA_G0P2_RETENTION_REGS_CNT_0 6 -#define AHB_DMA_G0P2_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH2_REG -#define AHB_DMA_G0P2_RETENTION_REGS_CNT_1 19 -#define AHB_DMA_G0P2_RETENTION_MAP_BASE_1 AHB_DMA_IN_PRI_CH2_REG -static const uint32_t ahb_dma_g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; -static const uint32_t ahb_dma_g0p2_regs_map1[4] = {0x3026003, 0x0, 0x30, 0xfe4c}; -static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AHB_DMA_G0P2_RETENTION_MAP_BASE_0, AHB_DMA_G0P2_RETENTION_MAP_BASE_0, \ - AHB_DMA_G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - ahb_dma_g0p2_regs_map0[0], ahb_dma_g0p2_regs_map0[1], \ - ahb_dma_g0p2_regs_map0[2], ahb_dma_g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AHB_DMA_G0P2_RETENTION_MAP_BASE_1, AHB_DMA_G0P2_RETENTION_MAP_BASE_1, \ - AHB_DMA_G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - ahb_dma_g0p2_regs_map1[0], ahb_dma_g0p2_regs_map1[1], \ - ahb_dma_g0p2_regs_map1[2], ahb_dma_g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AXI_DMA Channel (Group1, Pair0) Registers Context - Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG - AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG - AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG - AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG - AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG - AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG - AXI_DMA_MISC_CONF_REG - - Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. -*/ -#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14 -#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG -#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8 -#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG -static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; -static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \ - axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \ - axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AXI_DMA Channel (Group1, Pair1) Registers Context - Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG - AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG - AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG - AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG - AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG - AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG - AXI_DMA_MISC_CONF_REG - - Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. -*/ -#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14 -#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG -#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8 -#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG -static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; -static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \ - axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \ - axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AXI_DMA Channel (Group1, Pair2) Registers Context - Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG - AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG - AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG - AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG - AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG - AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG - AXI_DMA_MISC_CONF_REG - - Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. -*/ -#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14 -#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG -#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8 -#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG -static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; -static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \ - axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \ - axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[2][3] = { - [0] = { - [0] = { - ahb_dma_g0p0_regs_retention, - ARRAY_SIZE(ahb_dma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH0, - }, - [1] = { - ahb_dma_g0p1_regs_retention, - ARRAY_SIZE(ahb_dma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH1, - }, - [2] = { - ahb_dma_g0p2_regs_retention, - ARRAY_SIZE(ahb_dma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH2, - }, - }, - [1] = { - [0] = { - axi_dma_g1p0_regs_retention, - ARRAY_SIZE(axi_dma_g1p0_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH0, - }, - [1] = { - axi_dma_g1p1_regs_retention, - ARRAY_SIZE(axi_dma_g1p1_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH1, - }, - [2] = { - axi_dma_g1p2_regs_retention, - ARRAY_SIZE(axi_dma_g1p2_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH2, - }, - } -}; diff --git a/components/esp_hal_dma/esp32s31/gdma_periph.c b/components/esp_hal_dma/esp32s31/gdma_periph.c index 22e1b6deb23..33d6562666c 100644 --- a/components/esp_hal_dma/esp32s31/gdma_periph.c +++ b/components/esp_hal_dma/esp32s31/gdma_periph.c @@ -72,391 +72,3 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; - -#if SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION -/* AHB_DMA Channel (Group0, Pair0) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG - AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG - AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG - AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG - AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG - AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG - AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG - - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ -#define G0P0_RETENTION_REGS_CNT_0 19 -#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) -#define G0P0_RETENTION_REGS_CNT_1 4 -#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600) -static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c}; -static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ - G0P0_RETENTION_REGS_CNT_0, 0, 0, \ - g0p0_regs_map0[0], g0p0_regs_map0[1], \ - g0p0_regs_map0[2], g0p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ - G0P0_RETENTION_REGS_CNT_1, 0, 0, \ - g0p0_regs_map1[0], g0p0_regs_map1[1], \ - g0p0_regs_map1[2], g0p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AHB_DMA Channel (Group0, Pair1) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG - - AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG - AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG - AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG - AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG - AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG - AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG - - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ - -#define G0P1_RETENTION_REGS_CNT_0 3 -#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) -#define G0P1_RETENTION_REGS_CNT_1 16 -#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200) -#define G0P1_RETENTION_REGS_CNT_2 4 -#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) -static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0}; -static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; -static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ - G0P1_RETENTION_REGS_CNT_0, 0, 0, \ - g0p1_regs_map0[0], g0p1_regs_map0[1], \ - g0p1_regs_map0[2], g0p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ - G0P1_RETENTION_REGS_CNT_1, 0, 0, \ - g0p1_regs_map1[0], g0p1_regs_map1[1], \ - g0p1_regs_map1[2], g0p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \ - G0P1_RETENTION_REGS_CNT_2, 0, 0, \ - g0p1_regs_map2[0], g0p1_regs_map2[1], \ - g0p1_regs_map2[2], g0p1_regs_map2[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AHB_DMA Channel (Group0, Pair2) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG - - AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG - AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG - AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG - AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG - AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG - AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG - - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ -#define G0P2_RETENTION_REGS_CNT_0 3 -#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) -#define G0P2_RETENTION_REGS_CNT_1 16 -#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300) -#define G0P2_RETENTION_REGS_CNT_2 4 -#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) -static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x8, 0x0, 0x0}; -static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; -static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ - G0P2_RETENTION_REGS_CNT_0, 0, 0, \ - g0p2_regs_map0[0], g0p2_regs_map0[1], \ - g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ - G0P2_RETENTION_REGS_CNT_1, 0, 0, \ - g0p2_regs_map1[0], g0p2_regs_map1[1], \ - g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \ - G0P2_RETENTION_REGS_CNT_2, 0, 0, \ - g0p2_regs_map2[0], g0p2_regs_map2[1], \ - g0p2_regs_map2[2], g0p2_regs_map2[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AHB_DMA Channel (Group0, Pair3) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG - - AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG - AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG - AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG - AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG - AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG - AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG - - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ -#define G0P3_RETENTION_REGS_CNT_0 3 -#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38) -#define G0P3_RETENTION_REGS_CNT_1 16 -#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400) -#define G0P3_RETENTION_REGS_CNT_2 4 -#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600) -static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x8, 0x0, 0x0}; -static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; -static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t ahb_dma_g0p3_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \ - G0P3_RETENTION_REGS_CNT_0, 0, 0, \ - g0p3_regs_map0[0], g0p3_regs_map0[1], \ - g0p3_regs_map0[2], g0p3_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \ - G0P3_RETENTION_REGS_CNT_1, 0, 0, \ - g0p3_regs_map1[0], g0p3_regs_map1[1], \ - g0p3_regs_map1[2], g0p3_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \ - G0P3_RETENTION_REGS_CNT_2, 0, 0, \ - g0p3_regs_map2[0], g0p3_regs_map2[1], \ - g0p3_regs_map2[2], g0p3_regs_map2[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AHB_DMA Channel (Group0, Pair4) Registers Context - Include: AHB_DMA_MISC_CONF_REG - AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG - - AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG - AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG - AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG - AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG - AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG - AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG - AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG -*/ -#define G0P4_RETENTION_REGS_CNT_0 3 -#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48) -#define G0P4_RETENTION_REGS_CNT_1 20 -#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500) -static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x8, 0x0, 0x0}; -static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0}; -static const regdma_entries_config_t ahb_dma_g0p4_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \ - G0P4_RETENTION_REGS_CNT_0, 0, 0, \ - g0p4_regs_map0[0], g0p4_regs_map0[1], \ - g0p4_regs_map0[2], g0p4_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ - G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \ - G0P4_RETENTION_REGS_CNT_1, 0, 0, \ - g0p4_regs_map1[0], g0p4_regs_map1[1], \ - g0p4_regs_map1[2], g0p4_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, \ -}; - -/* AXI_DMA Channel (Group1, Pair0) Registers Context - Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG - AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG - AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG - AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG - AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG - AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG - AXI_DMA_MISC_CONF_REG -*/ -#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14 -#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG -#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8 -#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG -static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; -static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \ - axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \ - axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AXI_DMA Channel (Group1, Pair1) Registers Context - Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG - AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG - AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG - AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG - AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG - AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG - AXI_DMA_MISC_CONF_REG -*/ -#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14 -#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG -#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8 -#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG -static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; -static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \ - axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \ - axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -/* AXI_DMA Channel (Group1, Pair2) Registers Context - Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG - AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG - AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG - AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG - AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG - AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG - AXI_DMA_MISC_CONF_REG -*/ -#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14 -#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG -#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8 -#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG -static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; -static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ - AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \ - AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \ - axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \ - axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ - AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \ - AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \ - axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \ - axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \ - .owner = GDMA_RETENTION_ENTRY - }, -}; - -const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[2][5] = { - [0] = { - [0] = { - ahb_dma_g0p0_regs_retention, - ARRAY_SIZE(ahb_dma_g0p0_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH0, - }, - [1] = { - ahb_dma_g0p1_regs_retention, - ARRAY_SIZE(ahb_dma_g0p1_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH1, - }, - [2] = { - ahb_dma_g0p2_regs_retention, - ARRAY_SIZE(ahb_dma_g0p2_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH2, - }, - [3] = { - ahb_dma_g0p3_regs_retention, - ARRAY_SIZE(ahb_dma_g0p3_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH3, - }, - [4] = { - ahb_dma_g0p4_regs_retention, - ARRAY_SIZE(ahb_dma_g0p4_regs_retention), - SLEEP_RETENTION_MODULE_AHB_DMA_CH4, - }, - }, - [1] = { - [0] = { - axi_dma_g1p0_regs_retention, - ARRAY_SIZE(axi_dma_g1p0_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH0, - }, - [1] = { - axi_dma_g1p1_regs_retention, - ARRAY_SIZE(axi_dma_g1p1_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH1, - }, - [2] = { - axi_dma_g1p2_regs_retention, - ARRAY_SIZE(axi_dma_g1p2_regs_retention), - SLEEP_RETENTION_MODULE_AXI_DMA_CH2, - }, - } -}; -#endif // SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION diff --git a/components/esp_hal_dma/include/hal/gdma_periph.h b/components/esp_hal_dma/include/hal/gdma_periph.h index 836b71eb5a7..35c4d25dc72 100644 --- a/components/esp_hal_dma/include/hal/gdma_periph.h +++ b/components/esp_hal_dma/include/hal/gdma_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,23 +8,9 @@ #include "soc/soc_caps.h" #include "soc/periph_defs.h" -#include "soc/regdma.h" #if SOC_HAS(GDMA) #include "hal/gdma_ll.h" #endif -#if SOC_HAS(PAU) -#include "soc/retention_periph_defs.h" -#endif - -#if CI_TEST_SW_RETENTION -#define GDMA_RETENTION_ENTRY REGDMA_SW_TRIGGER_ENTRY -#else -#if SOC_PHY_SUPPORTED -#define GDMA_RETENTION_ENTRY (ENTRY(0) | ENTRY(2)) -#else -#define GDMA_RETENTION_ENTRY (ENTRY(0)) -#endif -#endif #ifdef __cplusplus extern "C" { @@ -46,16 +32,6 @@ typedef struct { extern const gdma_signal_conn_t gdma_periph_signals; -#if SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_LIGHT_SLEEP_SUPPORTED -typedef struct { - const regdma_entries_config_t *link_list; - uint32_t link_num; - const periph_retention_module_t module_id; -} gdma_chx_reg_ctx_link_t; - -extern const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[GDMA_LL_GET(INST_NUM)][GDMA_LL_GET(PAIRS_PER_INST)]; -#endif - #endif #ifdef __cplusplus diff --git a/components/esp_hw_support/port/esp32h4/peripheral_domain_pd.c b/components/esp_hw_support/port/esp32h4/peripheral_domain_pd.c index 06dbbfb8d7a..a8aa135d8ec 100644 --- a/components/esp_hw_support/port/esp32h4/peripheral_domain_pd.c +++ b/components/esp_hw_support/port/esp32h4/peripheral_domain_pd.c @@ -41,6 +41,8 @@ bool peripheral_domain_pd_allowed(void) RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH0); RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH1); RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH2); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH3); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GDMA_CH4); // ESP32H4 supports PAU and I2S sleep retention RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2S0);