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Merge branch 'bugfix/esp32s31_raise_ahb_clk_freq' into 'master'

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fix(clk): raised ESP32S31 axi/ahb clock freq up to 106mhz at max

Closes IDF-14696

See merge request espressif/esp-idf!48207
This commit is contained in:
morris
2026-05-25 18:23:37 +08:00
parent bd29b11895 3ba8d08d02
commit c23e87b81b
2 changed files with 17 additions and 6 deletions
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2
components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
View File

@@ -112,7 +112,7 @@ esp_err_t bootloader_init(void)
{
esp_err_t ret = ESP_OK;
bootloader_hardware_init(); // TODO: IDF-14696
bootloader_hardware_init();
bootloader_ana_reset_config();
#if SOC_RTC_WDT_SUPPORTED
bootloader_super_wdt_auto_feed();

21
components/esp_hw_support/port/esp32s31/rtc_clk.c
View File

@@ -230,13 +230,14 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
*
* Current available configurations:
* CPLL -> CPU_CLK -> MEM_CLK
* -> SYS_CLK -> APB_CLK
* -> SYS_CLK -> APB_CLK
* 320 div1 320 div2 160
* div4 80 div2 40
* div3 320/3(106.67) div2 320/6(53.33)
* 320 div2 160 div1 160
* div2 80 div2 40
* div2 80 div2 40
* 320 div4 80 div1 80
* div1 80 div2 40
* div1 80 div2 40
* 320 div6 53.33 div1 53.33 div1 53.33
*/
uint32_t mem_divider = 1;
uint32_t sys_divider = 1;
@@ -244,7 +245,7 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
switch (cpu_freq_mhz) {
case 320:
mem_divider = 2;
sys_divider = 4;
sys_divider = 3;
apb_divider = 2;
break;
case 160:
@@ -257,6 +258,11 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
sys_divider = 1;
apb_divider = 2;
break;
case 53:
mem_divider = 1;
sys_divider = 1;
apb_divider = 1;
break;
default:
// Unsupported configuration
// This is dangerous to modify dividers. Hardware could automatically correct the divider, and it won't be
@@ -291,6 +297,11 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
}
source_freq_mhz = xtal_freq;
source = SOC_CPU_CLK_SRC_XTAL;
} else if (freq_mhz == 53) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_CPLL;
source_freq_mhz = CLK_LL_PLL_320M_FREQ_MHZ;
divider.integer = 6;
} else if (freq_mhz == 80) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_CPLL;