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Merge branch 'fix/fix_parlio_valid_delay_max_value' into 'master'

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fix(parlio): fix max valid delay value

See merge request espressif/esp-idf!48577
This commit is contained in:
morris
2026-05-25 18:13:57 +08:00
parent b6a2af2fe1 440f0cb225
commit bd29b11895
3 changed files with 5 additions and 5 deletions
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2
components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h
View File

@@ -42,7 +42,7 @@
#define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL)
#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal
#define PARLIO_LL_TX_VALID_MAX_DELAY 32767
#define PARLIO_LL_TX_VALID_MAX_DELAY 65535
#ifdef __cplusplus
extern "C" {
#endif

2
components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h
View File

@@ -42,7 +42,7 @@
#define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL)
#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal
#define PARLIO_LL_TX_VALID_MAX_DELAY 32767
#define PARLIO_LL_TX_VALID_MAX_DELAY 65535
#ifdef __cplusplus
extern "C" {
#endif

6
components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h
View File

@@ -49,7 +49,7 @@
#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 15 // TXD[15] can be used as clock gate signal
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define PARLIO_LL_TX_VALID_MAX_DELAY 32767
#define PARLIO_LL_TX_VALID_MAX_DELAY 65535
#define PARLIO_LL_SUPPORT_TX_EOF_FROM_DMA 1 // Support to treat DMA EOF as TX unit EOF
#endif
@@ -136,6 +136,7 @@ static inline void _parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clo
HAL_ASSERT(false);
break;
}
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = (src == PARLIO_CLK_SRC_EXTERNAL);
HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_src_sel = clk_sel;
}
@@ -197,7 +198,6 @@ __attribute__((always_inline))
static inline void _parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en)
{
(void)dev;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = en;
HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_en = en;
}
@@ -486,6 +486,7 @@ static inline void _parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clo
HAL_ASSERT(false);
break;
}
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = (src == PARLIO_CLK_SRC_EXTERNAL);
HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_src_sel = clk_sel;
}
@@ -548,7 +549,6 @@ __attribute__((always_inline))
static inline void _parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
{
(void)dev;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = en;
HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_en = en;
}