Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-06-08 22:26:32 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'ci/ulp_fsm_i_wr_reg_v5.3' into 'release/v5.3'

Browse Source 
test(ulp): added larger delay in ULP FSM I_WR_REG instruction test (v5.3)

See merge request espressif/esp-idf!43424
This commit is contained in:
Marius Vikhammer
2025-11-18 09:27:11 +08:00
parent 9a38d629c1 bfc3815ce6
commit bd6bd6bc2d
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
components/ulp/test_apps/ulp_fsm/main/test_ulp.c
View File

@@ -362,7 +362,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
TEST_ESP_OK(ulp_run(0));
/* Wait for the ULP co-processor to finish up */
vTaskDelay(10 / portTICK_PERIOD_MS);
vTaskDelay(50 / portTICK_PERIOD_MS);
/* Verify the test results */
uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);