From bfc3815ce6aec7444882bf2d7f4aeda316a4c43f Mon Sep 17 00:00:00 2001
From: Marius Vikhammer <marius.vikhammer@espressif.com>
Date: Mon, 17 Nov 2025 16:03:15 +0800
Subject: [PATCH] test(ulp): added larger delay in ULP FSM I_WR_REG instruction
 test

Test is flakey, could possibly be due to the ULP occasionally needing
a bit more time to start up.
---
 components/ulp/test_apps/ulp_fsm/main/test_ulp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c
index ee4ae12f88b..faa44964f6d 100644
--- a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c
+++ b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c
@@ -362,7 +362,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
         TEST_ESP_OK(ulp_run(0));
 
         /* Wait for the ULP co-processor to finish up */
-        vTaskDelay(10 / portTICK_PERIOD_MS);
+        vTaskDelay(50 / portTICK_PERIOD_MS);
 
         /* Verify the test results */
         uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);