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fix(soc): make SOC_RAM_ICACHE1_HIGH an exclusive bound on ESP32-H4

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Every other SOC_*_HIGH macro in soc.h is an exclusive region end;
SOC_RAM_ICACHE1_HIGH was the inclusive last byte (0x40867fff). This
also made the reclaimed ICache1 heap region in single core mode
(components/heap/port/esp32h4/memory_layout.c, sized as HIGH - LOW)
one byte short. Change the value to the exclusive end 0x40868000 and
drop the +1 compensation at the SOC_HP_RAM_HIGH definition.
This commit is contained in:
harshal.patil
2026-08-25 10:40:28 +05:30
parent 07debe6edc
commit a7f4dbf35a
2 changed files with 2 additions and 2 deletions
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components/esp_hw_support/port/esp32h4/cpu_region_protect.c
+1 -1
View File
@@ -45,7 +45,7 @@
* outside the valid RAM window. * outside the valid RAM window.
*/ */
#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
#define SOC_HP_RAM_HIGH (SOC_RAM_ICACHE1_HIGH + 1) #define SOC_HP_RAM_HIGH SOC_RAM_ICACHE1_HIGH
_Static_assert(SOC_IRAM_HIGH == SOC_RAM_ICACHE1_LOW, "ICache1 RAM must be contiguous with D/IRAM"); _Static_assert(SOC_IRAM_HIGH == SOC_RAM_ICACHE1_LOW, "ICache1 RAM must be contiguous with D/IRAM");
#else #else
#define SOC_HP_RAM_HIGH SOC_IRAM_HIGH #define SOC_HP_RAM_HIGH SOC_IRAM_HIGH
components/soc/esp32h4/include/soc/soc.h
+1 -1
View File
@@ -196,7 +196,7 @@
//ICache1 region //ICache1 region
#define SOC_RAM_ICACHE1_LOW 0x40860000 #define SOC_RAM_ICACHE1_LOW 0x40860000
#define SOC_RAM_ICACHE1_HIGH 0x40867fff #define SOC_RAM_ICACHE1_HIGH 0x40868000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.