From a7f4dbf35abdf78c631c9c639c155c19ca596af9 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Mon, 24 Aug 2026 13:25:58 +0530 Subject: [PATCH] fix(soc): make SOC_RAM_ICACHE1_HIGH an exclusive bound on ESP32-H4 Every other SOC_*_HIGH macro in soc.h is an exclusive region end; SOC_RAM_ICACHE1_HIGH was the inclusive last byte (0x40867fff). This also made the reclaimed ICache1 heap region in single core mode (components/heap/port/esp32h4/memory_layout.c, sized as HIGH - LOW) one byte short. Change the value to the exclusive end 0x40868000 and drop the +1 compensation at the SOC_HP_RAM_HIGH definition. --- components/esp_hw_support/port/esp32h4/cpu_region_protect.c | 2 +- components/soc/esp32h4/include/soc/soc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/esp_hw_support/port/esp32h4/cpu_region_protect.c b/components/esp_hw_support/port/esp32h4/cpu_region_protect.c index 2358bf35515..7cfa4be33f1 100644 --- a/components/esp_hw_support/port/esp32h4/cpu_region_protect.c +++ b/components/esp_hw_support/port/esp32h4/cpu_region_protect.c @@ -45,7 +45,7 @@ * outside the valid RAM window. */ #if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE -#define SOC_HP_RAM_HIGH (SOC_RAM_ICACHE1_HIGH + 1) +#define SOC_HP_RAM_HIGH SOC_RAM_ICACHE1_HIGH _Static_assert(SOC_IRAM_HIGH == SOC_RAM_ICACHE1_LOW, "ICache1 RAM must be contiguous with D/IRAM"); #else #define SOC_HP_RAM_HIGH SOC_IRAM_HIGH diff --git a/components/soc/esp32h4/include/soc/soc.h b/components/soc/esp32h4/include/soc/soc.h index 95d452909a5..4f85684dc31 100644 --- a/components/soc/esp32h4/include/soc/soc.h +++ b/components/soc/esp32h4/include/soc/soc.h @@ -196,7 +196,7 @@ //ICache1 region #define SOC_RAM_ICACHE1_LOW 0x40860000 -#define SOC_RAM_ICACHE1_HIGH 0x40867fff +#define SOC_RAM_ICACHE1_HIGH 0x40868000 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.