Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(soc): make SOC_RAM_ICACHE1_HIGH an exclusive bound on ESP32-H4

Browse Source 
Every other SOC_*_HIGH macro in soc.h is an exclusive region end;
SOC_RAM_ICACHE1_HIGH was the inclusive last byte (0x40867fff). This
also made the reclaimed ICache1 heap region in single core mode
(components/heap/port/esp32h4/memory_layout.c, sized as HIGH - LOW)
one byte short. Change the value to the exclusive end 0x40868000 and
drop the +1 compensation at the SOC_HP_RAM_HIGH definition.
This commit is contained in:
harshal.patil
2026-08-25 10:40:28 +05:30
parent 07debe6edc
commit a7f4dbf35a
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32h4/include/soc/soc.h
+1 -1
View File
@@ -196,7 +196,7 @@
//ICache1 region
#define SOC_RAM_ICACHE1_LOW 0x40860000
#define SOC_RAM_ICACHE1_HIGH 0x40867fff
#define SOC_RAM_ICACHE1_HIGH 0x40868000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.