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Merge branch 'feat/enable_zcmp_for_c5_c61_v6.1' into 'release/v6.1'

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feat(soc): esp32c5, esp32c61: enable zc extensions (v6.1)

See merge request espressif/esp-idf!51525
This commit is contained in:
Jiang Jiang Jian
2026-09-03 20:41:23 +08:00
parent 089ccceb01 1ed4ec55ba
commit a4bbf950c8
8 changed files with 16 additions and 2 deletions
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components/esp_libc/test_apps/newlib/pytest_newlib.py
+1
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@@ -17,6 +17,7 @@ from pytest_embedded_idf.utils import idf_parametrize
('release_esp32', 'esp32'),
('release_esp32c2', 'esp32c2'),
('misaligned_mem', 'esp32c3'),
('zcmp', 'esp32c5'),
],
indirect=['config', 'target'],
)
components/esp_libc/test_apps/newlib/sdkconfig.ci.zcmp
+1
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@@ -0,0 +1 @@
CONFIG_COMPILER_ENABLE_RISCV_ZCMP=y
components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c
+1 -1
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@@ -300,8 +300,8 @@ BaseType_t xPortStartScheduler(void)
/* Setup the hardware to generate the tick. */
vPortSetupTimer();
esprv_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
rv_utils_intr_global_enable();
esprv_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
vPortYield();
components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
+1 -1
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@@ -170,8 +170,8 @@ BaseType_t xPortStartScheduler(void)
/* Setup the hardware to generate the tick. */
vPortSetupTimer();
esprv_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
rv_utils_intr_global_enable();
esprv_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
vPortYield();
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
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@@ -503,6 +503,10 @@ config SOC_CPU_HAS_LOCKUP_RESET
bool
default y
config SOC_CPU_HAS_ZC_EXTENSIONS
bool
default y
config SOC_CPU_ZCMP_WORKAROUND
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+2
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@@ -187,6 +187,8 @@
#define SOC_CPU_HAS_LOCKUP_RESET 1
#define SOC_CPU_HAS_ZC_EXTENSIONS 1
#define SOC_CPU_ZCMP_WORKAROUND 1
#define SOC_CPU_ZCMP_PUSH_REVERSED 1
#define SOC_CPU_ZCMP_POPRET_ISSUE 1
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+4
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@@ -387,6 +387,10 @@ config SOC_CPU_HAS_LOCKUP_RESET
bool
default y
config SOC_CPU_HAS_ZC_EXTENSIONS
bool
default y
config SOC_CPU_ZCMP_WORKAROUND
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
+2
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@@ -150,6 +150,8 @@
#define SOC_CPU_HAS_LOCKUP_RESET 1
#define SOC_CPU_HAS_ZC_EXTENSIONS 1
#define SOC_CPU_ZCMP_WORKAROUND 1
#define SOC_CPU_ZCMP_PUSH_REVERSED 1
#define SOC_CPU_ZCMP_POPRET_ISSUE 1