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update(pmu_sleep): enable SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED

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sibeibei
2026-06-10 20:40:09 +08:00
committed by yinqingzhao
parent 4c9cdf8710
commit 9a3b0b5f02
3 changed files with 25 additions and 2 deletions
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components/esp_hw_support/port/esp32s31/pmu_sleep.c
+8 -2
View File
@@ -160,7 +160,13 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
#else
const uint32_t slowclk_period_fixed = slowclk_period;
#endif
param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
@@ -168,7 +174,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
param->hp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->hp.isolate_wait_time_us, fastclk_period);
param->hp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->hp.reset_wait_time_us, fastclk_period);
param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period_fixed);
param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -1547,6 +1547,10 @@ config SOC_PM_SUPPORT_PMU_MODEM_STATE
bool
default y
config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
bool
default y
config SOC_PM_RETENTION_MODULE_NUM
int
default 64
components/soc/esp32s31/include/soc/soc_caps.h
+13
View File
@@ -575,6 +575,19 @@
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
#define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
/*
* min_slp_val is derived from slow clock period (450us / slow_clk).
* With internal slow clock, frequency drift may cause min_slp_val to vary.
* If the updated value becomes larger than the previous one, modem wakeup
* path may still use the old value, leading to inconsistent PMU timing and
* potential modem state hang.
*
* Therefore, when using internal slow clock, min_slp_val is fixed after init,
* and clock drift is handled via separate timing compensation instead of
* updating this PMU threshold dynamically.
*/
#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED (1)
#define SOC_PM_RETENTION_MODULE_NUM (64)
/*-------------------------- LP_CORE CAPS ------------------------------------*/