From 9a3b0b5f0208f52eac7010324135f6028c1ceacd Mon Sep 17 00:00:00 2001 From: sibeibei Date: Wed, 13 May 2026 21:27:47 +0800 Subject: [PATCH] update(pmu_sleep): enable SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED --- components/esp_hw_support/port/esp32s31/pmu_sleep.c | 10 ++++++++-- .../soc/esp32s31/include/soc/Kconfig.soc_caps.in | 4 ++++ components/soc/esp32s31/include/soc/soc_caps.h | 13 +++++++++++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/components/esp_hw_support/port/esp32s31/pmu_sleep.c b/components/esp_hw_support/port/esp32s31/pmu_sleep.c index 42837b69e76..0c07af6511e 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32s31/pmu_sleep.c @@ -160,7 +160,13 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default( { const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc; - param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period); +#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP) + const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period; +#else + const uint32_t slowclk_period_fixed = slowclk_period; +#endif + + param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed); param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period); param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period); param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period); @@ -168,7 +174,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default( param->hp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->hp.isolate_wait_time_us, fastclk_period); param->hp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->hp.reset_wait_time_us, fastclk_period); - param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period); + param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period_fixed); param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period); param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period); param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period); diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 1dad4c124f4..bb5607d56f9 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -1547,6 +1547,10 @@ config SOC_PM_SUPPORT_PMU_MODEM_STATE bool default y +config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED + bool + default y + config SOC_PM_RETENTION_MODULE_NUM int default 64 diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index 1d1b565d743..28cedcd7561 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -575,6 +575,19 @@ #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1) #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE +/* + * min_slp_val is derived from slow clock period (450us / slow_clk). + * With internal slow clock, frequency drift may cause min_slp_val to vary. + * If the updated value becomes larger than the previous one, modem wakeup + * path may still use the old value, leading to inconsistent PMU timing and + * potential modem state hang. + * + * Therefore, when using internal slow clock, min_slp_val is fixed after init, + * and clock drift is handled via separate timing compensation instead of + * updating this PMU threshold dynamically. + */ +#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED (1) + #define SOC_PM_RETENTION_MODULE_NUM (64) /*-------------------------- LP_CORE CAPS ------------------------------------*/