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test(mbedtls): add partial-block PSRAM coverage for AES
Extend the CTR test data length to 6433 bytes so the trailing partial block is exercised with external RAM buffers (which stalls the ESP32-S2 Crypto DMA on an unfixed driver).
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@@ -839,10 +839,10 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]")
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const uint8_t expected_cipher_ctr_end[] = {
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0x93, 0xca, 0xe0, 0x44, 0x96, 0x6d, 0xcb, 0xb2,
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0xcf, 0x8a, 0x8d, 0x73, 0x8c, 0x6b, 0xfa, 0x4d,
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0xd6, 0xc4, 0x18, 0x49, 0xdd, 0xc6, 0xbf, 0xc2,
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0xb9, 0xf0, 0x09, 0x69, 0x45, 0x42, 0xc6, 0x05,
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0x42, 0xf6, 0x3b, 0x8e, 0x11, 0x43, 0xc8, 0xc7,
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0xd9, 0x85, 0xf3, 0xdc, 0x39, 0x6b, 0x33, 0x98,
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0x8c, 0xc0, 0xf5, 0x92, 0xb4, 0x04, 0xf9, 0x2f,
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0xdf, 0x12, 0xc0, 0xa1, 0xd2, 0xdc, 0x71, 0x88,
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};
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@@ -852,7 +852,7 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps)
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uint8_t nonce[16];
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uint8_t key[16];
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uint8_t stream_block[16];
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size_t SZ = 32*200;
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size_t SZ = 32*200 + 33;
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size_t ALIGNMENT_SIZE_BYTES = 64;
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memset(nonce, 0x2F, 16);
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memset(key, 0x1E, 16);
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@@ -911,7 +911,7 @@ void aes_psram_one_buf_ctr_test(void)
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uint8_t nonce[16];
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uint8_t key[16];
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uint8_t stream_block[16];
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size_t SZ = 32*200;
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size_t SZ = 32*200 + 33;
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size_t ALIGNMENT_SIZE_BYTES = 32;
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memset(nonce, 0x2F, 16);
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memset(key, 0x1E, 16);
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