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Merge branch 'feat/update_esp32s31_socs' into 'master'

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feat(esp32s31): Add esp32s31 soc header files part1 (auto generate from a~i)

See merge request espressif/esp-idf!43471
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C.S.M
2025-11-19 10:59:39 +08:00
parent 27bb77e77c e0d62e664b
commit 929c24d6dd
78 changed files with 173899 additions and 0 deletions
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components/soc/esp32s31/register/soc/adc_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ADC_CTRL0_REG register
* Register
*/
#define ADC_CTRL0_REG (DR_REG_ADC_BASE + 0x0)
/** ADC_SAR1_TRIGGER_STOP : WT; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_SAR1_TRIGGER_STOP (BIT(0))
#define ADC_SAR1_TRIGGER_STOP_M (ADC_SAR1_TRIGGER_STOP_V << ADC_SAR1_TRIGGER_STOP_S)
#define ADC_SAR1_TRIGGER_STOP_V 0x00000001U
#define ADC_SAR1_TRIGGER_STOP_S 0
/** ADC_SAR1_TRIGGER_START : WT; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_SAR1_TRIGGER_START (BIT(1))
#define ADC_SAR1_TRIGGER_START_M (ADC_SAR1_TRIGGER_START_V << ADC_SAR1_TRIGGER_START_S)
#define ADC_SAR1_TRIGGER_START_V 0x00000001U
#define ADC_SAR1_TRIGGER_START_S 1
/** ADC_SAR1_TRIGGER_MODE : R/W; bitpos: [3:2]; default: 0;
* SAR clock divider
*/
#define ADC_SAR1_TRIGGER_MODE 0x00000003U
#define ADC_SAR1_TRIGGER_MODE_M (ADC_SAR1_TRIGGER_MODE_V << ADC_SAR1_TRIGGER_MODE_S)
#define ADC_SAR1_TRIGGER_MODE_V 0x00000003U
#define ADC_SAR1_TRIGGER_MODE_S 2
/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define ADC_SAR1_PATT_LEN 0x0000000FU
#define ADC_SAR1_PATT_LEN_M (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
#define ADC_SAR1_PATT_LEN_V 0x0000000FU
#define ADC_SAR1_PATT_LEN_S 14
/** ADC_SAR1_PATT_P_CLEAR : WT; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define ADC_SAR1_PATT_P_CLEAR (BIT(22))
#define ADC_SAR1_PATT_P_CLEAR_M (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
#define ADC_SAR1_PATT_P_CLEAR_V 0x00000001U
#define ADC_SAR1_PATT_P_CLEAR_S 22
/** ADC_SAR1_PATT_TYPE : R/W; bitpos: [23]; default: 0;
* 1: select meas start as table update 0:select mead done as table update
*/
#define ADC_SAR1_PATT_TYPE (BIT(23))
#define ADC_SAR1_PATT_TYPE_M (ADC_SAR1_PATT_TYPE_V << ADC_SAR1_PATT_TYPE_S)
#define ADC_SAR1_PATT_TYPE_V 0x00000001U
#define ADC_SAR1_PATT_TYPE_S 23
/** ADC_SAR1_CLK_POS_SEL : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
#define ADC_SAR1_CLK_POS_SEL (BIT(24))
#define ADC_SAR1_CLK_POS_SEL_M (ADC_SAR1_CLK_POS_SEL_V << ADC_SAR1_CLK_POS_SEL_S)
#define ADC_SAR1_CLK_POS_SEL_V 0x00000001U
#define ADC_SAR1_CLK_POS_SEL_S 24
/** ADC_SAR1_CONTINUE_MODE_EN : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
#define ADC_SAR1_CONTINUE_MODE_EN (BIT(25))
#define ADC_SAR1_CONTINUE_MODE_EN_M (ADC_SAR1_CONTINUE_MODE_EN_V << ADC_SAR1_CONTINUE_MODE_EN_S)
#define ADC_SAR1_CONTINUE_MODE_EN_V 0x00000001U
#define ADC_SAR1_CONTINUE_MODE_EN_S 25
/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
#define ADC_XPD_SAR1_FORCE 0x00000003U
#define ADC_XPD_SAR1_FORCE_M (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
#define ADC_XPD_SAR1_FORCE_V 0x00000003U
#define ADC_XPD_SAR1_FORCE_S 26
/** ADC_CTRL1_REG register
* Register
*/
#define ADC_CTRL1_REG (DR_REG_ADC_BASE + 0x4)
/** ADC_SAR2_TRIGGER_STOP : WT; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_SAR2_TRIGGER_STOP (BIT(0))
#define ADC_SAR2_TRIGGER_STOP_M (ADC_SAR2_TRIGGER_STOP_V << ADC_SAR2_TRIGGER_STOP_S)
#define ADC_SAR2_TRIGGER_STOP_V 0x00000001U
#define ADC_SAR2_TRIGGER_STOP_S 0
/** ADC_SAR2_TRIGGER_START : WT; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_SAR2_TRIGGER_START (BIT(1))
#define ADC_SAR2_TRIGGER_START_M (ADC_SAR2_TRIGGER_START_V << ADC_SAR2_TRIGGER_START_S)
#define ADC_SAR2_TRIGGER_START_V 0x00000001U
#define ADC_SAR2_TRIGGER_START_S 1
/** ADC_SAR2_TRIGGER_MODE : R/W; bitpos: [3:2]; default: 0;
* SAR clock divider
*/
#define ADC_SAR2_TRIGGER_MODE 0x00000003U
#define ADC_SAR2_TRIGGER_MODE_M (ADC_SAR2_TRIGGER_MODE_V << ADC_SAR2_TRIGGER_MODE_S)
#define ADC_SAR2_TRIGGER_MODE_V 0x00000003U
#define ADC_SAR2_TRIGGER_MODE_S 2
/** ADC_SAR2_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define ADC_SAR2_PATT_LEN 0x0000000FU
#define ADC_SAR2_PATT_LEN_M (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
#define ADC_SAR2_PATT_LEN_V 0x0000000FU
#define ADC_SAR2_PATT_LEN_S 14
/** ADC_SAR2_PATT_P_CLEAR : WT; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define ADC_SAR2_PATT_P_CLEAR (BIT(22))
#define ADC_SAR2_PATT_P_CLEAR_M (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
#define ADC_SAR2_PATT_P_CLEAR_V 0x00000001U
#define ADC_SAR2_PATT_P_CLEAR_S 22
/** ADC_SAR2_PATT_TYPE : R/W; bitpos: [23]; default: 0;
* 1: select meas start as table update 0:select mead done as table update
*/
#define ADC_SAR2_PATT_TYPE (BIT(23))
#define ADC_SAR2_PATT_TYPE_M (ADC_SAR2_PATT_TYPE_V << ADC_SAR2_PATT_TYPE_S)
#define ADC_SAR2_PATT_TYPE_V 0x00000001U
#define ADC_SAR2_PATT_TYPE_S 23
/** ADC_SAR2_CLK_POS_SEL : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
#define ADC_SAR2_CLK_POS_SEL (BIT(24))
#define ADC_SAR2_CLK_POS_SEL_M (ADC_SAR2_CLK_POS_SEL_V << ADC_SAR2_CLK_POS_SEL_S)
#define ADC_SAR2_CLK_POS_SEL_V 0x00000001U
#define ADC_SAR2_CLK_POS_SEL_S 24
/** ADC_SAR2_CONTINUE_MODE_EN : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
#define ADC_SAR2_CONTINUE_MODE_EN (BIT(25))
#define ADC_SAR2_CONTINUE_MODE_EN_M (ADC_SAR2_CONTINUE_MODE_EN_V << ADC_SAR2_CONTINUE_MODE_EN_S)
#define ADC_SAR2_CONTINUE_MODE_EN_V 0x00000001U
#define ADC_SAR2_CONTINUE_MODE_EN_S 25
/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
#define ADC_XPD_SAR2_FORCE 0x00000003U
#define ADC_XPD_SAR2_FORCE_M (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
#define ADC_XPD_SAR2_FORCE_V 0x00000003U
#define ADC_XPD_SAR2_FORCE_S 26
/** ADC_CTRL2_REG register
* Register
*/
#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x8)
/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define ADC_TIMER_TARGET 0x00000FFFU
#define ADC_TIMER_TARGET_M (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
#define ADC_TIMER_TARGET_V 0x00000FFFU
#define ADC_TIMER_TARGET_S 12
/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define ADC_TIMER_EN (BIT(24))
#define ADC_TIMER_EN_M (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
#define ADC_TIMER_EN_V 0x00000001U
#define ADC_TIMER_EN_S 24
/** ADC_FILTER_CTRL1_REG register
* Register
*/
#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0xc)
/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* need_des
*/
#define ADC_FILTER_FACTOR1 0x00000007U
#define ADC_FILTER_FACTOR1_M (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
#define ADC_FILTER_FACTOR1_V 0x00000007U
#define ADC_FILTER_FACTOR1_S 26
/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
#define ADC_FILTER_FACTOR0 0x00000007U
#define ADC_FILTER_FACTOR0_M (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
#define ADC_FILTER_FACTOR0_V 0x00000007U
#define ADC_FILTER_FACTOR0_S 29
/** ADC_SAR1_PATT_TAB1_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x1c)
/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 15728640;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB1 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB1_M (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
#define ADC_SAR1_PATT_TAB1_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB1_S 0
/** ADC_SAR1_PATT_TAB2_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x20)
/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB2 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB2_M (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
#define ADC_SAR1_PATT_TAB2_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB2_S 0
/** ADC_SAR1_PATT_TAB3_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x24)
/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB3 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB3_M (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
#define ADC_SAR1_PATT_TAB3_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB3_S 0
/** ADC_SAR1_PATT_TAB4_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x28)
/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB4 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB4_M (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
#define ADC_SAR1_PATT_TAB4_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB4_S 0
/** ADC_SAR2_PATT_TAB1_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x2c)
/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 15728640;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB1 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB1_M (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
#define ADC_SAR2_PATT_TAB1_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB1_S 0
/** ADC_SAR2_PATT_TAB2_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x30)
/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB2 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB2_M (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
#define ADC_SAR2_PATT_TAB2_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB2_S 0
/** ADC_SAR2_PATT_TAB3_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x34)
/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB3 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB3_M (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
#define ADC_SAR2_PATT_TAB3_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB3_S 0
/** ADC_SAR2_PATT_TAB4_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x38)
/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB4 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB4_M (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
#define ADC_SAR2_PATT_TAB4_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB4_S 0
/** ADC_FILTER_CTRL0_REG register
* Register
*/
#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
* need_des
*/
#define ADC_FILTER_CHANNEL1 0x0000001FU
#define ADC_FILTER_CHANNEL1_M (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
#define ADC_FILTER_CHANNEL1_V 0x0000001FU
#define ADC_FILTER_CHANNEL1_S 14
/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
* apb_adc1_filter_factor
*/
#define ADC_FILTER_CHANNEL0 0x0000001FU
#define ADC_FILTER_CHANNEL0_M (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
#define ADC_FILTER_CHANNEL0_V 0x0000001FU
#define ADC_FILTER_CHANNEL0_S 19
/** ADC_FILTER_RESET : WT; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define ADC_FILTER_RESET (BIT(31))
#define ADC_FILTER_RESET_M (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
#define ADC_FILTER_RESET_V 0x00000001U
#define ADC_FILTER_RESET_S 31
/** ADC_SAR1_DATA_STATUS_REG register
* Register
*/
#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
/** ADC_APB_SARADC1_DATA : RO; bitpos: [21:0]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DATA 0x003FFFFFU
#define ADC_APB_SARADC1_DATA_M (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
#define ADC_APB_SARADC1_DATA_V 0x003FFFFFU
#define ADC_APB_SARADC1_DATA_S 0
/** ADC_SAR2_DATA_STATUS_REG register
* Register
*/
#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x44)
/** ADC_APB_SARADC2_DATA : RO; bitpos: [21:0]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DATA 0x003FFFFFU
#define ADC_APB_SARADC2_DATA_M (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
#define ADC_APB_SARADC2_DATA_V 0x003FFFFFU
#define ADC_APB_SARADC2_DATA_S 0
/** ADC_THRES0_HIGH_THRES_REG register
* Register
*/
#define ADC_THRES0_HIGH_THRES_REG (DR_REG_ADC_BASE + 0x48)
/** ADC_THRES0_HIGH : R/W; bitpos: [16:0]; default: 255;
* need_des
*/
#define ADC_THRES0_HIGH 0x0001FFFFU
#define ADC_THRES0_HIGH_M (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
#define ADC_THRES0_HIGH_V 0x0001FFFFU
#define ADC_THRES0_HIGH_S 0
/** ADC_THRES0_LOW_THRES_REG register
* Register
*/
#define ADC_THRES0_LOW_THRES_REG (DR_REG_ADC_BASE + 0x4c)
/** ADC_THRES0_LOW : R/W; bitpos: [16:0]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW 0x0001FFFFU
#define ADC_THRES0_LOW_M (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
#define ADC_THRES0_LOW_V 0x0001FFFFU
#define ADC_THRES0_LOW_S 0
/** ADC_THRES0_CTRL_REG register
* Register
*/
#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x50)
/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
#define ADC_THRES0_CHANNEL 0x0000001FU
#define ADC_THRES0_CHANNEL_M (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
#define ADC_THRES0_CHANNEL_V 0x0000001FU
#define ADC_THRES0_CHANNEL_S 0
/** ADC_THRES0_EN : R/W; bitpos: [5]; default: 0;
* need_des
*/
#define ADC_THRES0_EN (BIT(5))
#define ADC_THRES0_EN_M (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
#define ADC_THRES0_EN_V 0x00000001U
#define ADC_THRES0_EN_S 5
/** ADC_THRES1_HIGH_THRES_REG register
* Register
*/
#define ADC_THRES1_HIGH_THRES_REG (DR_REG_ADC_BASE + 0x54)
/** ADC_THRES1_HIGH : R/W; bitpos: [16:0]; default: 255;
* need_des
*/
#define ADC_THRES1_HIGH 0x0001FFFFU
#define ADC_THRES1_HIGH_M (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
#define ADC_THRES1_HIGH_V 0x0001FFFFU
#define ADC_THRES1_HIGH_S 0
/** ADC_THRES1_LOW_THRES_REG register
* Register
*/
#define ADC_THRES1_LOW_THRES_REG (DR_REG_ADC_BASE + 0x58)
/** ADC_THRES1_LOW : R/W; bitpos: [16:0]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW 0x0001FFFFU
#define ADC_THRES1_LOW_M (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
#define ADC_THRES1_LOW_V 0x0001FFFFU
#define ADC_THRES1_LOW_S 0
/** ADC_THRES1_CTRL_REG register
* Register
*/
#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x5c)
/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
#define ADC_THRES1_CHANNEL 0x0000001FU
#define ADC_THRES1_CHANNEL_M (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
#define ADC_THRES1_CHANNEL_V 0x0000001FU
#define ADC_THRES1_CHANNEL_S 0
/** ADC_THRES1_EN : R/W; bitpos: [5]; default: 0;
* need_des
*/
#define ADC_THRES1_EN (BIT(5))
#define ADC_THRES1_EN_M (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
#define ADC_THRES1_EN_V 0x00000001U
#define ADC_THRES1_EN_S 5
/** ADC_THRES_CTRL_REG register
* Register
*/
#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x60)
/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES_ALL_EN (BIT(27))
#define ADC_THRES_ALL_EN_M (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
#define ADC_THRES_ALL_EN_V 0x00000001U
#define ADC_THRES_ALL_EN_S 27
/** ADC_INT_ENA_REG register
* Register
*/
#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x64)
/** ADC_FIFO_OVERFLOW_INT_ENA : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define ADC_FIFO_OVERFLOW_INT_ENA (BIT(25))
#define ADC_FIFO_OVERFLOW_INT_ENA_M (ADC_FIFO_OVERFLOW_INT_ENA_V << ADC_FIFO_OVERFLOW_INT_ENA_S)
#define ADC_FIFO_OVERFLOW_INT_ENA_V 0x00000001U
#define ADC_FIFO_OVERFLOW_INT_ENA_S 25
/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_ENA (BIT(26))
#define ADC_THRES1_LOW_INT_ENA_M (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
#define ADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define ADC_THRES1_LOW_INT_ENA_S 26
/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_ENA (BIT(27))
#define ADC_THRES0_LOW_INT_ENA_M (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
#define ADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define ADC_THRES0_LOW_INT_ENA_S 27
/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_ENA (BIT(28))
#define ADC_THRES1_HIGH_INT_ENA_M (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
#define ADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define ADC_THRES1_HIGH_INT_ENA_S 28
/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_ENA (BIT(29))
#define ADC_THRES0_HIGH_INT_ENA_M (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
#define ADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define ADC_THRES0_HIGH_INT_ENA_S 29
/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_ENA (BIT(30))
#define ADC_SAR2_DONE_INT_ENA_M (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
#define ADC_SAR2_DONE_INT_ENA_V 0x00000001U
#define ADC_SAR2_DONE_INT_ENA_S 30
/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_ENA (BIT(31))
#define ADC_SAR1_DONE_INT_ENA_M (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
#define ADC_SAR1_DONE_INT_ENA_V 0x00000001U
#define ADC_SAR1_DONE_INT_ENA_S 31
/** ADC_INT_RAW_REG register
* Register
*/
#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x68)
/** ADC_FIFO_OVERFLOW_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
* need_des
*/
#define ADC_FIFO_OVERFLOW_INT_RAW (BIT(25))
#define ADC_FIFO_OVERFLOW_INT_RAW_M (ADC_FIFO_OVERFLOW_INT_RAW_V << ADC_FIFO_OVERFLOW_INT_RAW_S)
#define ADC_FIFO_OVERFLOW_INT_RAW_V 0x00000001U
#define ADC_FIFO_OVERFLOW_INT_RAW_S 25
/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_RAW (BIT(26))
#define ADC_THRES1_LOW_INT_RAW_M (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
#define ADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define ADC_THRES1_LOW_INT_RAW_S 26
/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_RAW (BIT(27))
#define ADC_THRES0_LOW_INT_RAW_M (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
#define ADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define ADC_THRES0_LOW_INT_RAW_S 27
/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_RAW (BIT(28))
#define ADC_THRES1_HIGH_INT_RAW_M (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
#define ADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define ADC_THRES1_HIGH_INT_RAW_S 28
/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_RAW (BIT(29))
#define ADC_THRES0_HIGH_INT_RAW_M (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
#define ADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define ADC_THRES0_HIGH_INT_RAW_S 29
/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_RAW (BIT(30))
#define ADC_SAR2_DONE_INT_RAW_M (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
#define ADC_SAR2_DONE_INT_RAW_V 0x00000001U
#define ADC_SAR2_DONE_INT_RAW_S 30
/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_RAW (BIT(31))
#define ADC_SAR1_DONE_INT_RAW_M (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
#define ADC_SAR1_DONE_INT_RAW_V 0x00000001U
#define ADC_SAR1_DONE_INT_RAW_S 31
/** ADC_INT_ST_REG register
* Register
*/
#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x6c)
/** ADC_FIFO_OVERFLOW_INT_ST : RO; bitpos: [25]; default: 0;
* need_des
*/
#define ADC_FIFO_OVERFLOW_INT_ST (BIT(25))
#define ADC_FIFO_OVERFLOW_INT_ST_M (ADC_FIFO_OVERFLOW_INT_ST_V << ADC_FIFO_OVERFLOW_INT_ST_S)
#define ADC_FIFO_OVERFLOW_INT_ST_V 0x00000001U
#define ADC_FIFO_OVERFLOW_INT_ST_S 25
/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_ST (BIT(26))
#define ADC_THRES1_LOW_INT_ST_M (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
#define ADC_THRES1_LOW_INT_ST_V 0x00000001U
#define ADC_THRES1_LOW_INT_ST_S 26
/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_ST (BIT(27))
#define ADC_THRES0_LOW_INT_ST_M (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
#define ADC_THRES0_LOW_INT_ST_V 0x00000001U
#define ADC_THRES0_LOW_INT_ST_S 27
/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_ST (BIT(28))
#define ADC_THRES1_HIGH_INT_ST_M (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
#define ADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define ADC_THRES1_HIGH_INT_ST_S 28
/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_ST (BIT(29))
#define ADC_THRES0_HIGH_INT_ST_M (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
#define ADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define ADC_THRES0_HIGH_INT_ST_S 29
/** ADC_SAR2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_ST (BIT(30))
#define ADC_SAR2_DONE_INT_ST_M (ADC_SAR2_DONE_INT_ST_V << ADC_SAR2_DONE_INT_ST_S)
#define ADC_SAR2_DONE_INT_ST_V 0x00000001U
#define ADC_SAR2_DONE_INT_ST_S 30
/** ADC_SAR1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_ST (BIT(31))
#define ADC_SAR1_DONE_INT_ST_M (ADC_SAR1_DONE_INT_ST_V << ADC_SAR1_DONE_INT_ST_S)
#define ADC_SAR1_DONE_INT_ST_V 0x00000001U
#define ADC_SAR1_DONE_INT_ST_S 31
/** ADC_INT_CLR_REG register
* Register
*/
#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x70)
/** ADC_FIFO_OVERFLOW_INT_CLR : WT; bitpos: [25]; default: 0;
* need_des
*/
#define ADC_FIFO_OVERFLOW_INT_CLR (BIT(25))
#define ADC_FIFO_OVERFLOW_INT_CLR_M (ADC_FIFO_OVERFLOW_INT_CLR_V << ADC_FIFO_OVERFLOW_INT_CLR_S)
#define ADC_FIFO_OVERFLOW_INT_CLR_V 0x00000001U
#define ADC_FIFO_OVERFLOW_INT_CLR_S 25
/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_CLR (BIT(26))
#define ADC_THRES1_LOW_INT_CLR_M (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
#define ADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define ADC_THRES1_LOW_INT_CLR_S 26
/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_CLR (BIT(27))
#define ADC_THRES0_LOW_INT_CLR_M (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
#define ADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define ADC_THRES0_LOW_INT_CLR_S 27
/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_CLR (BIT(28))
#define ADC_THRES1_HIGH_INT_CLR_M (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
#define ADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define ADC_THRES1_HIGH_INT_CLR_S 28
/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_CLR (BIT(29))
#define ADC_THRES0_HIGH_INT_CLR_M (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
#define ADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define ADC_THRES0_HIGH_INT_CLR_S 29
/** ADC_SAR2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_CLR (BIT(30))
#define ADC_SAR2_DONE_INT_CLR_M (ADC_SAR2_DONE_INT_CLR_V << ADC_SAR2_DONE_INT_CLR_S)
#define ADC_SAR2_DONE_INT_CLR_V 0x00000001U
#define ADC_SAR2_DONE_INT_CLR_S 30
/** ADC_SAR1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_CLR (BIT(31))
#define ADC_SAR1_DONE_INT_CLR_M (ADC_SAR1_DONE_INT_CLR_V << ADC_SAR1_DONE_INT_CLR_S)
#define ADC_SAR1_DONE_INT_CLR_V 0x00000001U
#define ADC_SAR1_DONE_INT_CLR_S 31
/** ADC_DMA_CONF_REG register
* Register
*/
#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x74)
/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define ADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define ADC_APB_ADC_EOF_NUM_M (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
#define ADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define ADC_APB_ADC_EOF_NUM_S 0
/** ADC_DMA_EOF_NUM_CLR : WT; bitpos: [16]; default: 0;
* clear eof cnt
*/
#define ADC_DMA_EOF_NUM_CLR (BIT(16))
#define ADC_DMA_EOF_NUM_CLR_M (ADC_DMA_EOF_NUM_CLR_V << ADC_DMA_EOF_NUM_CLR_S)
#define ADC_DMA_EOF_NUM_CLR_V 0x00000001U
#define ADC_DMA_EOF_NUM_CLR_S 16
/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define ADC_APB_ADC_TRANS (BIT(31))
#define ADC_APB_ADC_TRANS_M (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
#define ADC_APB_ADC_TRANS_V 0x00000001U
#define ADC_APB_ADC_TRANS_S 31
/** ADC_REF_CONTROL_REG register
* Register
*/
#define ADC_REF_CONTROL_REG (DR_REG_ADC_BASE + 0x78)
/** ADC_RTC_REF_DELAY : R/W; bitpos: [29]; default: 0;
* control the refgen short vdd
*/
#define ADC_RTC_REF_DELAY (BIT(29))
#define ADC_RTC_REF_DELAY_M (ADC_RTC_REF_DELAY_V << ADC_RTC_REF_DELAY_S)
#define ADC_RTC_REF_DELAY_V 0x00000001U
#define ADC_RTC_REF_DELAY_S 29
/** ADC_RTC_PRE_CHARGE : R/W; bitpos: [30]; default: 0;
* control the refgen module pre charge
*/
#define ADC_RTC_PRE_CHARGE (BIT(30))
#define ADC_RTC_PRE_CHARGE_M (ADC_RTC_PRE_CHARGE_V << ADC_RTC_PRE_CHARGE_S)
#define ADC_RTC_PRE_CHARGE_V 0x00000001U
#define ADC_RTC_PRE_CHARGE_S 30
/** ADC_RTC_XPD_REFGEN : R/W; bitpos: [31]; default: 0;
* control the refgen module power up
*/
#define ADC_RTC_XPD_REFGEN (BIT(31))
#define ADC_RTC_XPD_REFGEN_M (ADC_RTC_XPD_REFGEN_V << ADC_RTC_XPD_REFGEN_S)
#define ADC_RTC_XPD_REFGEN_V 0x00000001U
#define ADC_RTC_XPD_REFGEN_S 31
/** ADC_RND_ECO_LOW_REG register
* Register
*/
#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x7c)
/** ADC_ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* rnd eco low
*/
#define ADC_ADC_RND_ECO_LOW 0xFFFFFFFFU
#define ADC_ADC_RND_ECO_LOW_M (ADC_ADC_RND_ECO_LOW_V << ADC_ADC_RND_ECO_LOW_S)
#define ADC_ADC_RND_ECO_LOW_V 0xFFFFFFFFU
#define ADC_ADC_RND_ECO_LOW_S 0
/** ADC_RND_ECO_HIGH_REG register
* Register
*/
#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x80)
/** ADC_ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* rnd eco high
*/
#define ADC_ADC_RND_ECO_HIGH 0xFFFFFFFFU
#define ADC_ADC_RND_ECO_HIGH_M (ADC_ADC_RND_ECO_HIGH_V << ADC_ADC_RND_ECO_HIGH_S)
#define ADC_ADC_RND_ECO_HIGH_V 0xFFFFFFFFU
#define ADC_ADC_RND_ECO_HIGH_S 0
/** ADC_RND_ECO_CS_REG register
* Register
*/
#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x84)
/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_RND_ECO_EN (BIT(0))
#define ADC_RND_ECO_EN_M (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
#define ADC_RND_ECO_EN_V 0x00000001U
#define ADC_RND_ECO_EN_S 0
/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_RND_ECO_RESULT (BIT(1))
#define ADC_RND_ECO_RESULT_M (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
#define ADC_RND_ECO_RESULT_V 0x00000001U
#define ADC_RND_ECO_RESULT_S 1
/** ADC_CTRL_DATE_REG register
* Register
*/
#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 38830624;
* need_des
*/
#define ADC_CTRL_DATE 0x7FFFFFFFU
#define ADC_CTRL_DATE_M (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
#define ADC_CTRL_DATE_V 0x7FFFFFFFU
#define ADC_CTRL_DATE_S 0
/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_CLK_EN (BIT(31))
#define ADC_CLK_EN_M (ADC_CLK_EN_V << ADC_CLK_EN_S)
#define ADC_CLK_EN_V 0x00000001U
#define ADC_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

721
components/soc/esp32s31/register/soc/adc_struct.h Normal file
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@@ -0,0 +1,721 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of ctrl0 register
* Register
*/
typedef union {
struct {
/** sar1_trigger_stop : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t sar1_trigger_stop:1;
/** sar1_trigger_start : WT; bitpos: [1]; default: 0;
* need_des
*/
uint32_t sar1_trigger_start:1;
/** sar1_trigger_mode : R/W; bitpos: [3:2]; default: 0;
* SAR clock divider
*/
uint32_t sar1_trigger_mode:2;
uint32_t reserved_4:10;
/** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t sar1_patt_len:4;
uint32_t reserved_18:4;
/** sar1_patt_p_clear : WT; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t sar1_patt_p_clear:1;
/** sar1_patt_type : R/W; bitpos: [23]; default: 0;
* 1: select meas start as table update 0:select mead done as table update
*/
uint32_t sar1_patt_type:1;
/** sar1_clk_pos_sel : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
uint32_t sar1_clk_pos_sel:1;
/** sar1_continue_mode_en : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
uint32_t sar1_continue_mode_en:1;
/** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
uint32_t xpd_sar1_force:2;
uint32_t reserved_28:4;
};
uint32_t val;
} adc_ctrl0_reg_t;
/** Type of ctrl1 register
* Register
*/
typedef union {
struct {
/** sar2_trigger_stop : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t sar2_trigger_stop:1;
/** sar2_trigger_start : WT; bitpos: [1]; default: 0;
* need_des
*/
uint32_t sar2_trigger_start:1;
/** sar2_trigger_mode : R/W; bitpos: [3:2]; default: 0;
* SAR clock divider
*/
uint32_t sar2_trigger_mode:2;
uint32_t reserved_4:10;
/** sar2_patt_len : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t sar2_patt_len:4;
uint32_t reserved_18:4;
/** sar2_patt_p_clear : WT; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t sar2_patt_p_clear:1;
/** sar2_patt_type : R/W; bitpos: [23]; default: 0;
* 1: select meas start as table update 0:select mead done as table update
*/
uint32_t sar2_patt_type:1;
/** sar2_clk_pos_sel : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
uint32_t sar2_clk_pos_sel:1;
/** sar2_continue_mode_en : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
uint32_t sar2_continue_mode_en:1;
/** xpd_sar2_force : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
uint32_t xpd_sar2_force:2;
uint32_t reserved_28:4;
};
uint32_t val;
} adc_ctrl1_reg_t;
/** Type of ctrl2 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t timer_target:12;
/** timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} adc_ctrl2_reg_t;
/** Type of filter_ctrl1 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* need_des
*/
uint32_t filter_factor1:3;
/** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
uint32_t filter_factor0:3;
};
uint32_t val;
} adc_filter_ctrl1_reg_t;
/** Type of sar1_patt_tab1 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab1 : R/W; bitpos: [23:0]; default: 15728640;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab1_reg_t;
/** Type of sar1_patt_tab2 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab2_reg_t;
/** Type of sar1_patt_tab3 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab3:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab3_reg_t;
/** Type of sar1_patt_tab4 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab4:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab4_reg_t;
/** Type of sar2_patt_tab1 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab1 : R/W; bitpos: [23:0]; default: 15728640;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab1_reg_t;
/** Type of sar2_patt_tab2 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab2_reg_t;
/** Type of sar2_patt_tab3 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab3:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab3_reg_t;
/** Type of sar2_patt_tab4 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab4:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab4_reg_t;
/** Type of filter_ctrl0 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
* need_des
*/
uint32_t filter_channel1:5;
/** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
* apb_adc1_filter_factor
*/
uint32_t filter_channel0:5;
uint32_t reserved_24:7;
/** filter_reset : WT; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t filter_reset:1;
};
uint32_t val;
} adc_filter_ctrl0_reg_t;
/** Type of sar1_data_status register
* Register
*/
typedef union {
struct {
/** apb_saradc1_data : RO; bitpos: [21:0]; default: 0;
* need_des
*/
uint32_t apb_saradc1_data:22;
uint32_t reserved_22:10;
};
uint32_t val;
} adc_sar1_data_status_reg_t;
/** Type of sar2_data_status register
* Register
*/
typedef union {
struct {
/** apb_saradc2_data : RO; bitpos: [21:0]; default: 0;
* need_des
*/
uint32_t apb_saradc2_data:22;
uint32_t reserved_22:10;
};
uint32_t val;
} adc_sar2_data_status_reg_t;
/** Type of thres0_high_thres register
* Register
*/
typedef union {
struct {
/** thres0_high : R/W; bitpos: [16:0]; default: 255;
* need_des
*/
uint32_t thres0_high:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_thres0_high_thres_reg_t;
/** Type of thres0_low_thres register
* Register
*/
typedef union {
struct {
/** thres0_low : R/W; bitpos: [16:0]; default: 0;
* need_des
*/
uint32_t thres0_low:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_thres0_low_thres_reg_t;
/** Type of thres0_ctrl register
* Register
*/
typedef union {
struct {
/** thres0_channel : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
uint32_t thres0_channel:5;
/** thres0_en : R/W; bitpos: [5]; default: 0;
* need_des
*/
uint32_t thres0_en:1;
uint32_t reserved_6:26;
};
uint32_t val;
} adc_thres0_ctrl_reg_t;
/** Type of thres1_high_thres register
* Register
*/
typedef union {
struct {
/** thres1_high : R/W; bitpos: [16:0]; default: 255;
* need_des
*/
uint32_t thres1_high:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_thres1_high_thres_reg_t;
/** Type of thres1_low_thres register
* Register
*/
typedef union {
struct {
/** thres1_low : R/W; bitpos: [16:0]; default: 0;
* need_des
*/
uint32_t thres1_low:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_thres1_low_thres_reg_t;
/** Type of thres1_ctrl register
* Register
*/
typedef union {
struct {
/** thres1_channel : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
uint32_t thres1_channel:5;
/** thres1_en : R/W; bitpos: [5]; default: 0;
* need_des
*/
uint32_t thres1_en:1;
uint32_t reserved_6:26;
};
uint32_t val;
} adc_thres1_ctrl_reg_t;
/** Type of thres_ctrl register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** thres_all_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres_all_en:1;
uint32_t reserved_28:4;
};
uint32_t val;
} adc_thres_ctrl_reg_t;
/** Type of int_ena register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** fifo_overflow_int_ena : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t fifo_overflow_int_ena:1;
/** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_ena:1;
/** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_ena:1;
/** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_ena:1;
/** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_ena:1;
/** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_ena:1;
/** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_ena:1;
};
uint32_t val;
} adc_int_ena_reg_t;
/** Type of int_raw register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** fifo_overflow_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
* need_des
*/
uint32_t fifo_overflow_int_raw:1;
/** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_raw:1;
/** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_raw:1;
/** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_raw:1;
/** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_raw:1;
/** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_raw:1;
/** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_raw:1;
};
uint32_t val;
} adc_int_raw_reg_t;
/** Type of int_st register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** fifo_overflow_int_st : RO; bitpos: [25]; default: 0;
* need_des
*/
uint32_t fifo_overflow_int_st:1;
/** thres1_low_int_st : RO; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_st:1;
/** thres0_low_int_st : RO; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_st:1;
/** thres1_high_int_st : RO; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_st:1;
/** thres0_high_int_st : RO; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_st:1;
/** sar2_done_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_st:1;
/** sar1_done_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_st:1;
};
uint32_t val;
} adc_int_st_reg_t;
/** Type of int_clr register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** fifo_overflow_int_clr : WT; bitpos: [25]; default: 0;
* need_des
*/
uint32_t fifo_overflow_int_clr:1;
/** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_clr:1;
/** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_clr:1;
/** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_clr:1;
/** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_clr:1;
/** sar2_done_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_clr:1;
/** sar1_done_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_clr:1;
};
uint32_t val;
} adc_int_clr_reg_t;
/** Type of dma_conf register
* Register
*/
typedef union {
struct {
/** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t apb_adc_eof_num:16;
/** dma_eof_num_clr : WT; bitpos: [16]; default: 0;
* clear eof cnt
*/
uint32_t dma_eof_num_clr:1;
uint32_t reserved_17:14;
/** apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t apb_adc_trans:1;
};
uint32_t val;
} adc_dma_conf_reg_t;
/** Type of ref_control register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** rtc_ref_delay : R/W; bitpos: [29]; default: 0;
* control the refgen short vdd
*/
uint32_t rtc_ref_delay:1;
/** rtc_pre_charge : R/W; bitpos: [30]; default: 0;
* control the refgen module pre charge
*/
uint32_t rtc_pre_charge:1;
/** rtc_xpd_refgen : R/W; bitpos: [31]; default: 0;
* control the refgen module power up
*/
uint32_t rtc_xpd_refgen:1;
};
uint32_t val;
} adc_ref_control_reg_t;
/** Type of rnd_eco_low register
* Register
*/
typedef union {
struct {
/** adc_rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
* rnd eco low
*/
uint32_t adc_rnd_eco_low:32;
};
uint32_t val;
} adc_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* Register
*/
typedef union {
struct {
/** adc_rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* rnd eco high
*/
uint32_t adc_rnd_eco_high:32;
};
uint32_t val;
} adc_rnd_eco_high_reg_t;
/** Type of rnd_eco_cs register
* Register
*/
typedef union {
struct {
/** rnd_eco_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t rnd_eco_en:1;
/** rnd_eco_result : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t rnd_eco_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} adc_rnd_eco_cs_reg_t;
/** Type of ctrl_date register
* Register
*/
typedef union {
struct {
/** ctrl_date : R/W; bitpos: [30:0]; default: 38830624;
* need_des
*/
uint32_t ctrl_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} adc_ctrl_date_reg_t;
typedef struct {
volatile adc_ctrl0_reg_t ctrl0;
volatile adc_ctrl1_reg_t ctrl1;
volatile adc_ctrl2_reg_t ctrl2;
volatile adc_filter_ctrl1_reg_t filter_ctrl1;
uint32_t reserved_010[3];
volatile adc_sar1_patt_tab1_reg_t sar1_patt_tab1;
volatile adc_sar1_patt_tab2_reg_t sar1_patt_tab2;
volatile adc_sar1_patt_tab3_reg_t sar1_patt_tab3;
volatile adc_sar1_patt_tab4_reg_t sar1_patt_tab4;
volatile adc_sar2_patt_tab1_reg_t sar2_patt_tab1;
volatile adc_sar2_patt_tab2_reg_t sar2_patt_tab2;
volatile adc_sar2_patt_tab3_reg_t sar2_patt_tab3;
volatile adc_sar2_patt_tab4_reg_t sar2_patt_tab4;
volatile adc_filter_ctrl0_reg_t filter_ctrl0;
volatile adc_sar1_data_status_reg_t sar1_data_status;
volatile adc_sar2_data_status_reg_t sar2_data_status;
volatile adc_thres0_high_thres_reg_t thres0_high_thres;
volatile adc_thres0_low_thres_reg_t thres0_low_thres;
volatile adc_thres0_ctrl_reg_t thres0_ctrl;
volatile adc_thres1_high_thres_reg_t thres1_high_thres;
volatile adc_thres1_low_thres_reg_t thres1_low_thres;
volatile adc_thres1_ctrl_reg_t thres1_ctrl;
volatile adc_thres_ctrl_reg_t thres_ctrl;
volatile adc_int_ena_reg_t int_ena;
volatile adc_int_raw_reg_t int_raw;
volatile adc_int_st_reg_t int_st;
volatile adc_int_clr_reg_t int_clr;
volatile adc_dma_conf_reg_t dma_conf;
volatile adc_ref_control_reg_t ref_control;
volatile adc_rnd_eco_low_reg_t rnd_eco_low;
volatile adc_rnd_eco_high_reg_t rnd_eco_high;
volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
uint32_t reserved_088[221];
volatile adc_ctrl_date_reg_t ctrl_date;
} adc_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

484
components/soc/esp32s31/register/soc/aes_reg.h Normal file
View File

@@ -0,0 +1,484 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* AES key data register 0
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* AES key data register 1
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_2_REG register
* AES key data register 2
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_3_REG register
* AES key data register 3
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_4_REG register
* AES key data register 4
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_5_REG register
* AES key data register 5
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_6_REG register
* AES key data register 6
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_7_REG register
* AES key data register 7
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_TEXT_IN_0_REG register
* Source text data register 0
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* Source text data register 1
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_2_REG register
* Source text data register 2
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_3_REG register
* Source text data register 3
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_OUT_0_REG register
* Result text data register 0
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* Result text data register 1
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_2_REG register
* Result text data register 2
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_3_REG register
* Result text data register 3
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_MODE_REG register
* Defines key length and encryption / decryption
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption
* 1: AES-192 encryption
* 2: AES-256 encryption
* 3: Reserved
* 4: AES-128 decryption
* 5: AES-192 decryption
* 6: AES-256 decryption
* 7: Reserved
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_USE_HARDWARE_KEY : R/W; bitpos: [4]; default: 0;
* Configures the AES accelerator use software key or hardware key.
* 0: Software key.
* 1: Hardware key.
*/
#define AES_USE_HARDWARE_KEY (BIT(4))
#define AES_USE_HARDWARE_KEY_M (AES_USE_HARDWARE_KEY_V << AES_USE_HARDWARE_KEY_S)
#define AES_USE_HARDWARE_KEY_V 0x00000001U
#define AES_USE_HARDWARE_KEY_S 4
/** AES_TRIGGER_REG register
* Operation start controlling register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation.
* 0: No effect
* 1: Start
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* Operation status register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator.
* In Typical AES working mode:
* 0: IDLE
* 1: WORK
* 2: No effect
* 3: No effect
* In DMA-AES working mode:
* 0: IDLE
* 1: WORK
* 2: DONE
* 3: No effect
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* Selects the working mode of the AES accelerator
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator.
* 0: Typical AES
* 1: DMA-AES
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* Defines the block cipher mode
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode.
* 0: ECB (Electronic Code Block)
* 1: CBC (Cipher Block Chaining)
* 2: OFB (Output FeedBack)
* 3: CTR (Counter)
* 4: CFB8 (8-bit Cipher FeedBack)
* 5: CFB128 (128-bit Cipher FeedBack)
* 6: GCM
* 7: Reserved
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* Block number configuration register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section . "
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation.
* 0: INC_32
* 1: INC_128
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_INT_CLEAR_REG register
* DMA-AES interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt.
* 0: No effect
* 1: Clear
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* DMA-AES interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.
* 0: Disable
* 1: Enable
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [27:0]; default: 38826624;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x0FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x0FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* Operation exit controlling register
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation.
* 0: No effect
* 1: Exit
* Only valid for DMA-AES operation.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
/** AES_RX_RESET_REG register
* AES-DMA reset rx-fifo register
*/
#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
#define AES_RX_RESET (BIT(0))
#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S)
#define AES_RX_RESET_V 0x00000001U
#define AES_RX_RESET_S 0
/** AES_TX_RESET_REG register
* AES-DMA reset tx-fifo register
*/
#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
#define AES_TX_RESET (BIT(0))
#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S)
#define AES_TX_RESET_V 0x00000001U
#define AES_TX_RESET_S 0
/** AES_PSEUDO_REG register
* AES PSEUDO function configure register
*/
#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
#define AES_PSEUDO_EN (BIT(0))
#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
#define AES_PSEUDO_EN_V 0x00000001U
#define AES_PSEUDO_EN_S 0
/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
#define AES_PSEUDO_BASE 0x0000000FU
#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
#define AES_PSEUDO_BASE_V 0x0000000FU
#define AES_PSEUDO_BASE_S 1
/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
#define AES_PSEUDO_INC 0x00000003U
#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
#define AES_PSEUDO_INC_V 0x00000003U
#define AES_PSEUDO_INC_S 5
/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
#define AES_PSEUDO_RNG_CNT 0x00000007U
#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
#define AES_PSEUDO_RNG_CNT_V 0x00000007U
#define AES_PSEUDO_RNG_CNT_S 7
/** AES_FREE_REG register
* AES free state register
*/
#define AES_FREE_REG (DR_REG_AES_BASE + 0xd4)
/** AES_FREE : R/W; bitpos: [0]; default: 1;
* 0: AES is non-free;
* 1:AES is free.
*/
#define AES_FREE (BIT(0))
#define AES_FREE_M (AES_FREE_V << AES_FREE_S)
#define AES_FREE_V 0x00000001U
#define AES_FREE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Key Registers */
/** Type of key_n register
* AES key data register n
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_n_reg_t;
/** Group: TEXT_IN Registers */
/** Type of text_in_n register
* Source text data register n
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_n_reg_t;
/** Group: TEXT_OUT Registers */
/** Type of text_out_n register
* Result text data register n
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_n_reg_t;
/** Group: Control / Configuration Registers */
/** Type of mode register
* Defines key length and encryption / decryption
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption
* 1: AES-192 encryption
* 2: AES-256 encryption
* 3: Reserved
* 4: AES-128 decryption
* 5: AES-192 decryption
* 6: AES-256 decryption
* 7: Reserved
*/
uint32_t mode:3;
uint32_t reserved_3:1;
/** use_hardware_key : R/W; bitpos: [4]; default: 0;
* Configures the AES accelerator use software key or hardware key.
* 0: Software key.
* 1: Hardware key.
*/
uint32_t use_hardware_key:1;
uint32_t reserved_5:27;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of trigger register
* Operation start controlling register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation.
* 0: No effect
* 1: Start
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of dma_enable register
* Selects the working mode of the AES accelerator
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator.
* 0: Typical AES
* 1: DMA-AES
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of block_mode register
* Defines the block cipher mode
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode.
* 0: ECB (Electronic Code Block)
* 1: CBC (Cipher Block Chaining)
* 2: OFB (Output FeedBack)
* 3: CTR (Counter)
* 4: CFB8 (8-bit Cipher FeedBack)
* 5: CFB128 (128-bit Cipher FeedBack)
* 6: GCM
* 7: Reserved
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* Block number configuration register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section . "
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation.
* 0: INC_32
* 1: INC_128
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Type of dma_exit register
* Operation exit controlling register
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation.
* 0: No effect
* 1: Exit
* Only valid for DMA-AES operation.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Type of rx_reset register
* AES-DMA reset rx-fifo register
*/
typedef union {
struct {
/** rx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
uint32_t rx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_rx_reset_reg_t;
/** Type of tx_reset register
* AES-DMA reset tx-fifo register
*/
typedef union {
struct {
/** tx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
uint32_t tx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_tx_reset_reg_t;
/** Group: Configuration register */
/** Type of pseudo register
* AES PSEUDO function configure register
*/
typedef union {
struct {
/** pseudo_en : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
uint32_t pseudo_en:1;
/** pseudo_base : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
uint32_t pseudo_base:4;
/** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
uint32_t pseudo_inc:2;
/** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
uint32_t pseudo_rng_cnt:3;
uint32_t reserved_10:22;
};
uint32_t val;
} aes_pseudo_reg_t;
/** Group: Status Register */
/** Type of state register
* Operation status register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator.
* In Typical AES working mode:
* 0: IDLE
* 1: WORK
* 2: No effect
* 3: No effect
* In DMA-AES working mode:
* 0: IDLE
* 1: WORK
* 2: DONE
* 3: No effect
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Type of free register
* AES free state register
*/
typedef union {
struct {
/** free : R/W; bitpos: [0]; default: 1;
* 0: AES is non-free;
* 1:AES is free.
*/
uint32_t free:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_free_reg_t;
/** Group: memory type */
/** Group: Interrupt Registers */
/** Type of int_clear register
* DMA-AES interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt.
* 0: No effect
* 1: Clear
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* DMA-AES interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 38826624;
* This bits stores the version information of AES.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} aes_date_reg_t;
typedef struct {
volatile aes_key_n_reg_t key_n[8];
volatile aes_text_in_n_reg_t text_in_n[4];
volatile aes_text_out_n_reg_t text_out_n[4];
volatile aes_mode_reg_t mode;
uint32_t reserved_044;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
uint32_t reserved_0a0[3];
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
uint32_t reserved_0bc;
volatile aes_rx_reset_reg_t rx_reset;
volatile aes_tx_reset_reg_t tx_reset;
uint32_t reserved_0c8[2];
volatile aes_pseudo_reg_t pseudo;
volatile aes_free_reg_t free;
} aes_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xd8, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASRC_CHNL0_CFG0_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG0_REG (DR_REG_ASRC_BASE + 0x0)
/** ASRC_CHNL0_RS2_STG1_BYPASS : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel0.
*/
#define ASRC_CHNL0_RS2_STG1_BYPASS (BIT(0))
#define ASRC_CHNL0_RS2_STG1_BYPASS_M (ASRC_CHNL0_RS2_STG1_BYPASS_V << ASRC_CHNL0_RS2_STG1_BYPASS_S)
#define ASRC_CHNL0_RS2_STG1_BYPASS_V 0x00000001U
#define ASRC_CHNL0_RS2_STG1_BYPASS_S 0
/** ASRC_CHNL0_RS2_STG0_BYPASS : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel0.
*/
#define ASRC_CHNL0_RS2_STG0_BYPASS (BIT(1))
#define ASRC_CHNL0_RS2_STG0_BYPASS_M (ASRC_CHNL0_RS2_STG0_BYPASS_V << ASRC_CHNL0_RS2_STG0_BYPASS_S)
#define ASRC_CHNL0_RS2_STG0_BYPASS_V 0x00000001U
#define ASRC_CHNL0_RS2_STG0_BYPASS_S 1
/** ASRC_CHNL0_FRAC_BYPASS : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel0.
*/
#define ASRC_CHNL0_FRAC_BYPASS (BIT(2))
#define ASRC_CHNL0_FRAC_BYPASS_M (ASRC_CHNL0_FRAC_BYPASS_V << ASRC_CHNL0_FRAC_BYPASS_S)
#define ASRC_CHNL0_FRAC_BYPASS_V 0x00000001U
#define ASRC_CHNL0_FRAC_BYPASS_S 2
/** ASRC_CHNL0_RS2_STG1_MODE : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
#define ASRC_CHNL0_RS2_STG1_MODE (BIT(3))
#define ASRC_CHNL0_RS2_STG1_MODE_M (ASRC_CHNL0_RS2_STG1_MODE_V << ASRC_CHNL0_RS2_STG1_MODE_S)
#define ASRC_CHNL0_RS2_STG1_MODE_V 0x00000001U
#define ASRC_CHNL0_RS2_STG1_MODE_S 3
/** ASRC_CHNL0_RS2_STG0_MODE : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
#define ASRC_CHNL0_RS2_STG0_MODE (BIT(4))
#define ASRC_CHNL0_RS2_STG0_MODE_M (ASRC_CHNL0_RS2_STG0_MODE_V << ASRC_CHNL0_RS2_STG0_MODE_S)
#define ASRC_CHNL0_RS2_STG0_MODE_V 0x00000001U
#define ASRC_CHNL0_RS2_STG0_MODE_S 4
/** ASRC_CHNL0_FRAC_AHEAD : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel0, it should
* be 1 when input frequency is higher the output.
*/
#define ASRC_CHNL0_FRAC_AHEAD (BIT(5))
#define ASRC_CHNL0_FRAC_AHEAD_M (ASRC_CHNL0_FRAC_AHEAD_V << ASRC_CHNL0_FRAC_AHEAD_S)
#define ASRC_CHNL0_FRAC_AHEAD_V 0x00000001U
#define ASRC_CHNL0_FRAC_AHEAD_S 5
/** ASRC_CHNL0_MODE : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
#define ASRC_CHNL0_MODE 0x00000003U
#define ASRC_CHNL0_MODE_M (ASRC_CHNL0_MODE_V << ASRC_CHNL0_MODE_S)
#define ASRC_CHNL0_MODE_V 0x00000003U
#define ASRC_CHNL0_MODE_S 7
/** ASRC_CHNL0_SEL : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
#define ASRC_CHNL0_SEL (BIT(9))
#define ASRC_CHNL0_SEL_M (ASRC_CHNL0_SEL_V << ASRC_CHNL0_SEL_S)
#define ASRC_CHNL0_SEL_V 0x00000001U
#define ASRC_CHNL0_SEL_S 9
/** ASRC_CHNL0_CFG1_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG1_REG (DR_REG_ASRC_BASE + 0x4)
/** ASRC_CHNL0_FRAC_M : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
#define ASRC_CHNL0_FRAC_M 0x000003FFU
#define ASRC_CHNL0_FRAC_M_M (ASRC_CHNL0_FRAC_M_V << ASRC_CHNL0_FRAC_M_S)
#define ASRC_CHNL0_FRAC_M_V 0x000003FFU
#define ASRC_CHNL0_FRAC_M_S 0
/** ASRC_CHNL0_FRAC_L : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
#define ASRC_CHNL0_FRAC_L 0x000003FFU
#define ASRC_CHNL0_FRAC_L_M (ASRC_CHNL0_FRAC_L_V << ASRC_CHNL0_FRAC_L_S)
#define ASRC_CHNL0_FRAC_L_V 0x000003FFU
#define ASRC_CHNL0_FRAC_L_S 10
/** ASRC_CHNL0_CFG2_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG2_REG (DR_REG_ASRC_BASE + 0x8)
/** ASRC_CHNL0_FRAC_RECIPL : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel0.
*/
#define ASRC_CHNL0_FRAC_RECIPL 0x000FFFFFU
#define ASRC_CHNL0_FRAC_RECIPL_M (ASRC_CHNL0_FRAC_RECIPL_V << ASRC_CHNL0_FRAC_RECIPL_S)
#define ASRC_CHNL0_FRAC_RECIPL_V 0x000FFFFFU
#define ASRC_CHNL0_FRAC_RECIPL_S 0
/** ASRC_CHNL0_CFG3_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG3_REG (DR_REG_ASRC_BASE + 0xc)
/** ASRC_CHNL0_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel0.
*/
#define ASRC_CHNL0_RESET (BIT(0))
#define ASRC_CHNL0_RESET_M (ASRC_CHNL0_RESET_V << ASRC_CHNL0_RESET_S)
#define ASRC_CHNL0_RESET_V 0x00000001U
#define ASRC_CHNL0_RESET_S 0
/** ASRC_CHNL0_CFG4_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG4_REG (DR_REG_ASRC_BASE + 0x10)
/** ASRC_CHNL0_START : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel0.
*/
#define ASRC_CHNL0_START (BIT(0))
#define ASRC_CHNL0_START_M (ASRC_CHNL0_START_V << ASRC_CHNL0_START_S)
#define ASRC_CHNL0_START_V 0x00000001U
#define ASRC_CHNL0_START_S 0
/** ASRC_CHNL0_CFG5_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG5_REG (DR_REG_ASRC_BASE + 0x14)
/** ASRC_CHNL0_IN_CNT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
#define ASRC_CHNL0_IN_CNT_ENA (BIT(0))
#define ASRC_CHNL0_IN_CNT_ENA_M (ASRC_CHNL0_IN_CNT_ENA_V << ASRC_CHNL0_IN_CNT_ENA_S)
#define ASRC_CHNL0_IN_CNT_ENA_V 0x00000001U
#define ASRC_CHNL0_IN_CNT_ENA_S 0
/** ASRC_CHNL0_IN_CNT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
#define ASRC_CHNL0_IN_CNT_CLR (BIT(1))
#define ASRC_CHNL0_IN_CNT_CLR_M (ASRC_CHNL0_IN_CNT_CLR_V << ASRC_CHNL0_IN_CNT_CLR_S)
#define ASRC_CHNL0_IN_CNT_CLR_V 0x00000001U
#define ASRC_CHNL0_IN_CNT_CLR_S 1
/** ASRC_CHNL0_IN_LEN : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data from the DMA
*/
#define ASRC_CHNL0_IN_LEN 0x00FFFFFFU
#define ASRC_CHNL0_IN_LEN_M (ASRC_CHNL0_IN_LEN_V << ASRC_CHNL0_IN_LEN_S)
#define ASRC_CHNL0_IN_LEN_V 0x00FFFFFFU
#define ASRC_CHNL0_IN_LEN_S 8
/** ASRC_CHNL0_CFG6_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_CFG6_REG (DR_REG_ASRC_BASE + 0x18)
/** ASRC_CHNL0_OUT_EOF_GEN_MODE : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
#define ASRC_CHNL0_OUT_EOF_GEN_MODE 0x00000003U
#define ASRC_CHNL0_OUT_EOF_GEN_MODE_M (ASRC_CHNL0_OUT_EOF_GEN_MODE_V << ASRC_CHNL0_OUT_EOF_GEN_MODE_S)
#define ASRC_CHNL0_OUT_EOF_GEN_MODE_V 0x00000003U
#define ASRC_CHNL0_OUT_EOF_GEN_MODE_S 0
/** ASRC_CHNL0_OUT_CNT_ENA : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
#define ASRC_CHNL0_OUT_CNT_ENA (BIT(2))
#define ASRC_CHNL0_OUT_CNT_ENA_M (ASRC_CHNL0_OUT_CNT_ENA_V << ASRC_CHNL0_OUT_CNT_ENA_S)
#define ASRC_CHNL0_OUT_CNT_ENA_V 0x00000001U
#define ASRC_CHNL0_OUT_CNT_ENA_S 2
/** ASRC_CHNL0_OUT_CNT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
#define ASRC_CHNL0_OUT_CNT_CLR (BIT(3))
#define ASRC_CHNL0_OUT_CNT_CLR_M (ASRC_CHNL0_OUT_CNT_CLR_V << ASRC_CHNL0_OUT_CNT_CLR_S)
#define ASRC_CHNL0_OUT_CNT_CLR_V 0x00000001U
#define ASRC_CHNL0_OUT_CNT_CLR_S 3
/** ASRC_CHNL0_OUT_LEN_COMP : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl0_out_cnt >=
* reg_chnl0_out_len
*/
#define ASRC_CHNL0_OUT_LEN_COMP (BIT(4))
#define ASRC_CHNL0_OUT_LEN_COMP_M (ASRC_CHNL0_OUT_LEN_COMP_V << ASRC_CHNL0_OUT_LEN_COMP_S)
#define ASRC_CHNL0_OUT_LEN_COMP_V 0x00000001U
#define ASRC_CHNL0_OUT_LEN_COMP_S 4
/** ASRC_CHNL0_OUT_LEN : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
#define ASRC_CHNL0_OUT_LEN 0x00FFFFFFU
#define ASRC_CHNL0_OUT_LEN_M (ASRC_CHNL0_OUT_LEN_V << ASRC_CHNL0_OUT_LEN_S)
#define ASRC_CHNL0_OUT_LEN_V 0x00FFFFFFU
#define ASRC_CHNL0_OUT_LEN_S 8
/** ASRC_CHNL0_FIFO_CTRL_REG register
* Control and configuration registers
*/
#define ASRC_CHNL0_FIFO_CTRL_REG (DR_REG_ASRC_BASE + 0x1c)
/** ASRC_CHNL0_INFIFO_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
#define ASRC_CHNL0_INFIFO_RESET (BIT(0))
#define ASRC_CHNL0_INFIFO_RESET_M (ASRC_CHNL0_INFIFO_RESET_V << ASRC_CHNL0_INFIFO_RESET_S)
#define ASRC_CHNL0_INFIFO_RESET_V 0x00000001U
#define ASRC_CHNL0_INFIFO_RESET_S 0
/** ASRC_CHNL0_OUTFIFO_RESET : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
#define ASRC_CHNL0_OUTFIFO_RESET (BIT(1))
#define ASRC_CHNL0_OUTFIFO_RESET_M (ASRC_CHNL0_OUTFIFO_RESET_V << ASRC_CHNL0_OUTFIFO_RESET_S)
#define ASRC_CHNL0_OUTFIFO_RESET_V 0x00000001U
#define ASRC_CHNL0_OUTFIFO_RESET_S 1
/** ASRC_CHNL0_INT_RAW_REG register
* Raw interrupt status
*/
#define ASRC_CHNL0_INT_RAW_REG (DR_REG_ASRC_BASE + 0x20)
/** ASRC_CHNL0_OUTCNT_EOF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW (BIT(0))
#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_M (ASRC_CHNL0_OUTCNT_EOF_INT_RAW_V << ASRC_CHNL0_OUTCNT_EOF_INT_RAW_S)
#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_V 0x00000001U
#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_S 0
/** ASRC_CHNL0_INT_ST_REG register
* Masked interrupt status
*/
#define ASRC_CHNL0_INT_ST_REG (DR_REG_ASRC_BASE + 0x24)
/** ASRC_CHNL0_OUTCNT_EOF_INT_ST : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
#define ASRC_CHNL0_OUTCNT_EOF_INT_ST (BIT(0))
#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_M (ASRC_CHNL0_OUTCNT_EOF_INT_ST_V << ASRC_CHNL0_OUTCNT_EOF_INT_ST_S)
#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_V 0x00000001U
#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_S 0
/** ASRC_CHNL0_INT_ENA_REG register
* Interrupt enable bits
*/
#define ASRC_CHNL0_INT_ENA_REG (DR_REG_ASRC_BASE + 0x28)
/** ASRC_CHNL0_OUTCNT_EOF_INT_ENA : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA (BIT(0))
#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_M (ASRC_CHNL0_OUTCNT_EOF_INT_ENA_V << ASRC_CHNL0_OUTCNT_EOF_INT_ENA_S)
#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_V 0x00000001U
#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_S 0
/** ASRC_CHNL0_INT_CLR_REG register
* Interrupt clear bits
*/
#define ASRC_CHNL0_INT_CLR_REG (DR_REG_ASRC_BASE + 0x2c)
/** ASRC_CHNL0_OUTCNT_EOF_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR (BIT(0))
#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_M (ASRC_CHNL0_OUTCNT_EOF_INT_CLR_V << ASRC_CHNL0_OUTCNT_EOF_INT_CLR_S)
#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_V 0x00000001U
#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_S 0
/** ASRC_CHNL0_OUT_CNT_REG register
* Status Registers
*/
#define ASRC_CHNL0_OUT_CNT_REG (DR_REG_ASRC_BASE + 0x30)
/** ASRC_CHNL0_OUT_CNT : RO; bitpos: [23:0]; default: 0;
* Represents the bytes numbers send to the DMA when EOF occurs.
*/
#define ASRC_CHNL0_OUT_CNT 0x00FFFFFFU
#define ASRC_CHNL0_OUT_CNT_M (ASRC_CHNL0_OUT_CNT_V << ASRC_CHNL0_OUT_CNT_S)
#define ASRC_CHNL0_OUT_CNT_V 0x00FFFFFFU
#define ASRC_CHNL0_OUT_CNT_S 0
/** ASRC_CHNL0_TRACE1_REG register
* Debug Register1
*/
#define ASRC_CHNL0_TRACE1_REG (DR_REG_ASRC_BASE + 0x38)
/** ASRC_CHNL0_OUT_INC : RO; bitpos: [23:0]; default: 0;
* Represents the samples numbers send to the DMA
*/
#define ASRC_CHNL0_OUT_INC 0x00FFFFFFU
#define ASRC_CHNL0_OUT_INC_M (ASRC_CHNL0_OUT_INC_V << ASRC_CHNL0_OUT_INC_S)
#define ASRC_CHNL0_OUT_INC_V 0x00FFFFFFU
#define ASRC_CHNL0_OUT_INC_S 0
/** ASRC_CHNL1_CFG0_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG0_REG (DR_REG_ASRC_BASE + 0x3c)
/** ASRC_CHNL1_RS2_STG1_BYPASS : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel1.
*/
#define ASRC_CHNL1_RS2_STG1_BYPASS (BIT(0))
#define ASRC_CHNL1_RS2_STG1_BYPASS_M (ASRC_CHNL1_RS2_STG1_BYPASS_V << ASRC_CHNL1_RS2_STG1_BYPASS_S)
#define ASRC_CHNL1_RS2_STG1_BYPASS_V 0x00000001U
#define ASRC_CHNL1_RS2_STG1_BYPASS_S 0
/** ASRC_CHNL1_RS2_STG0_BYPASS : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel1.
*/
#define ASRC_CHNL1_RS2_STG0_BYPASS (BIT(1))
#define ASRC_CHNL1_RS2_STG0_BYPASS_M (ASRC_CHNL1_RS2_STG0_BYPASS_V << ASRC_CHNL1_RS2_STG0_BYPASS_S)
#define ASRC_CHNL1_RS2_STG0_BYPASS_V 0x00000001U
#define ASRC_CHNL1_RS2_STG0_BYPASS_S 1
/** ASRC_CHNL1_FRAC_BYPASS : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel1.
*/
#define ASRC_CHNL1_FRAC_BYPASS (BIT(2))
#define ASRC_CHNL1_FRAC_BYPASS_M (ASRC_CHNL1_FRAC_BYPASS_V << ASRC_CHNL1_FRAC_BYPASS_S)
#define ASRC_CHNL1_FRAC_BYPASS_V 0x00000001U
#define ASRC_CHNL1_FRAC_BYPASS_S 2
/** ASRC_CHNL1_RS2_STG1_MODE : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
#define ASRC_CHNL1_RS2_STG1_MODE (BIT(3))
#define ASRC_CHNL1_RS2_STG1_MODE_M (ASRC_CHNL1_RS2_STG1_MODE_V << ASRC_CHNL1_RS2_STG1_MODE_S)
#define ASRC_CHNL1_RS2_STG1_MODE_V 0x00000001U
#define ASRC_CHNL1_RS2_STG1_MODE_S 3
/** ASRC_CHNL1_RS2_STG0_MODE : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
#define ASRC_CHNL1_RS2_STG0_MODE (BIT(4))
#define ASRC_CHNL1_RS2_STG0_MODE_M (ASRC_CHNL1_RS2_STG0_MODE_V << ASRC_CHNL1_RS2_STG0_MODE_S)
#define ASRC_CHNL1_RS2_STG0_MODE_V 0x00000001U
#define ASRC_CHNL1_RS2_STG0_MODE_S 4
/** ASRC_CHNL1_FRAC_AHEAD : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel1, it should
* be 1 when input frequency is higher the output.
*/
#define ASRC_CHNL1_FRAC_AHEAD (BIT(5))
#define ASRC_CHNL1_FRAC_AHEAD_M (ASRC_CHNL1_FRAC_AHEAD_V << ASRC_CHNL1_FRAC_AHEAD_S)
#define ASRC_CHNL1_FRAC_AHEAD_V 0x00000001U
#define ASRC_CHNL1_FRAC_AHEAD_S 5
/** ASRC_CHNL1_MODE : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
#define ASRC_CHNL1_MODE 0x00000003U
#define ASRC_CHNL1_MODE_M (ASRC_CHNL1_MODE_V << ASRC_CHNL1_MODE_S)
#define ASRC_CHNL1_MODE_V 0x00000003U
#define ASRC_CHNL1_MODE_S 7
/** ASRC_CHNL1_SEL : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
#define ASRC_CHNL1_SEL (BIT(9))
#define ASRC_CHNL1_SEL_M (ASRC_CHNL1_SEL_V << ASRC_CHNL1_SEL_S)
#define ASRC_CHNL1_SEL_V 0x00000001U
#define ASRC_CHNL1_SEL_S 9
/** ASRC_CHNL1_CFG1_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG1_REG (DR_REG_ASRC_BASE + 0x40)
/** ASRC_CHNL1_FRAC_M : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
#define ASRC_CHNL1_FRAC_M 0x000003FFU
#define ASRC_CHNL1_FRAC_M_M (ASRC_CHNL1_FRAC_M_V << ASRC_CHNL1_FRAC_M_S)
#define ASRC_CHNL1_FRAC_M_V 0x000003FFU
#define ASRC_CHNL1_FRAC_M_S 0
/** ASRC_CHNL1_FRAC_L : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
#define ASRC_CHNL1_FRAC_L 0x000003FFU
#define ASRC_CHNL1_FRAC_L_M (ASRC_CHNL1_FRAC_L_V << ASRC_CHNL1_FRAC_L_S)
#define ASRC_CHNL1_FRAC_L_V 0x000003FFU
#define ASRC_CHNL1_FRAC_L_S 10
/** ASRC_CHNL1_CFG2_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG2_REG (DR_REG_ASRC_BASE + 0x44)
/** ASRC_CHNL1_FRAC_RECIPL : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel1.
*/
#define ASRC_CHNL1_FRAC_RECIPL 0x000FFFFFU
#define ASRC_CHNL1_FRAC_RECIPL_M (ASRC_CHNL1_FRAC_RECIPL_V << ASRC_CHNL1_FRAC_RECIPL_S)
#define ASRC_CHNL1_FRAC_RECIPL_V 0x000FFFFFU
#define ASRC_CHNL1_FRAC_RECIPL_S 0
/** ASRC_CHNL1_CFG3_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG3_REG (DR_REG_ASRC_BASE + 0x48)
/** ASRC_CHNL1_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel1.
*/
#define ASRC_CHNL1_RESET (BIT(0))
#define ASRC_CHNL1_RESET_M (ASRC_CHNL1_RESET_V << ASRC_CHNL1_RESET_S)
#define ASRC_CHNL1_RESET_V 0x00000001U
#define ASRC_CHNL1_RESET_S 0
/** ASRC_CHNL1_CFG4_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG4_REG (DR_REG_ASRC_BASE + 0x4c)
/** ASRC_CHNL1_START : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel1.
*/
#define ASRC_CHNL1_START (BIT(0))
#define ASRC_CHNL1_START_M (ASRC_CHNL1_START_V << ASRC_CHNL1_START_S)
#define ASRC_CHNL1_START_V 0x00000001U
#define ASRC_CHNL1_START_S 0
/** ASRC_CHNL1_CFG5_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG5_REG (DR_REG_ASRC_BASE + 0x50)
/** ASRC_CHNL1_IN_CNT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
#define ASRC_CHNL1_IN_CNT_ENA (BIT(0))
#define ASRC_CHNL1_IN_CNT_ENA_M (ASRC_CHNL1_IN_CNT_ENA_V << ASRC_CHNL1_IN_CNT_ENA_S)
#define ASRC_CHNL1_IN_CNT_ENA_V 0x00000001U
#define ASRC_CHNL1_IN_CNT_ENA_S 0
/** ASRC_CHNL1_IN_CNT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
#define ASRC_CHNL1_IN_CNT_CLR (BIT(1))
#define ASRC_CHNL1_IN_CNT_CLR_M (ASRC_CHNL1_IN_CNT_CLR_V << ASRC_CHNL1_IN_CNT_CLR_S)
#define ASRC_CHNL1_IN_CNT_CLR_V 0x00000001U
#define ASRC_CHNL1_IN_CNT_CLR_S 1
/** ASRC_CHNL1_IN_LEN : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte numbers of data from the DMA
*/
#define ASRC_CHNL1_IN_LEN 0x00FFFFFFU
#define ASRC_CHNL1_IN_LEN_M (ASRC_CHNL1_IN_LEN_V << ASRC_CHNL1_IN_LEN_S)
#define ASRC_CHNL1_IN_LEN_V 0x00FFFFFFU
#define ASRC_CHNL1_IN_LEN_S 8
/** ASRC_CHNL1_CFG6_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_CFG6_REG (DR_REG_ASRC_BASE + 0x54)
/** ASRC_CHNL1_OUT_EOF_GEN_MODE : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
#define ASRC_CHNL1_OUT_EOF_GEN_MODE 0x00000003U
#define ASRC_CHNL1_OUT_EOF_GEN_MODE_M (ASRC_CHNL1_OUT_EOF_GEN_MODE_V << ASRC_CHNL1_OUT_EOF_GEN_MODE_S)
#define ASRC_CHNL1_OUT_EOF_GEN_MODE_V 0x00000003U
#define ASRC_CHNL1_OUT_EOF_GEN_MODE_S 0
/** ASRC_CHNL1_OUT_CNT_ENA : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
#define ASRC_CHNL1_OUT_CNT_ENA (BIT(2))
#define ASRC_CHNL1_OUT_CNT_ENA_M (ASRC_CHNL1_OUT_CNT_ENA_V << ASRC_CHNL1_OUT_CNT_ENA_S)
#define ASRC_CHNL1_OUT_CNT_ENA_V 0x00000001U
#define ASRC_CHNL1_OUT_CNT_ENA_S 2
/** ASRC_CHNL1_OUT_CNT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
#define ASRC_CHNL1_OUT_CNT_CLR (BIT(3))
#define ASRC_CHNL1_OUT_CNT_CLR_M (ASRC_CHNL1_OUT_CNT_CLR_V << ASRC_CHNL1_OUT_CNT_CLR_S)
#define ASRC_CHNL1_OUT_CNT_CLR_V 0x00000001U
#define ASRC_CHNL1_OUT_CNT_CLR_S 3
/** ASRC_CHNL1_OUT_SAMPLES_COMP : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl1_out_cnt >=
* reg_chnl1_out_len
*/
#define ASRC_CHNL1_OUT_SAMPLES_COMP (BIT(4))
#define ASRC_CHNL1_OUT_SAMPLES_COMP_M (ASRC_CHNL1_OUT_SAMPLES_COMP_V << ASRC_CHNL1_OUT_SAMPLES_COMP_S)
#define ASRC_CHNL1_OUT_SAMPLES_COMP_V 0x00000001U
#define ASRC_CHNL1_OUT_SAMPLES_COMP_S 4
/** ASRC_CHNL1_OUT_LEN : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
#define ASRC_CHNL1_OUT_LEN 0x00FFFFFFU
#define ASRC_CHNL1_OUT_LEN_M (ASRC_CHNL1_OUT_LEN_V << ASRC_CHNL1_OUT_LEN_S)
#define ASRC_CHNL1_OUT_LEN_V 0x00FFFFFFU
#define ASRC_CHNL1_OUT_LEN_S 8
/** ASRC_CHNL1_FIFO_CTRL_REG register
* Control and configuration registers
*/
#define ASRC_CHNL1_FIFO_CTRL_REG (DR_REG_ASRC_BASE + 0x58)
/** ASRC_CHNL1_INFIFO_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
#define ASRC_CHNL1_INFIFO_RESET (BIT(0))
#define ASRC_CHNL1_INFIFO_RESET_M (ASRC_CHNL1_INFIFO_RESET_V << ASRC_CHNL1_INFIFO_RESET_S)
#define ASRC_CHNL1_INFIFO_RESET_V 0x00000001U
#define ASRC_CHNL1_INFIFO_RESET_S 0
/** ASRC_CHNL1_OUTFIFO_RESET : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
#define ASRC_CHNL1_OUTFIFO_RESET (BIT(1))
#define ASRC_CHNL1_OUTFIFO_RESET_M (ASRC_CHNL1_OUTFIFO_RESET_V << ASRC_CHNL1_OUTFIFO_RESET_S)
#define ASRC_CHNL1_OUTFIFO_RESET_V 0x00000001U
#define ASRC_CHNL1_OUTFIFO_RESET_S 1
/** ASRC_CHNL1_INT_RAW_REG register
* Raw interrupt status
*/
#define ASRC_CHNL1_INT_RAW_REG (DR_REG_ASRC_BASE + 0x5c)
/** ASRC_CHNL1_OUTCNT_EOF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW (BIT(0))
#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_M (ASRC_CHNL1_OUTCNT_EOF_INT_RAW_V << ASRC_CHNL1_OUTCNT_EOF_INT_RAW_S)
#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_V 0x00000001U
#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_S 0
/** ASRC_CHNL1_INT_ST_REG register
* Masked interrupt status
*/
#define ASRC_CHNL1_INT_ST_REG (DR_REG_ASRC_BASE + 0x60)
/** ASRC_CHNL1_OUTCNT_EOF_INT_ST : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
#define ASRC_CHNL1_OUTCNT_EOF_INT_ST (BIT(0))
#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_M (ASRC_CHNL1_OUTCNT_EOF_INT_ST_V << ASRC_CHNL1_OUTCNT_EOF_INT_ST_S)
#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_V 0x00000001U
#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_S 0
/** ASRC_CHNL1_INT_ENA_REG register
* Interrupt enable bits
*/
#define ASRC_CHNL1_INT_ENA_REG (DR_REG_ASRC_BASE + 0x64)
/** ASRC_CHNL1_OUTCNT_EOF_INT_ENA : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA (BIT(0))
#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_M (ASRC_CHNL1_OUTCNT_EOF_INT_ENA_V << ASRC_CHNL1_OUTCNT_EOF_INT_ENA_S)
#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_V 0x00000001U
#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_S 0
/** ASRC_CHNL1_INT_CLR_REG register
* Interrupt clear bits
*/
#define ASRC_CHNL1_INT_CLR_REG (DR_REG_ASRC_BASE + 0x68)
/** ASRC_CHNL1_OUTCNT_EOF_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR (BIT(0))
#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_M (ASRC_CHNL1_OUTCNT_EOF_INT_CLR_V << ASRC_CHNL1_OUTCNT_EOF_INT_CLR_S)
#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_V 0x00000001U
#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_S 0
/** ASRC_CHNL1_OUT_CNT_REG register
* Status Registers
*/
#define ASRC_CHNL1_OUT_CNT_REG (DR_REG_ASRC_BASE + 0x6c)
/** ASRC_CHNL1_OUT_CNT : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA when EOF occurs.
*/
#define ASRC_CHNL1_OUT_CNT 0x00FFFFFFU
#define ASRC_CHNL1_OUT_CNT_M (ASRC_CHNL1_OUT_CNT_V << ASRC_CHNL1_OUT_CNT_S)
#define ASRC_CHNL1_OUT_CNT_V 0x00FFFFFFU
#define ASRC_CHNL1_OUT_CNT_S 0
/** ASRC_CHNL1_TRACE1_REG register
* Debug Register1
*/
#define ASRC_CHNL1_TRACE1_REG (DR_REG_ASRC_BASE + 0x74)
/** ASRC_CHNL1_OUT_INC : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA
*/
#define ASRC_CHNL1_OUT_INC 0x00FFFFFFU
#define ASRC_CHNL1_OUT_INC_M (ASRC_CHNL1_OUT_INC_V << ASRC_CHNL1_OUT_INC_S)
#define ASRC_CHNL1_OUT_INC_V 0x00FFFFFFU
#define ASRC_CHNL1_OUT_INC_S 0
/** ASRC_SYS_REG register
* Control and configuration
*/
#define ASRC_SYS_REG (DR_REG_ASRC_BASE + 0xf8)
/** ASRC_CLK_EN : R/W; bitpos: [0]; default: 0;
* Reserved
*/
#define ASRC_CLK_EN (BIT(0))
#define ASRC_CLK_EN_M (ASRC_CLK_EN_V << ASRC_CLK_EN_S)
#define ASRC_CLK_EN_V 0x00000001U
#define ASRC_CLK_EN_S 0
/** ASRC_CHNL0_CLK_FO : R/W; bitpos: [1]; default: 0;
* Set this bit to make channel0 clock free run.
*/
#define ASRC_CHNL0_CLK_FO (BIT(1))
#define ASRC_CHNL0_CLK_FO_M (ASRC_CHNL0_CLK_FO_V << ASRC_CHNL0_CLK_FO_S)
#define ASRC_CHNL0_CLK_FO_V 0x00000001U
#define ASRC_CHNL0_CLK_FO_S 1
/** ASRC_CHNL1_CLK_FO : R/W; bitpos: [2]; default: 0;
* Set this bit to make channel1 clock free run.
*/
#define ASRC_CHNL1_CLK_FO (BIT(2))
#define ASRC_CHNL1_CLK_FO_M (ASRC_CHNL1_CLK_FO_V << ASRC_CHNL1_CLK_FO_S)
#define ASRC_CHNL1_CLK_FO_V 0x00000001U
#define ASRC_CHNL1_CLK_FO_S 2
/** ASRC_CHNL0_OUTFIFO_CLK_FO : R/W; bitpos: [3]; default: 0;
* Set this bit to make channel0 outfifo clock free run.
*/
#define ASRC_CHNL0_OUTFIFO_CLK_FO (BIT(3))
#define ASRC_CHNL0_OUTFIFO_CLK_FO_M (ASRC_CHNL0_OUTFIFO_CLK_FO_V << ASRC_CHNL0_OUTFIFO_CLK_FO_S)
#define ASRC_CHNL0_OUTFIFO_CLK_FO_V 0x00000001U
#define ASRC_CHNL0_OUTFIFO_CLK_FO_S 3
/** ASRC_CHNL0_INFIFO_CLK_FO : R/W; bitpos: [4]; default: 0;
* Set this bit to make channel0 infifo clock free run.
*/
#define ASRC_CHNL0_INFIFO_CLK_FO (BIT(4))
#define ASRC_CHNL0_INFIFO_CLK_FO_M (ASRC_CHNL0_INFIFO_CLK_FO_V << ASRC_CHNL0_INFIFO_CLK_FO_S)
#define ASRC_CHNL0_INFIFO_CLK_FO_V 0x00000001U
#define ASRC_CHNL0_INFIFO_CLK_FO_S 4
/** ASRC_CHNL1_OUTFIFO_CLK_FO : R/W; bitpos: [5]; default: 0;
* Set this bit to make channel1 outfifo clock free run.
*/
#define ASRC_CHNL1_OUTFIFO_CLK_FO (BIT(5))
#define ASRC_CHNL1_OUTFIFO_CLK_FO_M (ASRC_CHNL1_OUTFIFO_CLK_FO_V << ASRC_CHNL1_OUTFIFO_CLK_FO_S)
#define ASRC_CHNL1_OUTFIFO_CLK_FO_V 0x00000001U
#define ASRC_CHNL1_OUTFIFO_CLK_FO_S 5
/** ASRC_CHNL1_INFIFO_CLK_FO : R/W; bitpos: [6]; default: 0;
* Set this bit to make channel1 infifo clock free run.
*/
#define ASRC_CHNL1_INFIFO_CLK_FO (BIT(6))
#define ASRC_CHNL1_INFIFO_CLK_FO_M (ASRC_CHNL1_INFIFO_CLK_FO_V << ASRC_CHNL1_INFIFO_CLK_FO_S)
#define ASRC_CHNL1_INFIFO_CLK_FO_V 0x00000001U
#define ASRC_CHNL1_INFIFO_CLK_FO_S 6
/** ASRC_DATE_REG register
* Control and configuration registers
*/
#define ASRC_DATE_REG (DR_REG_ASRC_BASE + 0xfc)
/** ASRC_DATE : R/W; bitpos: [27:0]; default: 37777984;
* Reserved
*/
#define ASRC_DATE 0x0FFFFFFFU
#define ASRC_DATE_M (ASRC_DATE_V << ASRC_DATE_S)
#define ASRC_DATE_V 0x0FFFFFFFU
#define ASRC_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/asrc_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of chnl0_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel0.
*/
uint32_t chnl0_rs2_stg1_bypass:1;
/** chnl0_rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel0.
*/
uint32_t chnl0_rs2_stg0_bypass:1;
/** chnl0_frac_bypass : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel0.
*/
uint32_t chnl0_frac_bypass:1;
/** chnl0_rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl0_rs2_stg1_mode:1;
/** chnl0_rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl0_rs2_stg0_mode:1;
/** chnl0_frac_ahead : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel0, it should
* be 1 when input frequency is higher the output.
*/
uint32_t chnl0_frac_ahead:1;
uint32_t reserved_6:1;
/** chnl0_mode : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
uint32_t chnl0_mode:2;
/** chnl0_sel : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
uint32_t chnl0_sel:1;
uint32_t reserved_10:22;
};
uint32_t val;
} asrc_chnl0_cfg0_reg_t;
/** Type of chnl0_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_frac_m : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
uint32_t chnl0_frac_m:10;
/** chnl0_frac_l : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
uint32_t chnl0_frac_l:10;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl0_cfg1_reg_t;
/** Type of chnl0_cfg2 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_frac_recipl : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel0.
*/
uint32_t chnl0_frac_recipl:20;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl0_cfg2_reg_t;
/** Type of chnl0_cfg3 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel0.
*/
uint32_t chnl0_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_cfg3_reg_t;
/** Type of chnl0_cfg4 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_start : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel0.
*/
uint32_t chnl0_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_cfg4_reg_t;
/** Type of chnl0_cfg5 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_in_cnt_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
uint32_t chnl0_in_cnt_ena:1;
/** chnl0_in_cnt_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
uint32_t chnl0_in_cnt_clr:1;
uint32_t reserved_2:6;
/** chnl0_in_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data from the DMA
*/
uint32_t chnl0_in_len:24;
};
uint32_t val;
} asrc_chnl0_cfg5_reg_t;
/** Type of chnl0_cfg6 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
uint32_t chnl0_out_eof_gen_mode:2;
/** chnl0_out_cnt_ena : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
uint32_t chnl0_out_cnt_ena:1;
/** chnl0_out_cnt_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
uint32_t chnl0_out_cnt_clr:1;
/** chnl0_out_len_comp : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl0_out_cnt >=
* reg_chnl0_out_len
*/
uint32_t chnl0_out_len_comp:1;
uint32_t reserved_5:3;
/** chnl0_out_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
uint32_t chnl0_out_len:24;
};
uint32_t val;
} asrc_chnl0_cfg6_reg_t;
/** Type of chnl0_fifo_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_infifo_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
uint32_t chnl0_infifo_reset:1;
/** chnl0_outfifo_reset : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
uint32_t chnl0_outfifo_reset:1;
uint32_t reserved_2:30;
};
uint32_t val;
} asrc_chnl0_fifo_ctrl_reg_t;
/** Type of chnl1_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel1.
*/
uint32_t chnl1_rs2_stg1_bypass:1;
/** chnl1_rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel1.
*/
uint32_t chnl1_rs2_stg0_bypass:1;
/** chnl1_frac_bypass : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel1.
*/
uint32_t chnl1_frac_bypass:1;
/** chnl1_rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl1_rs2_stg1_mode:1;
/** chnl1_rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl1_rs2_stg0_mode:1;
/** chnl1_frac_ahead : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel1, it should
* be 1 when input frequency is higher the output.
*/
uint32_t chnl1_frac_ahead:1;
uint32_t reserved_6:1;
/** chnl1_mode : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
uint32_t chnl1_mode:2;
/** chnl1_sel : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
uint32_t chnl1_sel:1;
uint32_t reserved_10:22;
};
uint32_t val;
} asrc_chnl1_cfg0_reg_t;
/** Type of chnl1_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_frac_m : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
uint32_t chnl1_frac_m:10;
/** chnl1_frac_l : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
uint32_t chnl1_frac_l:10;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl1_cfg1_reg_t;
/** Type of chnl1_cfg2 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_frac_recipl : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel1.
*/
uint32_t chnl1_frac_recipl:20;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl1_cfg2_reg_t;
/** Type of chnl1_cfg3 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel1.
*/
uint32_t chnl1_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_cfg3_reg_t;
/** Type of chnl1_cfg4 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_start : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel1.
*/
uint32_t chnl1_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_cfg4_reg_t;
/** Type of chnl1_cfg5 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_in_cnt_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
uint32_t chnl1_in_cnt_ena:1;
/** chnl1_in_cnt_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
uint32_t chnl1_in_cnt_clr:1;
uint32_t reserved_2:6;
/** chnl1_in_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte numbers of data from the DMA
*/
uint32_t chnl1_in_len:24;
};
uint32_t val;
} asrc_chnl1_cfg5_reg_t;
/** Type of chnl1_cfg6 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
uint32_t chnl1_out_eof_gen_mode:2;
/** chnl1_out_cnt_ena : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
uint32_t chnl1_out_cnt_ena:1;
/** chnl1_out_cnt_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
uint32_t chnl1_out_cnt_clr:1;
/** chnl1_out_samples_comp : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl1_out_cnt >=
* reg_chnl1_out_len
*/
uint32_t chnl1_out_samples_comp:1;
uint32_t reserved_5:3;
/** chnl1_out_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
uint32_t chnl1_out_len:24;
};
uint32_t val;
} asrc_chnl1_cfg6_reg_t;
/** Type of chnl1_fifo_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_infifo_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
uint32_t chnl1_infifo_reset:1;
/** chnl1_outfifo_reset : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
uint32_t chnl1_outfifo_reset:1;
uint32_t reserved_2:30;
};
uint32_t val;
} asrc_chnl1_fifo_ctrl_reg_t;
/** Group: Interrupt Register */
/** Type of chnl0_int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
uint32_t chnl0_outcnt_eof_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_int_raw_reg_t;
/** Type of chnl0_int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
uint32_t chnl0_outcnt_eof_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_int_st_reg_t;
/** Type of chnl0_int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
uint32_t chnl0_outcnt_eof_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_int_ena_reg_t;
/** Type of chnl0_int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
uint32_t chnl0_outcnt_eof_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl0_int_clr_reg_t;
/** Type of chnl1_int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
uint32_t chnl1_outcnt_eof_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_raw_reg_t;
/** Type of chnl1_int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
uint32_t chnl1_outcnt_eof_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_st_reg_t;
/** Type of chnl1_int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
uint32_t chnl1_outcnt_eof_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_ena_reg_t;
/** Type of chnl1_int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
uint32_t chnl1_outcnt_eof_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_clr_reg_t;
/** Group: Status registers */
/** Type of chnl0_out_cnt register
* Status Registers
*/
typedef union {
struct {
/** chnl0_out_cnt : RO; bitpos: [23:0]; default: 0;
* Represents the bytes numbers send to the DMA when EOF occurs.
*/
uint32_t chnl0_out_cnt:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl0_out_cnt_reg_t;
/** Type of chnl1_out_cnt register
* Status Registers
*/
typedef union {
struct {
/** chnl1_out_cnt : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA when EOF occurs.
*/
uint32_t chnl1_out_cnt:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl1_out_cnt_reg_t;
/** Group: DEBUG registers */
/** Type of chnl0_trace1 register
* Debug Register1
*/
typedef union {
struct {
/** chnl0_out_inc : RO; bitpos: [23:0]; default: 0;
* Represents the samples numbers send to the DMA
*/
uint32_t chnl0_out_inc:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl0_trace1_reg_t;
/** Type of chnl1_trace1 register
* Debug Register1
*/
typedef union {
struct {
/** chnl1_out_inc : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA
*/
uint32_t chnl1_out_inc:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl1_trace1_reg_t;
/** Group: Configuration registers */
/** Type of sys register
* Control and configuration
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
/** chnl0_clk_fo : R/W; bitpos: [1]; default: 0;
* Set this bit to make channel0 clock free run.
*/
uint32_t chnl0_clk_fo:1;
/** chnl1_clk_fo : R/W; bitpos: [2]; default: 0;
* Set this bit to make channel1 clock free run.
*/
uint32_t chnl1_clk_fo:1;
/** chnl0_outfifo_clk_fo : R/W; bitpos: [3]; default: 0;
* Set this bit to make channel0 outfifo clock free run.
*/
uint32_t chnl0_outfifo_clk_fo:1;
/** chnl0_infifo_clk_fo : R/W; bitpos: [4]; default: 0;
* Set this bit to make channel0 infifo clock free run.
*/
uint32_t chnl0_infifo_clk_fo:1;
/** chnl1_outfifo_clk_fo : R/W; bitpos: [5]; default: 0;
* Set this bit to make channel1 outfifo clock free run.
*/
uint32_t chnl1_outfifo_clk_fo:1;
/** chnl1_infifo_clk_fo : R/W; bitpos: [6]; default: 0;
* Set this bit to make channel1 infifo clock free run.
*/
uint32_t chnl1_infifo_clk_fo:1;
uint32_t reserved_7:25;
};
uint32_t val;
} asrc_sys_reg_t;
/** Group: Version register */
/** Type of date register
* Control and configuration registers
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37777984;
* Reserved
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} asrc_date_reg_t;
typedef struct {
volatile asrc_chnl0_cfg0_reg_t chnl0_cfg0;
volatile asrc_chnl0_cfg1_reg_t chnl0_cfg1;
volatile asrc_chnl0_cfg2_reg_t chnl0_cfg2;
volatile asrc_chnl0_cfg3_reg_t chnl0_cfg3;
volatile asrc_chnl0_cfg4_reg_t chnl0_cfg4;
volatile asrc_chnl0_cfg5_reg_t chnl0_cfg5;
volatile asrc_chnl0_cfg6_reg_t chnl0_cfg6;
volatile asrc_chnl0_fifo_ctrl_reg_t chnl0_fifo_ctrl;
volatile asrc_chnl0_int_raw_reg_t chnl0_int_raw;
volatile asrc_chnl0_int_st_reg_t chnl0_int_st;
volatile asrc_chnl0_int_ena_reg_t chnl0_int_ena;
volatile asrc_chnl0_int_clr_reg_t chnl0_int_clr;
volatile asrc_chnl0_out_cnt_reg_t chnl0_out_cnt;
uint32_t reserved_034;
volatile asrc_chnl0_trace1_reg_t chnl0_trace1;
volatile asrc_chnl1_cfg0_reg_t chnl1_cfg0;
volatile asrc_chnl1_cfg1_reg_t chnl1_cfg1;
volatile asrc_chnl1_cfg2_reg_t chnl1_cfg2;
volatile asrc_chnl1_cfg3_reg_t chnl1_cfg3;
volatile asrc_chnl1_cfg4_reg_t chnl1_cfg4;
volatile asrc_chnl1_cfg5_reg_t chnl1_cfg5;
volatile asrc_chnl1_cfg6_reg_t chnl1_cfg6;
volatile asrc_chnl1_fifo_ctrl_reg_t chnl1_fifo_ctrl;
volatile asrc_chnl1_int_raw_reg_t chnl1_int_raw;
volatile asrc_chnl1_int_st_reg_t chnl1_int_st;
volatile asrc_chnl1_int_ena_reg_t chnl1_int_ena;
volatile asrc_chnl1_int_clr_reg_t chnl1_int_clr;
volatile asrc_chnl1_out_cnt_reg_t chnl1_out_cnt;
uint32_t reserved_070;
volatile asrc_chnl1_trace1_reg_t chnl1_trace1;
uint32_t reserved_078[32];
volatile asrc_sys_reg_t sys;
volatile asrc_date_reg_t date;
} asrc_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(asrc_dev_t) == 0x100, "Invalid size of asrc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** BITSCRAMBLER_TX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_TX_INST_IDX 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_M (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
#define BITSCRAMBLER_TX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_S 0
/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_TX_INST_POS 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_M (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
#define BITSCRAMBLER_TX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_S 3
/** BITSCRAMBLER_TX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
#define BITSCRAMBLER_TX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_M (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
#define BITSCRAMBLER_TX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_S 0
/** BITSCRAMBLER_RX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_RX_INST_IDX 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_M (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
#define BITSCRAMBLER_RX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_S 0
/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_RX_INST_POS 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_M (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
#define BITSCRAMBLER_RX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_S 3
/** BITSCRAMBLER_RX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
#define BITSCRAMBLER_RX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_M (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
#define BITSCRAMBLER_RX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_S 0
/** BITSCRAMBLER_TX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
#define BITSCRAMBLER_TX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_M (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
#define BITSCRAMBLER_TX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_S 0
/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_TX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_M (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
#define BITSCRAMBLER_TX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_S 11
/** BITSCRAMBLER_TX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_TX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_M (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
#define BITSCRAMBLER_TX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_S 0
/** BITSCRAMBLER_RX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
#define BITSCRAMBLER_RX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_M (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
#define BITSCRAMBLER_RX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_S 0
/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_RX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_M (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
#define BITSCRAMBLER_RX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_S 11
/** BITSCRAMBLER_RX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_RX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_M (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
#define BITSCRAMBLER_RX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_S 0
/** BITSCRAMBLER_TX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_TX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_M (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
#define BITSCRAMBLER_TX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_S 0
/** BITSCRAMBLER_RX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_RX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_M (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
#define BITSCRAMBLER_RX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_S 0
/** BITSCRAMBLER_TX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
#define BITSCRAMBLER_TX_ENA (BIT(0))
#define BITSCRAMBLER_TX_ENA_M (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
#define BITSCRAMBLER_TX_ENA_V 0x00000001U
#define BITSCRAMBLER_TX_ENA_S 0
/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_PAUSE (BIT(1))
#define BITSCRAMBLER_TX_PAUSE_M (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
#define BITSCRAMBLER_TX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_PAUSE_S 1
/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_HALT (BIT(2))
#define BITSCRAMBLER_TX_HALT_M (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
#define BITSCRAMBLER_TX_HALT_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_S 2
/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
#define BITSCRAMBLER_TX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_TX_EOF_MODE_M (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
#define BITSCRAMBLER_TX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_MODE_S 3
/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_TX_COND_MODE (BIT(4))
#define BITSCRAMBLER_TX_COND_MODE_M (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
#define BITSCRAMBLER_TX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_COND_MODE_S 4
/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
#define BITSCRAMBLER_TX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
#define BITSCRAMBLER_TX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_FETCH_MODE_S 5
/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_TX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_TX_HALT_MODE_M (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
#define BITSCRAMBLER_TX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_MODE_S 6
/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_TX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_TX_RD_DUMMY_M (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
#define BITSCRAMBLER_TX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_TX_RD_DUMMY_S 7
/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
#define BITSCRAMBLER_TX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_TX_FIFO_RST_M (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
#define BITSCRAMBLER_TX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_RST_S 8
/** BITSCRAMBLER_RX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
#define BITSCRAMBLER_RX_ENA (BIT(0))
#define BITSCRAMBLER_RX_ENA_M (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
#define BITSCRAMBLER_RX_ENA_V 0x00000001U
#define BITSCRAMBLER_RX_ENA_S 0
/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_PAUSE (BIT(1))
#define BITSCRAMBLER_RX_PAUSE_M (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
#define BITSCRAMBLER_RX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_PAUSE_S 1
/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_HALT (BIT(2))
#define BITSCRAMBLER_RX_HALT_M (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
#define BITSCRAMBLER_RX_HALT_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_S 2
/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
#define BITSCRAMBLER_RX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_RX_EOF_MODE_M (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
#define BITSCRAMBLER_RX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_MODE_S 3
/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_RX_COND_MODE (BIT(4))
#define BITSCRAMBLER_RX_COND_MODE_M (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
#define BITSCRAMBLER_RX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_COND_MODE_S 4
/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
#define BITSCRAMBLER_RX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
#define BITSCRAMBLER_RX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_FETCH_MODE_S 5
/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_RX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_RX_HALT_MODE_M (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
#define BITSCRAMBLER_RX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_MODE_S 6
/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_RX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_RX_RD_DUMMY_M (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
#define BITSCRAMBLER_RX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_RX_RD_DUMMY_S 7
/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
#define BITSCRAMBLER_RX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_RX_FIFO_RST_M (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
#define BITSCRAMBLER_RX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_RST_S 8
/** BITSCRAMBLER_TX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
#define BITSCRAMBLER_TX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_TX_IN_IDLE_M (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
#define BITSCRAMBLER_TX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_IDLE_S 0
/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
#define BITSCRAMBLER_TX_IN_RUN (BIT(1))
#define BITSCRAMBLER_TX_IN_RUN_M (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
#define BITSCRAMBLER_TX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_TX_IN_RUN_S 1
/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_TX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_TX_IN_WAIT_M (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
#define BITSCRAMBLER_TX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_TX_IN_WAIT_S 2
/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
#define BITSCRAMBLER_TX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_TX_IN_PAUSE_M (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
#define BITSCRAMBLER_TX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_PAUSE_S 3
/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 1;
* represents the bitscrambler tx fifo in empty state
*/
#define BITSCRAMBLER_TX_FIFO_EMPTY (BIT(4))
#define BITSCRAMBLER_TX_FIFO_EMPTY_M (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
#define BITSCRAMBLER_TX_FIFO_EMPTY_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_EMPTY_S 4
/** BITSCRAMBLER_TX_CRC_RDY : RO; bitpos: [5]; default: 0;
* represents the crc calculate result of bitscrambler tx path is ready
*/
#define BITSCRAMBLER_TX_CRC_RDY (BIT(5))
#define BITSCRAMBLER_TX_CRC_RDY_M (BITSCRAMBLER_TX_CRC_RDY_V << BITSCRAMBLER_TX_CRC_RDY_S)
#define BITSCRAMBLER_TX_CRC_RDY_V 0x00000001U
#define BITSCRAMBLER_TX_CRC_RDY_S 5
/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
#define BITSCRAMBLER_TX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_M (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
#define BITSCRAMBLER_TX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
#define BITSCRAMBLER_TX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_TX_EOF_OVERLOAD_M (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_TX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
#define BITSCRAMBLER_TX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_RX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
#define BITSCRAMBLER_RX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_RX_IN_IDLE_M (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
#define BITSCRAMBLER_RX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_IDLE_S 0
/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
#define BITSCRAMBLER_RX_IN_RUN (BIT(1))
#define BITSCRAMBLER_RX_IN_RUN_M (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
#define BITSCRAMBLER_RX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_RX_IN_RUN_S 1
/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_RX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_RX_IN_WAIT_M (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
#define BITSCRAMBLER_RX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_RX_IN_WAIT_S 2
/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
#define BITSCRAMBLER_RX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_RX_IN_PAUSE_M (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
#define BITSCRAMBLER_RX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_PAUSE_S 3
/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
#define BITSCRAMBLER_RX_FIFO_FULL (BIT(4))
#define BITSCRAMBLER_RX_FIFO_FULL_M (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
#define BITSCRAMBLER_RX_FIFO_FULL_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_FULL_S 4
/** BITSCRAMBLER_RX_CRC_RDY : RO; bitpos: [5]; default: 0;
* represents the crc calculate result of bitscrambler rx path is ready
*/
#define BITSCRAMBLER_RX_CRC_RDY (BIT(5))
#define BITSCRAMBLER_RX_CRC_RDY_M (BITSCRAMBLER_RX_CRC_RDY_V << BITSCRAMBLER_RX_CRC_RDY_S)
#define BITSCRAMBLER_RX_CRC_RDY_V 0x00000001U
#define BITSCRAMBLER_RX_CRC_RDY_S 5
/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
#define BITSCRAMBLER_RX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_M (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
#define BITSCRAMBLER_RX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
#define BITSCRAMBLER_RX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_RX_EOF_OVERLOAD_M (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_RX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
#define BITSCRAMBLER_RX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_TX_CNT_CFG_REG register
* TX Counter cfg registers
*/
#define BITSCRAMBLER_TX_CNT_CFG_REG (DR_REG_BITSCRAMBLER_BASE + 0x38)
/** BITSCRAMBLER_RX_CNT_A_CFG_VALUE : R/W; bitpos: [15:0]; default: 0;
* config the tx counter a value
*/
#define BITSCRAMBLER_RX_CNT_A_CFG_VALUE 0x0000FFFFU
#define BITSCRAMBLER_RX_CNT_A_CFG_VALUE_M (BITSCRAMBLER_RX_CNT_A_CFG_VALUE_V << BITSCRAMBLER_RX_CNT_A_CFG_VALUE_S)
#define BITSCRAMBLER_RX_CNT_A_CFG_VALUE_V 0x0000FFFFU
#define BITSCRAMBLER_RX_CNT_A_CFG_VALUE_S 0
/** BITSCRAMBLER_RX_CNT_B_CFG_VALUE : R/W; bitpos: [31:16]; default: 0;
* config the tx counter b value
*/
#define BITSCRAMBLER_RX_CNT_B_CFG_VALUE 0x0000FFFFU
#define BITSCRAMBLER_RX_CNT_B_CFG_VALUE_M (BITSCRAMBLER_RX_CNT_B_CFG_VALUE_V << BITSCRAMBLER_RX_CNT_B_CFG_VALUE_S)
#define BITSCRAMBLER_RX_CNT_B_CFG_VALUE_V 0x0000FFFFU
#define BITSCRAMBLER_RX_CNT_B_CFG_VALUE_S 16
/** BITSCRAMBLER_RX_CNT_CFG_REG register
* RX Counter cfg registers
*/
#define BITSCRAMBLER_RX_CNT_CFG_REG (DR_REG_BITSCRAMBLER_BASE + 0x3c)
/** BITSCRAMBLER_TX_CNT_A_CFG_VALUE : R/W; bitpos: [15:0]; default: 0;
* config the rx counter a value
*/
#define BITSCRAMBLER_TX_CNT_A_CFG_VALUE 0x0000FFFFU
#define BITSCRAMBLER_TX_CNT_A_CFG_VALUE_M (BITSCRAMBLER_TX_CNT_A_CFG_VALUE_V << BITSCRAMBLER_TX_CNT_A_CFG_VALUE_S)
#define BITSCRAMBLER_TX_CNT_A_CFG_VALUE_V 0x0000FFFFU
#define BITSCRAMBLER_TX_CNT_A_CFG_VALUE_S 0
/** BITSCRAMBLER_TX_CNT_B_CFG_VALUE : R/W; bitpos: [31:16]; default: 0;
* config the rx counter b value
*/
#define BITSCRAMBLER_TX_CNT_B_CFG_VALUE 0x0000FFFFU
#define BITSCRAMBLER_TX_CNT_B_CFG_VALUE_M (BITSCRAMBLER_TX_CNT_B_CFG_VALUE_V << BITSCRAMBLER_TX_CNT_B_CFG_VALUE_S)
#define BITSCRAMBLER_TX_CNT_B_CFG_VALUE_V 0x0000FFFFU
#define BITSCRAMBLER_TX_CNT_B_CFG_VALUE_S 16
/** BITSCRAMBLER_TX_CNT_STATE_REG register
* TX Counter state registers
*/
#define BITSCRAMBLER_TX_CNT_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x40)
/** BITSCRAMBLER_RX_CNT_A_VALUE : RO; bitpos: [15:0]; default: 0;
* read the tx counter a value
*/
#define BITSCRAMBLER_RX_CNT_A_VALUE 0x0000FFFFU
#define BITSCRAMBLER_RX_CNT_A_VALUE_M (BITSCRAMBLER_RX_CNT_A_VALUE_V << BITSCRAMBLER_RX_CNT_A_VALUE_S)
#define BITSCRAMBLER_RX_CNT_A_VALUE_V 0x0000FFFFU
#define BITSCRAMBLER_RX_CNT_A_VALUE_S 0
/** BITSCRAMBLER_RX_CNT_B_VALUE : RO; bitpos: [31:16]; default: 0;
* read the tx counter b value
*/
#define BITSCRAMBLER_RX_CNT_B_VALUE 0x0000FFFFU
#define BITSCRAMBLER_RX_CNT_B_VALUE_M (BITSCRAMBLER_RX_CNT_B_VALUE_V << BITSCRAMBLER_RX_CNT_B_VALUE_S)
#define BITSCRAMBLER_RX_CNT_B_VALUE_V 0x0000FFFFU
#define BITSCRAMBLER_RX_CNT_B_VALUE_S 16
/** BITSCRAMBLER_RX_CNT_STATE_REG register
* RX Counter state registers
*/
#define BITSCRAMBLER_RX_CNT_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x44)
/** BITSCRAMBLER_TX_CNT_A_VALUE : RO; bitpos: [15:0]; default: 0;
* read the rx counter a value
*/
#define BITSCRAMBLER_TX_CNT_A_VALUE 0x0000FFFFU
#define BITSCRAMBLER_TX_CNT_A_VALUE_M (BITSCRAMBLER_TX_CNT_A_VALUE_V << BITSCRAMBLER_TX_CNT_A_VALUE_S)
#define BITSCRAMBLER_TX_CNT_A_VALUE_V 0x0000FFFFU
#define BITSCRAMBLER_TX_CNT_A_VALUE_S 0
/** BITSCRAMBLER_TX_CNT_B_VALUE : RO; bitpos: [31:16]; default: 0;
* read the rx counter b value
*/
#define BITSCRAMBLER_TX_CNT_B_VALUE 0x0000FFFFU
#define BITSCRAMBLER_TX_CNT_B_VALUE_M (BITSCRAMBLER_TX_CNT_B_VALUE_V << BITSCRAMBLER_TX_CNT_B_VALUE_S)
#define BITSCRAMBLER_TX_CNT_B_VALUE_V 0x0000FFFFU
#define BITSCRAMBLER_TX_CNT_B_VALUE_S 16
/** BITSCRAMBLER_SYS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
#define BITSCRAMBLER_LOOP_MODE (BIT(0))
#define BITSCRAMBLER_LOOP_MODE_M (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
#define BITSCRAMBLER_LOOP_MODE_V 0x00000001U
#define BITSCRAMBLER_LOOP_MODE_S 0
/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
* Write this bit to enable the configuration register clock to be always-on. 0: turn
* on during access, 1: always-on.
*/
#define BITSCRAMBLER_CLK_EN (BIT(31))
#define BITSCRAMBLER_CLK_EN_M (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
#define BITSCRAMBLER_CLK_EN_V 0x00000001U
#define BITSCRAMBLER_CLK_EN_S 31
/** BITSCRAMBLER_VERSION_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 38801776;
* Reserved
*/
#define BITSCRAMBLER_BITSCRAMBLER_VER 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_M (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
#define BITSCRAMBLER_BITSCRAMBLER_VER_V 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/bitscrambler_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t tx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_tx_inst_cfg0_reg_t;
/** Type of tx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
uint32_t tx_inst:32;
};
uint32_t val;
} bitscrambler_tx_inst_cfg1_reg_t;
/** Type of rx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t rx_inst_idx:3;
/** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t rx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_rx_inst_cfg0_reg_t;
/** Type of rx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
uint32_t rx_inst:32;
};
uint32_t val;
} bitscrambler_rx_inst_cfg1_reg_t;
/** Type of tx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
uint32_t tx_lut_idx:11;
/** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t tx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_tx_lut_cfg0_reg_t;
/** Type of tx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
uint32_t tx_lut:32;
};
uint32_t val;
} bitscrambler_tx_lut_cfg1_reg_t;
/** Type of rx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
uint32_t rx_lut_idx:11;
/** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t rx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_rx_lut_cfg0_reg_t;
/** Type of rx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
uint32_t rx_lut:32;
};
uint32_t val;
} bitscrambler_rx_lut_cfg1_reg_t;
/** Group: Configuration registers */
/** Type of tx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t tx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_tx_tailing_bits_reg_t;
/** Type of rx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t rx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_rx_tailing_bits_reg_t;
/** Type of tx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
uint32_t tx_ena:1;
/** tx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
uint32_t tx_pause:1;
/** tx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
uint32_t tx_halt:1;
/** tx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
uint32_t tx_eof_mode:1;
/** tx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t tx_cond_mode:1;
/** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
uint32_t tx_fetch_mode:1;
/** tx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t tx_halt_mode:1;
/** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t tx_rd_dummy:1;
/** tx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
uint32_t tx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_tx_ctrl_reg_t;
/** Type of rx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
uint32_t rx_ena:1;
/** rx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
uint32_t rx_pause:1;
/** rx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
uint32_t rx_halt:1;
/** rx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
uint32_t rx_eof_mode:1;
/** rx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t rx_cond_mode:1;
/** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
uint32_t rx_fetch_mode:1;
/** rx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t rx_halt_mode:1;
/** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t rx_rd_dummy:1;
/** rx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
uint32_t rx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_rx_ctrl_reg_t;
/** Type of sys register
* Control and configuration registers
*/
typedef union {
struct {
/** loop_mode : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
uint32_t loop_mode:1;
uint32_t reserved_1:30;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Write this bit to enable the configuration register clock to be always-on. 0: turn
* on during access, 1: always-on.
*/
uint32_t clk_en:1;
};
uint32_t val;
} bitscrambler_sys_reg_t;
/** Group: Status registers */
/** Type of tx_state register
* Status registers
*/
typedef union {
struct {
/** tx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
uint32_t tx_in_idle:1;
/** tx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
uint32_t tx_in_run:1;
/** tx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
uint32_t tx_in_wait:1;
/** tx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
uint32_t tx_in_pause:1;
/** tx_fifo_empty : RO; bitpos: [4]; default: 1;
* represents the bitscrambler tx fifo in empty state
*/
uint32_t tx_fifo_empty:1;
/** tx_crc_rdy : RO; bitpos: [5]; default: 0;
* represents the crc calculate result of bitscrambler tx path is ready
*/
uint32_t tx_crc_rdy:1;
uint32_t reserved_6:10;
/** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
uint32_t tx_eof_get_cnt:14;
/** tx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
uint32_t tx_eof_overload:1;
/** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
uint32_t tx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_tx_state_reg_t;
/** Type of rx_state register
* Status registers
*/
typedef union {
struct {
/** rx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
uint32_t rx_in_idle:1;
/** rx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
uint32_t rx_in_run:1;
/** rx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
uint32_t rx_in_wait:1;
/** rx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
uint32_t rx_in_pause:1;
/** rx_fifo_full : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
uint32_t rx_fifo_full:1;
/** rx_crc_rdy : RO; bitpos: [5]; default: 0;
* represents the crc calculate result of bitscrambler rx path is ready
*/
uint32_t rx_crc_rdy:1;
uint32_t reserved_6:10;
/** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
uint32_t rx_eof_get_cnt:14;
/** rx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
uint32_t rx_eof_overload:1;
/** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
uint32_t rx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_rx_state_reg_t;
/** Group: RX Counter cfg registers */
/** Type of tx_cnt_cfg register
* TX Counter cfg registers
*/
typedef union {
struct {
/** rx_cnt_a_cfg_value : R/W; bitpos: [15:0]; default: 0;
* config the tx counter a value
*/
uint32_t rx_cnt_a_cfg_value:16;
/** rx_cnt_b_cfg_value : R/W; bitpos: [31:16]; default: 0;
* config the tx counter b value
*/
uint32_t rx_cnt_b_cfg_value:16;
};
uint32_t val;
} bitscrambler_tx_cnt_cfg_reg_t;
/** Group: TX_Counter cfg registers */
/** Type of rx_cnt_cfg register
* RX Counter cfg registers
*/
typedef union {
struct {
/** tx_cnt_a_cfg_value : R/W; bitpos: [15:0]; default: 0;
* config the rx counter a value
*/
uint32_t tx_cnt_a_cfg_value:16;
/** tx_cnt_b_cfg_value : R/W; bitpos: [31:16]; default: 0;
* config the rx counter b value
*/
uint32_t tx_cnt_b_cfg_value:16;
};
uint32_t val;
} bitscrambler_rx_cnt_cfg_reg_t;
/** Group: RX Counter status registers */
/** Type of tx_cnt_state register
* TX Counter state registers
*/
typedef union {
struct {
/** rx_cnt_a_value : RO; bitpos: [15:0]; default: 0;
* read the tx counter a value
*/
uint32_t rx_cnt_a_value:16;
/** rx_cnt_b_value : RO; bitpos: [31:16]; default: 0;
* read the tx counter b value
*/
uint32_t rx_cnt_b_value:16;
};
uint32_t val;
} bitscrambler_tx_cnt_state_reg_t;
/** Group: TX_Counter status registers */
/** Type of rx_cnt_state register
* RX Counter state registers
*/
typedef union {
struct {
/** tx_cnt_a_value : RO; bitpos: [15:0]; default: 0;
* read the rx counter a value
*/
uint32_t tx_cnt_a_value:16;
/** tx_cnt_b_value : RO; bitpos: [31:16]; default: 0;
* read the rx counter b value
*/
uint32_t tx_cnt_b_value:16;
};
uint32_t val;
} bitscrambler_rx_cnt_state_reg_t;
/** Group: Version register */
/** Type of version register
* Control and configuration registers
*/
typedef union {
struct {
/** bitscrambler_ver : R/W; bitpos: [27:0]; default: 38801776;
* Reserved
*/
uint32_t bitscrambler_ver:28;
uint32_t reserved_28:4;
};
uint32_t val;
} bitscrambler_version_reg_t;
typedef struct {
volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
volatile bitscrambler_tx_state_reg_t tx_state;
volatile bitscrambler_rx_state_reg_t rx_state;
volatile bitscrambler_tx_cnt_cfg_reg_t tx_cnt_cfg;
volatile bitscrambler_rx_cnt_cfg_reg_t rx_cnt_cfg;
volatile bitscrambler_tx_cnt_state_reg_t tx_cnt_state;
volatile bitscrambler_rx_cnt_state_reg_t rx_cnt_state;
uint32_t reserved_048[44];
volatile bitscrambler_sys_reg_t sys;
volatile bitscrambler_version_reg_t version;
} bitscrambler_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** CNNT_SYS_VER_DATE_REG register
* NA
*/
#define CNNT_SYS_VER_DATE_REG (DR_REG_CNNT_BASE + 0x0)
/** CNNT_SYS_VER_DATE : R/W; bitpos: [31:0]; default: 539298086;
* NA
*/
#define CNNT_SYS_VER_DATE 0xFFFFFFFFU
#define CNNT_SYS_VER_DATE_M (CNNT_SYS_VER_DATE_V << CNNT_SYS_VER_DATE_S)
#define CNNT_SYS_VER_DATE_V 0xFFFFFFFFU
#define CNNT_SYS_VER_DATE_S 0
/** CNNT_CLK_EN_REG register
* NA
*/
#define CNNT_CLK_EN_REG (DR_REG_CNNT_BASE + 0x4)
/** CNNT_SYS_DATE : R/W; bitpos: [30:0]; default: 38826240;
* need_des
*/
#define CNNT_SYS_DATE 0x7FFFFFFFU
#define CNNT_SYS_DATE_M (CNNT_SYS_DATE_V << CNNT_SYS_DATE_S)
#define CNNT_SYS_DATE_V 0x7FFFFFFFU
#define CNNT_SYS_DATE_S 0
/** CNNT_SYS_CLK_EN : R/W; bitpos: [31]; default: 0;
* NA
*/
#define CNNT_SYS_CLK_EN (BIT(31))
#define CNNT_SYS_CLK_EN_M (CNNT_SYS_CLK_EN_V << CNNT_SYS_CLK_EN_S)
#define CNNT_SYS_CLK_EN_V 0x00000001U
#define CNNT_SYS_CLK_EN_S 31
/** CNNT_SYS_SDMMC_MEM_LP_CTRL_REG register
* HP CORE0 & HP CORE1 memory power control register
*/
#define CNNT_SYS_SDMMC_MEM_LP_CTRL_REG (DR_REG_CNNT_BASE + 0x10)
/** CNNT_SYS_SDMMC_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
* Configures sdmmc memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
#define CNNT_SYS_SDMMC_MEM_LP_MODE 0x00000003U
#define CNNT_SYS_SDMMC_MEM_LP_MODE_M (CNNT_SYS_SDMMC_MEM_LP_MODE_V << CNNT_SYS_SDMMC_MEM_LP_MODE_S)
#define CNNT_SYS_SDMMC_MEM_LP_MODE_V 0x00000003U
#define CNNT_SYS_SDMMC_MEM_LP_MODE_S 0
/** CNNT_SYS_SDMMC_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
* Set this bit to power down sdmmc memory.
*/
#define CNNT_SYS_SDMMC_MEM_LP_EN (BIT(2))
#define CNNT_SYS_SDMMC_MEM_LP_EN_M (CNNT_SYS_SDMMC_MEM_LP_EN_V << CNNT_SYS_SDMMC_MEM_LP_EN_S)
#define CNNT_SYS_SDMMC_MEM_LP_EN_V 0x00000001U
#define CNNT_SYS_SDMMC_MEM_LP_EN_S 2
/** CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control sdmmc memory, disable hardware control.
*/
#define CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL (BIT(3))
#define CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_M (CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_V << CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_S)
#define CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_V 0x00000001U
#define CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_S 3
/** CNNT_SYS_USB_OTGHS_MEM_LP_CTRL_REG register
* HP CORE0 & HP CORE1 memory power control register
*/
#define CNNT_SYS_USB_OTGHS_MEM_LP_CTRL_REG (DR_REG_CNNT_BASE + 0x14)
/** CNNT_SYS_USB_OTGHS_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
* Configures usb_otghs memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
#define CNNT_SYS_USB_OTGHS_MEM_LP_MODE 0x00000003U
#define CNNT_SYS_USB_OTGHS_MEM_LP_MODE_M (CNNT_SYS_USB_OTGHS_MEM_LP_MODE_V << CNNT_SYS_USB_OTGHS_MEM_LP_MODE_S)
#define CNNT_SYS_USB_OTGHS_MEM_LP_MODE_V 0x00000003U
#define CNNT_SYS_USB_OTGHS_MEM_LP_MODE_S 0
/** CNNT_SYS_USB_OTGHS_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
* Set this bit to power down usb_otghs memory.
*/
#define CNNT_SYS_USB_OTGHS_MEM_LP_EN (BIT(2))
#define CNNT_SYS_USB_OTGHS_MEM_LP_EN_M (CNNT_SYS_USB_OTGHS_MEM_LP_EN_V << CNNT_SYS_USB_OTGHS_MEM_LP_EN_S)
#define CNNT_SYS_USB_OTGHS_MEM_LP_EN_V 0x00000001U
#define CNNT_SYS_USB_OTGHS_MEM_LP_EN_S 2
/** CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control usb_otghs memory, disable hardware control.
*/
#define CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL (BIT(3))
#define CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_M (CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_V << CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_S)
#define CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_V 0x00000001U
#define CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_S 3
/** CNNT_SYS_USB_DEVICE_MEM_LP_CTRL_REG register
* HP CORE0 & HP CORE1 memory power control register
*/
#define CNNT_SYS_USB_DEVICE_MEM_LP_CTRL_REG (DR_REG_CNNT_BASE + 0x18)
/** CNNT_SYS_USB_DEVICE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
* Configures usb_device memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
#define CNNT_SYS_USB_DEVICE_MEM_LP_MODE 0x00000003U
#define CNNT_SYS_USB_DEVICE_MEM_LP_MODE_M (CNNT_SYS_USB_DEVICE_MEM_LP_MODE_V << CNNT_SYS_USB_DEVICE_MEM_LP_MODE_S)
#define CNNT_SYS_USB_DEVICE_MEM_LP_MODE_V 0x00000003U
#define CNNT_SYS_USB_DEVICE_MEM_LP_MODE_S 0
/** CNNT_SYS_USB_DEVICE_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
* Set this bit to power down usb_device memory.
*/
#define CNNT_SYS_USB_DEVICE_MEM_LP_EN (BIT(2))
#define CNNT_SYS_USB_DEVICE_MEM_LP_EN_M (CNNT_SYS_USB_DEVICE_MEM_LP_EN_V << CNNT_SYS_USB_DEVICE_MEM_LP_EN_S)
#define CNNT_SYS_USB_DEVICE_MEM_LP_EN_V 0x00000001U
#define CNNT_SYS_USB_DEVICE_MEM_LP_EN_S 2
/** CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control usb_device (serial jtag) memory, disable
* hardware control.
*/
#define CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL (BIT(3))
#define CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_M (CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_V << CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_S)
#define CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_V 0x00000001U
#define CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_S 3
/** CNNT_SYS_GMAC_MEM_LP_CTRL_REG register
* HP CORE0 & HP CORE1 memory power control register
*/
#define CNNT_SYS_GMAC_MEM_LP_CTRL_REG (DR_REG_CNNT_BASE + 0x1c)
/** CNNT_SYS_GMAC_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
* Configures gmac memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
#define CNNT_SYS_GMAC_MEM_LP_MODE 0x00000003U
#define CNNT_SYS_GMAC_MEM_LP_MODE_M (CNNT_SYS_GMAC_MEM_LP_MODE_V << CNNT_SYS_GMAC_MEM_LP_MODE_S)
#define CNNT_SYS_GMAC_MEM_LP_MODE_V 0x00000003U
#define CNNT_SYS_GMAC_MEM_LP_MODE_S 0
/** CNNT_SYS_GMAC_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
* Set this bit to power down gmac memory.
*/
#define CNNT_SYS_GMAC_MEM_LP_EN (BIT(2))
#define CNNT_SYS_GMAC_MEM_LP_EN_M (CNNT_SYS_GMAC_MEM_LP_EN_V << CNNT_SYS_GMAC_MEM_LP_EN_S)
#define CNNT_SYS_GMAC_MEM_LP_EN_V 0x00000001U
#define CNNT_SYS_GMAC_MEM_LP_EN_S 2
/** CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control gmac memory, disable hardware control.
*/
#define CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL (BIT(3))
#define CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_M (CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_V << CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_S)
#define CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_V 0x00000001U
#define CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_S 3
/** CNNT_SYS_SPRF_MEM_AUX_CTRL_REG register
* need_des
*/
#define CNNT_SYS_SPRF_MEM_AUX_CTRL_REG (DR_REG_CNNT_BASE + 0x20)
/** CNNT_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
#define CNNT_SYS_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define CNNT_SYS_SPRF_MEM_AUX_CTRL_M (CNNT_SYS_SPRF_MEM_AUX_CTRL_V << CNNT_SYS_SPRF_MEM_AUX_CTRL_S)
#define CNNT_SYS_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define CNNT_SYS_SPRF_MEM_AUX_CTRL_S 0
/** CNNT_SYS_SDPRF_MEM_AUX_CTRL_REG register
* need_des
*/
#define CNNT_SYS_SDPRF_MEM_AUX_CTRL_REG (DR_REG_CNNT_BASE + 0x24)
/** CNNT_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
#define CNNT_SYS_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define CNNT_SYS_SDPRF_MEM_AUX_CTRL_M (CNNT_SYS_SDPRF_MEM_AUX_CTRL_V << CNNT_SYS_SDPRF_MEM_AUX_CTRL_S)
#define CNNT_SYS_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define CNNT_SYS_SDPRF_MEM_AUX_CTRL_S 0
/** CNNT_SYS_HP_PAD_ULPI_CTRL_REG register
* HP Clock Control Register.
*/
#define CNNT_SYS_HP_PAD_ULPI_CTRL_REG (DR_REG_CNNT_BASE + 0x28)
/** CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN : R/W; bitpos: [30]; default: 0;
* PAD ULPI Clock output inv Enable, valid only when CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN
* is 1.
*/
#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN (BIT(30))
#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_M (CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_V << CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_S)
#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_V 0x00000001U
#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_S 30
/** CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN : R/W; bitpos: [31]; default: 0;
* PAD ULPI Clock output Enable. 0: pad_ulpi_clk is used as input clk, 1: pad_ulpi_clk
* is used as output clk
*/
#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN (BIT(31))
#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_M (CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_V << CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_S)
#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_V 0x00000001U
#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_S 31
/** CNNT_SYS_USB_CLK_CTRL_REG register
* HP USB Clock Reset Control Register.
*/
#define CNNT_SYS_USB_CLK_CTRL_REG (DR_REG_CNNT_BASE + 0x2c)
/** CNNT_SYS_USB_48M_DIV_NUM : R/W; bitpos: [15:8]; default: 9;
* usb 480m to 25m divide number.
*/
#define CNNT_SYS_USB_48M_DIV_NUM 0x000000FFU
#define CNNT_SYS_USB_48M_DIV_NUM_M (CNNT_SYS_USB_48M_DIV_NUM_V << CNNT_SYS_USB_48M_DIV_NUM_S)
#define CNNT_SYS_USB_48M_DIV_NUM_V 0x000000FFU
#define CNNT_SYS_USB_48M_DIV_NUM_S 8
/** CNNT_SYS_USB_25M_DIV_NUM : R/W; bitpos: [23:16]; default: 19;
* usb 500m to 25m divide number.
*/
#define CNNT_SYS_USB_25M_DIV_NUM 0x000000FFU
#define CNNT_SYS_USB_25M_DIV_NUM_M (CNNT_SYS_USB_25M_DIV_NUM_V << CNNT_SYS_USB_25M_DIV_NUM_S)
#define CNNT_SYS_USB_25M_DIV_NUM_V 0x000000FFU
#define CNNT_SYS_USB_25M_DIV_NUM_S 16
/** CNNT_SYS_USB_12M_DIV_NUM : R/W; bitpos: [31:24]; default: 39;
* usb 480m to 12m divide number.
*/
#define CNNT_SYS_USB_12M_DIV_NUM 0x000000FFU
#define CNNT_SYS_USB_12M_DIV_NUM_M (CNNT_SYS_USB_12M_DIV_NUM_V << CNNT_SYS_USB_12M_DIV_NUM_S)
#define CNNT_SYS_USB_12M_DIV_NUM_V 0x000000FFU
#define CNNT_SYS_USB_12M_DIV_NUM_S 24
/** CNNT_SYS_USB_OTG20_CTRL_REG register
* HP USB Clock Reset Control Register.
*/
#define CNNT_SYS_USB_OTG20_CTRL_REG (DR_REG_CNNT_BASE + 0x30)
/** CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN : R/W; bitpos: [23]; default: 1;
* usb otg20 utmifs clk enable.
*/
#define CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN (BIT(23))
#define CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_M (CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_V << CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_S)
#define CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_V 0x00000001U
#define CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_S 23
/** CNNT_SYS_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [24]; default: 0;
* usb otg20 ulpi clk enable.
*/
#define CNNT_SYS_USB_OTG20_ULPI_CLK_EN (BIT(24))
#define CNNT_SYS_USB_OTG20_ULPI_CLK_EN_M (CNNT_SYS_USB_OTG20_ULPI_CLK_EN_V << CNNT_SYS_USB_OTG20_ULPI_CLK_EN_S)
#define CNNT_SYS_USB_OTG20_ULPI_CLK_EN_V 0x00000001U
#define CNNT_SYS_USB_OTG20_ULPI_CLK_EN_S 24
/** CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [26:25]; default: 0;
* usb otg20 hs phy src sel. 2''d0: 12m, 2''d1: 25m, 2''d2: pad_hsphy_refclk.'
*/
#define CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL 0x00000003U
#define CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_M (CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_V << CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_S)
#define CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_V 0x00000003U
#define CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_S 25
/** CNNT_SYS_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [27]; default: 0;
* usb otg20 hs phy refclk enable.
*/
#define CNNT_SYS_USB_OTG20_PHYREF_CLK_EN (BIT(27))
#define CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_M (CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_V << CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_S)
#define CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_V 0x00000001U
#define CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_S 27
/** CNNT_SYS_USB_OTG20_PHY_RST_EN : R/W; bitpos: [29]; default: 1;
* usb otg20 phy reset en
*/
#define CNNT_SYS_USB_OTG20_PHY_RST_EN (BIT(29))
#define CNNT_SYS_USB_OTG20_PHY_RST_EN_M (CNNT_SYS_USB_OTG20_PHY_RST_EN_V << CNNT_SYS_USB_OTG20_PHY_RST_EN_S)
#define CNNT_SYS_USB_OTG20_PHY_RST_EN_V 0x00000001U
#define CNNT_SYS_USB_OTG20_PHY_RST_EN_S 29
/** CNNT_SYS_USB_OTG20_AHB_RST_EN : R/W; bitpos: [30]; default: 1;
* usb otg20 ahb reset en
*/
#define CNNT_SYS_USB_OTG20_AHB_RST_EN (BIT(30))
#define CNNT_SYS_USB_OTG20_AHB_RST_EN_M (CNNT_SYS_USB_OTG20_AHB_RST_EN_V << CNNT_SYS_USB_OTG20_AHB_RST_EN_S)
#define CNNT_SYS_USB_OTG20_AHB_RST_EN_V 0x00000001U
#define CNNT_SYS_USB_OTG20_AHB_RST_EN_S 30
/** CNNT_SYS_USB_OTG20_APB_RST_EN : R/W; bitpos: [31]; default: 1;
* usb otg20 apb reset en
*/
#define CNNT_SYS_USB_OTG20_APB_RST_EN (BIT(31))
#define CNNT_SYS_USB_OTG20_APB_RST_EN_M (CNNT_SYS_USB_OTG20_APB_RST_EN_V << CNNT_SYS_USB_OTG20_APB_RST_EN_S)
#define CNNT_SYS_USB_OTG20_APB_RST_EN_V 0x00000001U
#define CNNT_SYS_USB_OTG20_APB_RST_EN_S 31
/** CNNT_SYS_HP_USB_DEVICE_CTRL_REG register
* HP USB Clock Reset Control Register.
*/
#define CNNT_SYS_HP_USB_DEVICE_CTRL_REG (DR_REG_CNNT_BASE + 0x34)
/** CNNT_SYS_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [30]; default: 1;
* usb device fs phy clock enable.
*/
#define CNNT_SYS_USB_DEVICE_48M_CLK_EN (BIT(30))
#define CNNT_SYS_USB_DEVICE_48M_CLK_EN_M (CNNT_SYS_USB_DEVICE_48M_CLK_EN_V << CNNT_SYS_USB_DEVICE_48M_CLK_EN_S)
#define CNNT_SYS_USB_DEVICE_48M_CLK_EN_V 0x00000001U
#define CNNT_SYS_USB_DEVICE_48M_CLK_EN_S 30
/** CNNT_SYS_USB_DEVICE_RST_EN : R/W; bitpos: [31]; default: 0;
* usb device reset en
*/
#define CNNT_SYS_USB_DEVICE_RST_EN (BIT(31))
#define CNNT_SYS_USB_DEVICE_RST_EN_M (CNNT_SYS_USB_DEVICE_RST_EN_V << CNNT_SYS_USB_DEVICE_RST_EN_S)
#define CNNT_SYS_USB_DEVICE_RST_EN_V 0x00000001U
#define CNNT_SYS_USB_DEVICE_RST_EN_S 31
/** CNNT_SYS_HP_SDMMC_CTRL_REG register
* need_des
*/
#define CNNT_SYS_HP_SDMMC_CTRL_REG (DR_REG_CNNT_BASE + 0x38)
/** CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN : R/W; bitpos: [29]; default: 0;
* this reg is used to enable the post_write function of the ahb2axi bridge for sdmmc
*/
#define CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN (BIT(29))
#define CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_M (CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_V << CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_S)
#define CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_V 0x00000001U
#define CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_S 29
/** CNNT_SYS_SDMMC_RST_EN : R/W; bitpos: [30]; default: 0;
* hp sdmmc reset en
*/
#define CNNT_SYS_SDMMC_RST_EN (BIT(30))
#define CNNT_SYS_SDMMC_RST_EN_M (CNNT_SYS_SDMMC_RST_EN_V << CNNT_SYS_SDMMC_RST_EN_S)
#define CNNT_SYS_SDMMC_RST_EN_V 0x00000001U
#define CNNT_SYS_SDMMC_RST_EN_S 30
/** CNNT_SYS_SDMMC_FORCE_NORST : R/W; bitpos: [31]; default: 0;
* hp sdmmc force norst
*/
#define CNNT_SYS_SDMMC_FORCE_NORST (BIT(31))
#define CNNT_SYS_SDMMC_FORCE_NORST_M (CNNT_SYS_SDMMC_FORCE_NORST_V << CNNT_SYS_SDMMC_FORCE_NORST_S)
#define CNNT_SYS_SDMMC_FORCE_NORST_V 0x00000001U
#define CNNT_SYS_SDMMC_FORCE_NORST_S 31
/** CNNT_SYS_HP_EMAC_CTRL_REG register
* need_des
*/
#define CNNT_SYS_HP_EMAC_CTRL_REG (DR_REG_CNNT_BASE + 0x3c)
/** CNNT_SYS_EMAC_USELESS_CLK_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_USELESS_CLK_EN (BIT(0))
#define CNNT_SYS_EMAC_USELESS_CLK_EN_M (CNNT_SYS_EMAC_USELESS_CLK_EN_V << CNNT_SYS_EMAC_USELESS_CLK_EN_S)
#define CNNT_SYS_EMAC_USELESS_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_USELESS_CLK_EN_S 0
/** CNNT_SYS_EMAC_RST_EN : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RST_EN (BIT(1))
#define CNNT_SYS_EMAC_RST_EN_M (CNNT_SYS_EMAC_RST_EN_V << CNNT_SYS_EMAC_RST_EN_S)
#define CNNT_SYS_EMAC_RST_EN_V 0x00000001U
#define CNNT_SYS_EMAC_RST_EN_S 1
/** CNNT_SYS_EMAC_FORCE_NORST : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_FORCE_NORST (BIT(2))
#define CNNT_SYS_EMAC_FORCE_NORST_M (CNNT_SYS_EMAC_FORCE_NORST_V << CNNT_SYS_EMAC_FORCE_NORST_S)
#define CNNT_SYS_EMAC_FORCE_NORST_V 0x00000001U
#define CNNT_SYS_EMAC_FORCE_NORST_S 2
/** CNNT_SYS_HP_EMAC_REF_CTRL_REG register
* need_des
*/
#define CNNT_SYS_HP_EMAC_REF_CTRL_REG (DR_REG_CNNT_BASE + 0x40)
/** CNNT_SYS_EMAC_REF_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
* select emac reference clock source. 0: mpll 500MHz, 1: cpll 300MHz.
*/
#define CNNT_SYS_EMAC_REF_CLK_SEL 0x00000003U
#define CNNT_SYS_EMAC_REF_CLK_SEL_M (CNNT_SYS_EMAC_REF_CLK_SEL_V << CNNT_SYS_EMAC_REF_CLK_SEL_S)
#define CNNT_SYS_EMAC_REF_CLK_SEL_V 0x00000003U
#define CNNT_SYS_EMAC_REF_CLK_SEL_S 0
/** CNNT_SYS_EMAC_REF_CLK_EN : R/W; bitpos: [2]; default: 0;
* Set as 1 to enable emac reference clock source selection
*/
#define CNNT_SYS_EMAC_REF_CLK_EN (BIT(2))
#define CNNT_SYS_EMAC_REF_CLK_EN_M (CNNT_SYS_EMAC_REF_CLK_EN_V << CNNT_SYS_EMAC_REF_CLK_EN_S)
#define CNNT_SYS_EMAC_REF_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_REF_CLK_EN_S 2
/** CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN : R/W; bitpos: [3]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN (BIT(3))
#define CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_M (CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_V << CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_S)
#define CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_S 3
/** CNNT_SYS_EMAC_REF_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
* Divide number of the divider which is used to divide reference clock source.
*/
#define CNNT_SYS_EMAC_REF_CLK_DIV_NUM 0x000000FFU
#define CNNT_SYS_EMAC_REF_CLK_DIV_NUM_M (CNNT_SYS_EMAC_REF_CLK_DIV_NUM_V << CNNT_SYS_EMAC_REF_CLK_DIV_NUM_S)
#define CNNT_SYS_EMAC_REF_CLK_DIV_NUM_V 0x000000FFU
#define CNNT_SYS_EMAC_REF_CLK_DIV_NUM_S 8
/** CNNT_SYS_HP_EMAC_RMII_PAD_CTRL_REG register
* need_des
*/
#define CNNT_SYS_HP_EMAC_RMII_PAD_CTRL_REG (DR_REG_CNNT_BASE + 0x44)
/** CNNT_SYS_EMAC_RMII_PAD_CLK_EN : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RMII_PAD_CLK_EN (BIT(1))
#define CNNT_SYS_EMAC_RMII_PAD_CLK_EN_M (CNNT_SYS_EMAC_RMII_PAD_CLK_EN_V << CNNT_SYS_EMAC_RMII_PAD_CLK_EN_S)
#define CNNT_SYS_EMAC_RMII_PAD_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_RMII_PAD_CLK_EN_S 1
/** CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN (BIT(2))
#define CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_M (CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_V << CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_S)
#define CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_V 0x00000001U
#define CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_S 2
/** CNNT_SYS_HP_EMAC_RMII_CTRL_REG register
* need_des
*/
#define CNNT_SYS_HP_EMAC_RMII_CTRL_REG (DR_REG_CNNT_BASE + 0x48)
/** CNNT_SYS_EMAC_RMII_CLK_SEL : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RMII_CLK_SEL (BIT(0))
#define CNNT_SYS_EMAC_RMII_CLK_SEL_M (CNNT_SYS_EMAC_RMII_CLK_SEL_V << CNNT_SYS_EMAC_RMII_CLK_SEL_S)
#define CNNT_SYS_EMAC_RMII_CLK_SEL_V 0x00000001U
#define CNNT_SYS_EMAC_RMII_CLK_SEL_S 0
/** CNNT_SYS_EMAC_RMII_CLK_EN : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RMII_CLK_EN (BIT(1))
#define CNNT_SYS_EMAC_RMII_CLK_EN_M (CNNT_SYS_EMAC_RMII_CLK_EN_V << CNNT_SYS_EMAC_RMII_CLK_EN_S)
#define CNNT_SYS_EMAC_RMII_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_RMII_CLK_EN_S 1
/** CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN (BIT(2))
#define CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_M (CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_V << CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_S)
#define CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_S 2
/** CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM : R/W; bitpos: [12:8]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM 0x0000001FU
#define CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_M (CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_V << CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_S)
#define CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_V 0x0000001FU
#define CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_S 8
/** CNNT_SYS_HP_EMAC_RX_CTRL_REG register
* need_des
*/
#define CNNT_SYS_HP_EMAC_RX_CTRL_REG (DR_REG_CNNT_BASE + 0x4c)
/** CNNT_SYS_EMAC_RX_PAD_CLK_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RX_PAD_CLK_EN (BIT(0))
#define CNNT_SYS_EMAC_RX_PAD_CLK_EN_M (CNNT_SYS_EMAC_RX_PAD_CLK_EN_V << CNNT_SYS_EMAC_RX_PAD_CLK_EN_S)
#define CNNT_SYS_EMAC_RX_PAD_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_RX_PAD_CLK_EN_S 0
/** CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN (BIT(1))
#define CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_M (CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_V << CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_S)
#define CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_V 0x00000001U
#define CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_S 1
/** CNNT_SYS_EMAC_RX_CLK_SEL : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RX_CLK_SEL (BIT(2))
#define CNNT_SYS_EMAC_RX_CLK_SEL_M (CNNT_SYS_EMAC_RX_CLK_SEL_V << CNNT_SYS_EMAC_RX_CLK_SEL_S)
#define CNNT_SYS_EMAC_RX_CLK_SEL_V 0x00000001U
#define CNNT_SYS_EMAC_RX_CLK_SEL_S 2
/** CNNT_SYS_EMAC_RX_180_CLK_EN : R/W; bitpos: [3]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_RX_180_CLK_EN (BIT(3))
#define CNNT_SYS_EMAC_RX_180_CLK_EN_M (CNNT_SYS_EMAC_RX_180_CLK_EN_V << CNNT_SYS_EMAC_RX_180_CLK_EN_S)
#define CNNT_SYS_EMAC_RX_180_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_RX_180_CLK_EN_S 3
/** CNNT_SYS_HP_EMAC_TX_CTRL_REG register
* need_des
*/
#define CNNT_SYS_HP_EMAC_TX_CTRL_REG (DR_REG_CNNT_BASE + 0x50)
/** CNNT_SYS_EMAC_TX_PAD_CLK_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_TX_PAD_CLK_EN (BIT(0))
#define CNNT_SYS_EMAC_TX_PAD_CLK_EN_M (CNNT_SYS_EMAC_TX_PAD_CLK_EN_V << CNNT_SYS_EMAC_TX_PAD_CLK_EN_S)
#define CNNT_SYS_EMAC_TX_PAD_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_TX_PAD_CLK_EN_S 0
/** CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN (BIT(1))
#define CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_M (CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_V << CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_S)
#define CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_V 0x00000001U
#define CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_S 1
/** CNNT_SYS_EMAC_TX_CLK_SEL : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_TX_CLK_SEL (BIT(2))
#define CNNT_SYS_EMAC_TX_CLK_SEL_M (CNNT_SYS_EMAC_TX_CLK_SEL_V << CNNT_SYS_EMAC_TX_CLK_SEL_S)
#define CNNT_SYS_EMAC_TX_CLK_SEL_V 0x00000001U
#define CNNT_SYS_EMAC_TX_CLK_SEL_S 2
/** CNNT_SYS_EMAC_TX_180_CLK_EN : R/W; bitpos: [3]; default: 0;
* need_des
*/
#define CNNT_SYS_EMAC_TX_180_CLK_EN (BIT(3))
#define CNNT_SYS_EMAC_TX_180_CLK_EN_M (CNNT_SYS_EMAC_TX_180_CLK_EN_V << CNNT_SYS_EMAC_TX_180_CLK_EN_S)
#define CNNT_SYS_EMAC_TX_180_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_TX_180_CLK_EN_S 3
/** CNNT_SYS_HP_EMAC_PTP_CTRL_REG register
* need_des
*/
#define CNNT_SYS_HP_EMAC_PTP_CTRL_REG (DR_REG_CNNT_BASE + 0x54)
/** CNNT_SYS_EMAC_PTP_REF_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set as 1 to enable emac PTP clock source selection.
*/
#define CNNT_SYS_EMAC_PTP_REF_CLK_EN (BIT(0))
#define CNNT_SYS_EMAC_PTP_REF_CLK_EN_M (CNNT_SYS_EMAC_PTP_REF_CLK_EN_V << CNNT_SYS_EMAC_PTP_REF_CLK_EN_S)
#define CNNT_SYS_EMAC_PTP_REF_CLK_EN_V 0x00000001U
#define CNNT_SYS_EMAC_PTP_REF_CLK_EN_S 0
/** CNNT_SYS_EMAC_PTP_REF_CLK_SEL : R/W; bitpos: [1]; default: 0;
* select emac PTP clock source. 0: xtal clock, 1: 80MHz internal clock.
*/
#define CNNT_SYS_EMAC_PTP_REF_CLK_SEL (BIT(1))
#define CNNT_SYS_EMAC_PTP_REF_CLK_SEL_M (CNNT_SYS_EMAC_PTP_REF_CLK_SEL_V << CNNT_SYS_EMAC_PTP_REF_CLK_SEL_S)
#define CNNT_SYS_EMAC_PTP_REF_CLK_SEL_V 0x00000001U
#define CNNT_SYS_EMAC_PTP_REF_CLK_SEL_S 1
/** CNNT_SYS_CNNT_IOMUX_CTRL0_REG register
* need_des
*/
#define CNNT_SYS_CNNT_IOMUX_CTRL0_REG (DR_REG_CNNT_BASE + 0x58)
/** CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN : R/W; bitpos: [0]; default: 0;
* cnnt_iomux rst en
*/
#define CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN (BIT(0))
#define CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_M (CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_V << CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_S)
#define CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_V 0x00000001U
#define CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_S 0
/** CNNT_SYS_SPRAM_MEM_AUX_CTRL_REG register
* need_des
*/
#define CNNT_SYS_SPRAM_MEM_AUX_CTRL_REG (DR_REG_CNNT_BASE + 0x5c)
/** CNNT_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
#define CNNT_SYS_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define CNNT_SYS_SPRAM_MEM_AUX_CTRL_M (CNNT_SYS_SPRAM_MEM_AUX_CTRL_V << CNNT_SYS_SPRAM_MEM_AUX_CTRL_S)
#define CNNT_SYS_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define CNNT_SYS_SPRAM_MEM_AUX_CTRL_S 0
/** CNNT_SYS_GMAC_CTRL0_REG register
* N/A
*/
#define CNNT_SYS_GMAC_CTRL0_REG (DR_REG_CNNT_BASE + 0x60)
/** CNNT_SYS_PTP_PPS : RO; bitpos: [0]; default: 0;
* N/A
*/
#define CNNT_SYS_PTP_PPS (BIT(0))
#define CNNT_SYS_PTP_PPS_M (CNNT_SYS_PTP_PPS_V << CNNT_SYS_PTP_PPS_S)
#define CNNT_SYS_PTP_PPS_V 0x00000001U
#define CNNT_SYS_PTP_PPS_S 0
/** CNNT_SYS_SBD_FLOWCTRL : R/W; bitpos: [1]; default: 0;
* N/A
*/
#define CNNT_SYS_SBD_FLOWCTRL (BIT(1))
#define CNNT_SYS_SBD_FLOWCTRL_M (CNNT_SYS_SBD_FLOWCTRL_V << CNNT_SYS_SBD_FLOWCTRL_S)
#define CNNT_SYS_SBD_FLOWCTRL_V 0x00000001U
#define CNNT_SYS_SBD_FLOWCTRL_S 1
/** CNNT_SYS_PHY_INTF_SEL : R/W; bitpos: [4:2]; default: 0;
* N/A
*/
#define CNNT_SYS_PHY_INTF_SEL 0x00000007U
#define CNNT_SYS_PHY_INTF_SEL_M (CNNT_SYS_PHY_INTF_SEL_V << CNNT_SYS_PHY_INTF_SEL_S)
#define CNNT_SYS_PHY_INTF_SEL_V 0x00000007U
#define CNNT_SYS_PHY_INTF_SEL_S 2
/** CNNT_SYS_GMAC_MEM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
* N/A
*/
#define CNNT_SYS_GMAC_MEM_CLK_FORCE_ON (BIT(5))
#define CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_M (CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_V << CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_S)
#define CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_V 0x00000001U
#define CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_S 5
/** CNNT_SYS_GMAC_RST_CLK_TX_N : RO; bitpos: [6]; default: 0;
* N/A
*/
#define CNNT_SYS_GMAC_RST_CLK_TX_N (BIT(6))
#define CNNT_SYS_GMAC_RST_CLK_TX_N_M (CNNT_SYS_GMAC_RST_CLK_TX_N_V << CNNT_SYS_GMAC_RST_CLK_TX_N_S)
#define CNNT_SYS_GMAC_RST_CLK_TX_N_V 0x00000001U
#define CNNT_SYS_GMAC_RST_CLK_TX_N_S 6
/** CNNT_SYS_GMAC_RST_CLK_RX_N : RO; bitpos: [7]; default: 0;
* N/A
*/
#define CNNT_SYS_GMAC_RST_CLK_RX_N (BIT(7))
#define CNNT_SYS_GMAC_RST_CLK_RX_N_M (CNNT_SYS_GMAC_RST_CLK_RX_N_V << CNNT_SYS_GMAC_RST_CLK_RX_N_S)
#define CNNT_SYS_GMAC_RST_CLK_RX_N_V 0x00000001U
#define CNNT_SYS_GMAC_RST_CLK_RX_N_S 7
/** CNNT_SYS_GMAC_CACTIVE : RO; bitpos: [8]; default: 0;
* this signal indicates that the GMAC-AXI requires its clock signal , 1 : required ,0
* : not required
*/
#define CNNT_SYS_GMAC_CACTIVE (BIT(8))
#define CNNT_SYS_GMAC_CACTIVE_M (CNNT_SYS_GMAC_CACTIVE_V << CNNT_SYS_GMAC_CACTIVE_S)
#define CNNT_SYS_GMAC_CACTIVE_V 0x00000001U
#define CNNT_SYS_GMAC_CACTIVE_S 8
/** CNNT_SYS_GMAC_CSYSACK : RO; bitpos: [9]; default: 0;
* this signal is the acknowledgement from the GMAC-AXI to the system for low-power
* request ,active high
*/
#define CNNT_SYS_GMAC_CSYSACK (BIT(9))
#define CNNT_SYS_GMAC_CSYSACK_M (CNNT_SYS_GMAC_CSYSACK_V << CNNT_SYS_GMAC_CSYSACK_S)
#define CNNT_SYS_GMAC_CSYSACK_V 0x00000001U
#define CNNT_SYS_GMAC_CSYSACK_S 9
/** CNNT_SYS_GMAC_CSYSREQ : R/W; bitpos: [10]; default: 0;
* clock controller system low-power request , when asserted low ,indicates the
* controller hs requested the GMAX-AXI to enter a lowpower state
*/
#define CNNT_SYS_GMAC_CSYSREQ (BIT(10))
#define CNNT_SYS_GMAC_CSYSREQ_M (CNNT_SYS_GMAC_CSYSREQ_V << CNNT_SYS_GMAC_CSYSREQ_S)
#define CNNT_SYS_GMAC_CSYSREQ_V 0x00000001U
#define CNNT_SYS_GMAC_CSYSREQ_S 10
/** CNNT_SYS_GMAC_APB_POSTW_EN : R/W; bitpos: [11]; default: 0;
* N/A
*/
#define CNNT_SYS_GMAC_APB_POSTW_EN (BIT(11))
#define CNNT_SYS_GMAC_APB_POSTW_EN_M (CNNT_SYS_GMAC_APB_POSTW_EN_V << CNNT_SYS_GMAC_APB_POSTW_EN_S)
#define CNNT_SYS_GMAC_APB_POSTW_EN_V 0x00000001U
#define CNNT_SYS_GMAC_APB_POSTW_EN_S 11
/** CNNT_SYS_GMAC_MEM_PRDYN : RO; bitpos: [12]; default: 1;
* record memory power status
*/
#define CNNT_SYS_GMAC_MEM_PRDYN (BIT(12))
#define CNNT_SYS_GMAC_MEM_PRDYN_M (CNNT_SYS_GMAC_MEM_PRDYN_V << CNNT_SYS_GMAC_MEM_PRDYN_S)
#define CNNT_SYS_GMAC_MEM_PRDYN_V 0x00000001U
#define CNNT_SYS_GMAC_MEM_PRDYN_S 12
/** CNNT_SYS_GMAC_CTRL1_REG register
* N/A
*/
#define CNNT_SYS_GMAC_CTRL1_REG (DR_REG_CNNT_BASE + 0x64)
/** CNNT_SYS_PTP_TIMESTAMP_L : RO; bitpos: [31:0]; default: 0;
* N/A
*/
#define CNNT_SYS_PTP_TIMESTAMP_L 0xFFFFFFFFU
#define CNNT_SYS_PTP_TIMESTAMP_L_M (CNNT_SYS_PTP_TIMESTAMP_L_V << CNNT_SYS_PTP_TIMESTAMP_L_S)
#define CNNT_SYS_PTP_TIMESTAMP_L_V 0xFFFFFFFFU
#define CNNT_SYS_PTP_TIMESTAMP_L_S 0
/** CNNT_SYS_GMAC_CTRL2_REG register
* N/A
*/
#define CNNT_SYS_GMAC_CTRL2_REG (DR_REG_CNNT_BASE + 0x68)
/** CNNT_SYS_PTP_TIMESTAMP_H : RO; bitpos: [31:0]; default: 0;
* N/A
*/
#define CNNT_SYS_PTP_TIMESTAMP_H 0xFFFFFFFFU
#define CNNT_SYS_PTP_TIMESTAMP_H_M (CNNT_SYS_PTP_TIMESTAMP_H_V << CNNT_SYS_PTP_TIMESTAMP_H_S)
#define CNNT_SYS_PTP_TIMESTAMP_H_V 0xFFFFFFFFU
#define CNNT_SYS_PTP_TIMESTAMP_H_S 0
#ifdef __cplusplus
}
#endif

618
components/soc/esp32s31/register/soc/cnnt_sys_struct.h Normal file
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@@ -0,0 +1,618 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: CNNT SYS VER DATE REG */
/** Type of sys_ver_date register
* NA
*/
typedef union {
struct {
/** sys_ver_date : R/W; bitpos: [31:0]; default: 539298086;
* NA
*/
uint32_t sys_ver_date:32;
};
uint32_t val;
} cnnt_sys_ver_date_reg_t;
/** Group: CNNT CLK EN REG */
/** Type of clk_en register
* NA
*/
typedef union {
struct {
/** sys_date : R/W; bitpos: [30:0]; default: 38826240;
* need_des
*/
uint32_t sys_date:31;
/** sys_clk_en : R/W; bitpos: [31]; default: 0;
* NA
*/
uint32_t sys_clk_en:1;
};
uint32_t val;
} cnnt_clk_en_reg_t;
/** Group: Configuration Register */
/** Type of sys_sdmmc_mem_lp_ctrl register
* HP CORE0 & HP CORE1 memory power control register
*/
typedef union {
struct {
/** sys_sdmmc_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
* Configures sdmmc memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
uint32_t sys_sdmmc_mem_lp_mode:2;
/** sys_sdmmc_mem_lp_en : R/W; bitpos: [2]; default: 1;
* Set this bit to power down sdmmc memory.
*/
uint32_t sys_sdmmc_mem_lp_en:1;
/** sys_sdmmc_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control sdmmc memory, disable hardware control.
*/
uint32_t sys_sdmmc_mem_lp_force_ctrl:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cnnt_sys_sdmmc_mem_lp_ctrl_reg_t;
/** Type of sys_usb_otghs_mem_lp_ctrl register
* HP CORE0 & HP CORE1 memory power control register
*/
typedef union {
struct {
/** sys_usb_otghs_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
* Configures usb_otghs memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
uint32_t sys_usb_otghs_mem_lp_mode:2;
/** sys_usb_otghs_mem_lp_en : R/W; bitpos: [2]; default: 0;
* Set this bit to power down usb_otghs memory.
*/
uint32_t sys_usb_otghs_mem_lp_en:1;
/** sys_usb_otghs_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control usb_otghs memory, disable hardware control.
*/
uint32_t sys_usb_otghs_mem_lp_force_ctrl:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cnnt_sys_usb_otghs_mem_lp_ctrl_reg_t;
/** Type of sys_usb_device_mem_lp_ctrl register
* HP CORE0 & HP CORE1 memory power control register
*/
typedef union {
struct {
/** sys_usb_device_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
* Configures usb_device memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
uint32_t sys_usb_device_mem_lp_mode:2;
/** sys_usb_device_mem_lp_en : R/W; bitpos: [2]; default: 0;
* Set this bit to power down usb_device memory.
*/
uint32_t sys_usb_device_mem_lp_en:1;
/** sys_usb_device_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control usb_device (serial jtag) memory, disable
* hardware control.
*/
uint32_t sys_usb_device_mem_lp_force_ctrl:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cnnt_sys_usb_device_mem_lp_ctrl_reg_t;
/** Type of sys_gmac_mem_lp_ctrl register
* HP CORE0 & HP CORE1 memory power control register
*/
typedef union {
struct {
/** sys_gmac_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
* Configures gmac memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
uint32_t sys_gmac_mem_lp_mode:2;
/** sys_gmac_mem_lp_en : R/W; bitpos: [2]; default: 1;
* Set this bit to power down gmac memory.
*/
uint32_t sys_gmac_mem_lp_en:1;
/** sys_gmac_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control gmac memory, disable hardware control.
*/
uint32_t sys_gmac_mem_lp_force_ctrl:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cnnt_sys_gmac_mem_lp_ctrl_reg_t;
/** Group: configure_register */
/** Type of sys_sprf_mem_aux_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
uint32_t sys_sprf_mem_aux_ctrl:32;
};
uint32_t val;
} cnnt_sys_sprf_mem_aux_ctrl_reg_t;
/** Type of sys_sdprf_mem_aux_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
uint32_t sys_sdprf_mem_aux_ctrl:32;
};
uint32_t val;
} cnnt_sys_sdprf_mem_aux_ctrl_reg_t;
/** Type of sys_hp_pad_ulpi_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** sys_hp_pad_ulpi_clk_out_inv_en : R/W; bitpos: [30]; default: 0;
* PAD ULPI Clock output inv Enable, valid only when CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN
* is 1.
*/
uint32_t sys_hp_pad_ulpi_clk_out_inv_en:1;
/** sys_hp_pad_ulpi_clk_out_en : R/W; bitpos: [31]; default: 0;
* PAD ULPI Clock output Enable. 0: pad_ulpi_clk is used as input clk, 1: pad_ulpi_clk
* is used as output clk
*/
uint32_t sys_hp_pad_ulpi_clk_out_en:1;
};
uint32_t val;
} cnnt_sys_hp_pad_ulpi_ctrl_reg_t;
/** Type of sys_usb_clk_ctrl register
* HP USB Clock Reset Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** sys_usb_48m_div_num : R/W; bitpos: [15:8]; default: 9;
* usb 480m to 25m divide number.
*/
uint32_t sys_usb_48m_div_num:8;
/** sys_usb_25m_div_num : R/W; bitpos: [23:16]; default: 19;
* usb 500m to 25m divide number.
*/
uint32_t sys_usb_25m_div_num:8;
/** sys_usb_12m_div_num : R/W; bitpos: [31:24]; default: 39;
* usb 480m to 12m divide number.
*/
uint32_t sys_usb_12m_div_num:8;
};
uint32_t val;
} cnnt_sys_usb_clk_ctrl_reg_t;
/** Type of sys_usb_otg20_ctrl register
* HP USB Clock Reset Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** sys_usb_otg20_utmifs_clk_en : R/W; bitpos: [23]; default: 1;
* usb otg20 utmifs clk enable.
*/
uint32_t sys_usb_otg20_utmifs_clk_en:1;
/** sys_usb_otg20_ulpi_clk_en : R/W; bitpos: [24]; default: 0;
* usb otg20 ulpi clk enable.
*/
uint32_t sys_usb_otg20_ulpi_clk_en:1;
/** sys_usb_otg20_phyref_clk_src_sel : R/W; bitpos: [26:25]; default: 0;
* usb otg20 hs phy src sel. 2''d0: 12m, 2''d1: 25m, 2''d2: pad_hsphy_refclk.'
*/
uint32_t sys_usb_otg20_phyref_clk_src_sel:2;
/** sys_usb_otg20_phyref_clk_en : R/W; bitpos: [27]; default: 0;
* usb otg20 hs phy refclk enable.
*/
uint32_t sys_usb_otg20_phyref_clk_en:1;
uint32_t reserved_28:1;
/** sys_usb_otg20_phy_rst_en : R/W; bitpos: [29]; default: 1;
* usb otg20 phy reset en
*/
uint32_t sys_usb_otg20_phy_rst_en:1;
/** sys_usb_otg20_ahb_rst_en : R/W; bitpos: [30]; default: 1;
* usb otg20 ahb reset en
*/
uint32_t sys_usb_otg20_ahb_rst_en:1;
/** sys_usb_otg20_apb_rst_en : R/W; bitpos: [31]; default: 1;
* usb otg20 apb reset en
*/
uint32_t sys_usb_otg20_apb_rst_en:1;
};
uint32_t val;
} cnnt_sys_usb_otg20_ctrl_reg_t;
/** Type of sys_hp_usb_device_ctrl register
* HP USB Clock Reset Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** sys_usb_device_48m_clk_en : R/W; bitpos: [30]; default: 1;
* usb device fs phy clock enable.
*/
uint32_t sys_usb_device_48m_clk_en:1;
/** sys_usb_device_rst_en : R/W; bitpos: [31]; default: 0;
* usb device reset en
*/
uint32_t sys_usb_device_rst_en:1;
};
uint32_t val;
} cnnt_sys_hp_usb_device_ctrl_reg_t;
/** Type of sys_hp_sdmmc_ctrl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** sys_sdmmc_ahb2axi_post_write_en : R/W; bitpos: [29]; default: 0;
* this reg is used to enable the post_write function of the ahb2axi bridge for sdmmc
*/
uint32_t sys_sdmmc_ahb2axi_post_write_en:1;
/** sys_sdmmc_rst_en : R/W; bitpos: [30]; default: 0;
* hp sdmmc reset en
*/
uint32_t sys_sdmmc_rst_en:1;
/** sys_sdmmc_force_norst : R/W; bitpos: [31]; default: 0;
* hp sdmmc force norst
*/
uint32_t sys_sdmmc_force_norst:1;
};
uint32_t val;
} cnnt_sys_hp_sdmmc_ctrl_reg_t;
/** Type of sys_hp_emac_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_emac_useless_clk_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t sys_emac_useless_clk_en:1;
/** sys_emac_rst_en : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t sys_emac_rst_en:1;
/** sys_emac_force_norst : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t sys_emac_force_norst:1;
uint32_t reserved_3:29;
};
uint32_t val;
} cnnt_sys_hp_emac_ctrl_reg_t;
/** Type of sys_hp_emac_ref_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_emac_ref_clk_sel : R/W; bitpos: [1:0]; default: 0;
* select emac reference clock source. 0: mpll 500MHz, 1: cpll 300MHz.
*/
uint32_t sys_emac_ref_clk_sel:2;
/** sys_emac_ref_clk_en : R/W; bitpos: [2]; default: 0;
* Set as 1 to enable emac reference clock source selection
*/
uint32_t sys_emac_ref_clk_en:1;
/** sys_emac_ref_50m_pad_out_clk_en : R/W; bitpos: [3]; default: 0;
* need_des
*/
uint32_t sys_emac_ref_50m_pad_out_clk_en:1;
uint32_t reserved_4:4;
/** sys_emac_ref_clk_div_num : R/W; bitpos: [15:8]; default: 0;
* Divide number of the divider which is used to divide reference clock source.
*/
uint32_t sys_emac_ref_clk_div_num:8;
uint32_t reserved_16:16;
};
uint32_t val;
} cnnt_sys_hp_emac_ref_ctrl_reg_t;
/** Type of sys_hp_emac_rmii_pad_ctrl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** sys_emac_rmii_pad_clk_en : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t sys_emac_rmii_pad_clk_en:1;
/** sys_emac_rmii_pad_clk_inv_en : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t sys_emac_rmii_pad_clk_inv_en:1;
uint32_t reserved_3:29;
};
uint32_t val;
} cnnt_sys_hp_emac_rmii_pad_ctrl_reg_t;
/** Type of sys_hp_emac_rmii_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_emac_rmii_clk_sel : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t sys_emac_rmii_clk_sel:1;
/** sys_emac_rmii_clk_en : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t sys_emac_rmii_clk_en:1;
/** sys_emac_rmii_pad_out_clk_en : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t sys_emac_rmii_pad_out_clk_en:1;
uint32_t reserved_3:5;
/** sys_emac_rxtx_clk_div_num : R/W; bitpos: [12:8]; default: 0;
* need_des
*/
uint32_t sys_emac_rxtx_clk_div_num:5;
uint32_t reserved_13:19;
};
uint32_t val;
} cnnt_sys_hp_emac_rmii_ctrl_reg_t;
/** Type of sys_hp_emac_rx_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_emac_rx_pad_clk_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t sys_emac_rx_pad_clk_en:1;
/** sys_emac_rx_pad_clk_inv_en : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t sys_emac_rx_pad_clk_inv_en:1;
/** sys_emac_rx_clk_sel : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t sys_emac_rx_clk_sel:1;
/** sys_emac_rx_180_clk_en : R/W; bitpos: [3]; default: 0;
* need_des
*/
uint32_t sys_emac_rx_180_clk_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cnnt_sys_hp_emac_rx_ctrl_reg_t;
/** Type of sys_hp_emac_tx_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_emac_tx_pad_clk_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t sys_emac_tx_pad_clk_en:1;
/** sys_emac_tx_pad_clk_inv_en : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t sys_emac_tx_pad_clk_inv_en:1;
/** sys_emac_tx_clk_sel : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t sys_emac_tx_clk_sel:1;
/** sys_emac_tx_180_clk_en : R/W; bitpos: [3]; default: 0;
* need_des
*/
uint32_t sys_emac_tx_180_clk_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cnnt_sys_hp_emac_tx_ctrl_reg_t;
/** Type of sys_hp_emac_ptp_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_emac_ptp_ref_clk_en : R/W; bitpos: [0]; default: 0;
* Set as 1 to enable emac PTP clock source selection.
*/
uint32_t sys_emac_ptp_ref_clk_en:1;
/** sys_emac_ptp_ref_clk_sel : R/W; bitpos: [1]; default: 0;
* select emac PTP clock source. 0: xtal clock, 1: 80MHz internal clock.
*/
uint32_t sys_emac_ptp_ref_clk_sel:1;
uint32_t reserved_2:30;
};
uint32_t val;
} cnnt_sys_hp_emac_ptp_ctrl_reg_t;
/** Type of sys_spram_mem_aux_ctrl register
* need_des
*/
typedef union {
struct {
/** sys_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
uint32_t sys_spram_mem_aux_ctrl:32;
};
uint32_t val;
} cnnt_sys_spram_mem_aux_ctrl_reg_t;
/** Group: cnnt_iomux_ctrl */
/** Type of sys_cnnt_iomux_ctrl0 register
* need_des
*/
typedef union {
struct {
/** sys_reg_cnnt_iomux_apb_rst_en : R/W; bitpos: [0]; default: 0;
* cnnt_iomux rst en
*/
uint32_t sys_reg_cnnt_iomux_apb_rst_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cnnt_sys_cnnt_iomux_ctrl0_reg_t;
/** Group: GMAC Control Register */
/** Type of sys_gmac_ctrl0 register
* N/A
*/
typedef union {
struct {
/** sys_ptp_pps : RO; bitpos: [0]; default: 0;
* N/A
*/
uint32_t sys_ptp_pps:1;
/** sys_sbd_flowctrl : R/W; bitpos: [1]; default: 0;
* N/A
*/
uint32_t sys_sbd_flowctrl:1;
/** sys_phy_intf_sel : R/W; bitpos: [4:2]; default: 0;
* N/A
*/
uint32_t sys_phy_intf_sel:3;
/** sys_gmac_mem_clk_force_on : R/W; bitpos: [5]; default: 0;
* N/A
*/
uint32_t sys_gmac_mem_clk_force_on:1;
/** sys_gmac_rst_clk_tx_n : RO; bitpos: [6]; default: 0;
* N/A
*/
uint32_t sys_gmac_rst_clk_tx_n:1;
/** sys_gmac_rst_clk_rx_n : RO; bitpos: [7]; default: 0;
* N/A
*/
uint32_t sys_gmac_rst_clk_rx_n:1;
/** sys_gmac_cactive : RO; bitpos: [8]; default: 0;
* this signal indicates that the GMAC-AXI requires its clock signal , 1 : required ,0
* : not required
*/
uint32_t sys_gmac_cactive:1;
/** sys_gmac_csysack : RO; bitpos: [9]; default: 0;
* this signal is the acknowledgement from the GMAC-AXI to the system for low-power
* request ,active high
*/
uint32_t sys_gmac_csysack:1;
/** sys_gmac_csysreq : R/W; bitpos: [10]; default: 0;
* clock controller system low-power request , when asserted low ,indicates the
* controller hs requested the GMAX-AXI to enter a lowpower state
*/
uint32_t sys_gmac_csysreq:1;
/** sys_gmac_apb_postw_en : R/W; bitpos: [11]; default: 0;
* N/A
*/
uint32_t sys_gmac_apb_postw_en:1;
/** sys_gmac_mem_prdyn : RO; bitpos: [12]; default: 1;
* record memory power status
*/
uint32_t sys_gmac_mem_prdyn:1;
uint32_t reserved_13:19;
};
uint32_t val;
} cnnt_sys_gmac_ctrl0_reg_t;
/** Type of sys_gmac_ctrl1 register
* N/A
*/
typedef union {
struct {
/** sys_ptp_timestamp_l : RO; bitpos: [31:0]; default: 0;
* N/A
*/
uint32_t sys_ptp_timestamp_l:32;
};
uint32_t val;
} cnnt_sys_gmac_ctrl1_reg_t;
/** Type of sys_gmac_ctrl2 register
* N/A
*/
typedef union {
struct {
/** sys_ptp_timestamp_h : RO; bitpos: [31:0]; default: 0;
* N/A
*/
uint32_t sys_ptp_timestamp_h:32;
};
uint32_t val;
} cnnt_sys_gmac_ctrl2_reg_t;
typedef struct {
volatile cnnt_sys_ver_date_reg_t sys_ver_date;
volatile cnnt_clk_en_reg_t clk_en;
uint32_t reserved_008[2];
volatile cnnt_sys_sdmmc_mem_lp_ctrl_reg_t sys_sdmmc_mem_lp_ctrl;
volatile cnnt_sys_usb_otghs_mem_lp_ctrl_reg_t sys_usb_otghs_mem_lp_ctrl;
volatile cnnt_sys_usb_device_mem_lp_ctrl_reg_t sys_usb_device_mem_lp_ctrl;
volatile cnnt_sys_gmac_mem_lp_ctrl_reg_t sys_gmac_mem_lp_ctrl;
volatile cnnt_sys_sprf_mem_aux_ctrl_reg_t sys_sprf_mem_aux_ctrl;
volatile cnnt_sys_sdprf_mem_aux_ctrl_reg_t sys_sdprf_mem_aux_ctrl;
volatile cnnt_sys_hp_pad_ulpi_ctrl_reg_t sys_hp_pad_ulpi_ctrl;
volatile cnnt_sys_usb_clk_ctrl_reg_t sys_usb_clk_ctrl;
volatile cnnt_sys_usb_otg20_ctrl_reg_t sys_usb_otg20_ctrl;
volatile cnnt_sys_hp_usb_device_ctrl_reg_t sys_hp_usb_device_ctrl;
volatile cnnt_sys_hp_sdmmc_ctrl_reg_t sys_hp_sdmmc_ctrl;
volatile cnnt_sys_hp_emac_ctrl_reg_t sys_hp_emac_ctrl;
volatile cnnt_sys_hp_emac_ref_ctrl_reg_t sys_hp_emac_ref_ctrl;
volatile cnnt_sys_hp_emac_rmii_pad_ctrl_reg_t sys_hp_emac_rmii_pad_ctrl;
volatile cnnt_sys_hp_emac_rmii_ctrl_reg_t sys_hp_emac_rmii_ctrl;
volatile cnnt_sys_hp_emac_rx_ctrl_reg_t sys_hp_emac_rx_ctrl;
volatile cnnt_sys_hp_emac_tx_ctrl_reg_t sys_hp_emac_tx_ctrl;
volatile cnnt_sys_hp_emac_ptp_ctrl_reg_t sys_hp_emac_ptp_ctrl;
volatile cnnt_sys_cnnt_iomux_ctrl0_reg_t sys_cnnt_iomux_ctrl0;
volatile cnnt_sys_spram_mem_aux_ctrl_reg_t sys_spram_mem_aux_ctrl;
volatile cnnt_sys_gmac_ctrl0_reg_t sys_gmac_ctrl0;
volatile cnnt_sys_gmac_ctrl1_reg_t sys_gmac_ctrl1;
volatile cnnt_sys_gmac_ctrl2_reg_t sys_gmac_ctrl2;
} cnnt_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(cnnt_dev_t) == 0x6c, "Invalid size of cnnt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/cordic_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** CORDIC_CSR_CFG_REG register
* Cordic model config register
*/
#define CORDIC_CSR_CFG_REG (DR_REG_CORDIC_BASE + 0x0)
/** CORDIC_FUNC : R/W; bitpos: [3:0]; default: 0;
* Used to inicate the type of operation currently being performed
*/
#define CORDIC_FUNC 0x0000000FU
#define CORDIC_FUNC_M (CORDIC_FUNC_V << CORDIC_FUNC_S)
#define CORDIC_FUNC_V 0x0000000FU
#define CORDIC_FUNC_S 0
/** CORDIC_PRES : R/W; bitpos: [7:4]; default: 0;
* Instruct the cordic calculate cycle number
*/
#define CORDIC_PRES 0x0000000FU
#define CORDIC_PRES_M (CORDIC_PRES_V << CORDIC_PRES_S)
#define CORDIC_PRES_V 0x0000000FU
#define CORDIC_PRES_S 4
/** CORDIC_SCALE : R/W; bitpos: [11:8]; default: 0;
* The scaling of Input argument
*/
#define CORDIC_SCALE 0x0000000FU
#define CORDIC_SCALE_M (CORDIC_SCALE_V << CORDIC_SCALE_S)
#define CORDIC_SCALE_V 0x0000000FU
#define CORDIC_SCALE_S 8
/** CORDIC_WORK_MODE : R/W; bitpos: [18:17]; default: 0;
* Select Cordic Module data transfer Mode,2'd0: reg_in,reg_out, no zero mode, 2'd1:
* dma_in, reg_out, no zero mode, 2'd2: dma_loop, 2'd3: reg_in, reg_out, zero mode
*/
#define CORDIC_WORK_MODE 0x00000003U
#define CORDIC_WORK_MODE_M (CORDIC_WORK_MODE_V << CORDIC_WORK_MODE_S)
#define CORDIC_WORK_MODE_V 0x00000003U
#define CORDIC_WORK_MODE_S 17
/** CORDIC_RES_NUM : R/W; bitpos: [19]; default: 0;
* Result number
*/
#define CORDIC_RES_NUM (BIT(19))
#define CORDIC_RES_NUM_M (CORDIC_RES_NUM_V << CORDIC_RES_NUM_S)
#define CORDIC_RES_NUM_V 0x00000001U
#define CORDIC_RES_NUM_S 19
/** CORDIC_ARG_NUM : R/W; bitpos: [20]; default: 0;
* Argument number
*/
#define CORDIC_ARG_NUM (BIT(20))
#define CORDIC_ARG_NUM_M (CORDIC_ARG_NUM_V << CORDIC_ARG_NUM_S)
#define CORDIC_ARG_NUM_V 0x00000001U
#define CORDIC_ARG_NUM_S 20
/** CORDIC_RES_SIZE : R/W; bitpos: [21]; default: 0;
* Result Size, 0: q1.15, 1: q1.31
*/
#define CORDIC_RES_SIZE (BIT(21))
#define CORDIC_RES_SIZE_M (CORDIC_RES_SIZE_V << CORDIC_RES_SIZE_S)
#define CORDIC_RES_SIZE_V 0x00000001U
#define CORDIC_RES_SIZE_S 21
/** CORDIC_ARG_SIZE : R/W; bitpos: [22]; default: 0;
* Argument Size, 0: q1.15, 1: q1.31
*/
#define CORDIC_ARG_SIZE (BIT(22))
#define CORDIC_ARG_SIZE_M (CORDIC_ARG_SIZE_V << CORDIC_ARG_SIZE_S)
#define CORDIC_ARG_SIZE_V 0x00000001U
#define CORDIC_ARG_SIZE_S 22
/** CORDIC_UPDATE_FLAG : R/W/SC; bitpos: [29]; default: 0;
* Used to synchronize register data to the computing core and start calculate
*/
#define CORDIC_UPDATE_FLAG (BIT(29))
#define CORDIC_UPDATE_FLAG_M (CORDIC_UPDATE_FLAG_V << CORDIC_UPDATE_FLAG_S)
#define CORDIC_UPDATE_FLAG_V 0x00000001U
#define CORDIC_UPDATE_FLAG_S 29
/** CORDIC_RES_ALL_RDY_FLAG : RO/SS/SC; bitpos: [30]; default: 0;
* Used to indicate whether the operation all result has been stored in the result
* register
*/
#define CORDIC_RES_ALL_RDY_FLAG (BIT(30))
#define CORDIC_RES_ALL_RDY_FLAG_M (CORDIC_RES_ALL_RDY_FLAG_V << CORDIC_RES_ALL_RDY_FLAG_S)
#define CORDIC_RES_ALL_RDY_FLAG_V 0x00000001U
#define CORDIC_RES_ALL_RDY_FLAG_S 30
/** CORDIC_RES_RDY_FLAG : RO/SS/SC; bitpos: [31]; default: 0;
* Used to indicate whether the operation result has been stored in the result register
*/
#define CORDIC_RES_RDY_FLAG (BIT(31))
#define CORDIC_RES_RDY_FLAG_M (CORDIC_RES_RDY_FLAG_V << CORDIC_RES_RDY_FLAG_S)
#define CORDIC_RES_RDY_FLAG_V 0x00000001U
#define CORDIC_RES_RDY_FLAG_S 31
/** CORDIC_ARG1_REG register
* Cordic argument 1 config register
*/
#define CORDIC_ARG1_REG (DR_REG_CORDIC_BASE + 0x4)
/** CORDIC_ARG1_DATA : R/W; bitpos: [31:0]; default: 0;
* First argument data for calculate
*/
#define CORDIC_ARG1_DATA 0xFFFFFFFFU
#define CORDIC_ARG1_DATA_M (CORDIC_ARG1_DATA_V << CORDIC_ARG1_DATA_S)
#define CORDIC_ARG1_DATA_V 0xFFFFFFFFU
#define CORDIC_ARG1_DATA_S 0
/** CORDIC_ARG2_REG register
* Cordic argument 2 config register
*/
#define CORDIC_ARG2_REG (DR_REG_CORDIC_BASE + 0x8)
/** CORDIC_ARG2_DATA : R/W; bitpos: [31:0]; default: 0;
* Second argument data for calculate
*/
#define CORDIC_ARG2_DATA 0xFFFFFFFFU
#define CORDIC_ARG2_DATA_M (CORDIC_ARG2_DATA_V << CORDIC_ARG2_DATA_S)
#define CORDIC_ARG2_DATA_V 0xFFFFFFFFU
#define CORDIC_ARG2_DATA_S 0
/** CORDIC_RES1_REG register
* Cordic result 1 receive register
*/
#define CORDIC_RES1_REG (DR_REG_CORDIC_BASE + 0xc)
/** CORDIC_RES1_DATA : RO; bitpos: [31:0]; default: 0;
* First result data from calculate
*/
#define CORDIC_RES1_DATA 0xFFFFFFFFU
#define CORDIC_RES1_DATA_M (CORDIC_RES1_DATA_V << CORDIC_RES1_DATA_S)
#define CORDIC_RES1_DATA_V 0xFFFFFFFFU
#define CORDIC_RES1_DATA_S 0
/** CORDIC_RES2_REG register
* Cordic result 2 receive register
*/
#define CORDIC_RES2_REG (DR_REG_CORDIC_BASE + 0x10)
/** CORDIC_RES2_DATA : RO; bitpos: [31:0]; default: 0;
* Second result data from calculate
*/
#define CORDIC_RES2_DATA 0xFFFFFFFFU
#define CORDIC_RES2_DATA_M (CORDIC_RES2_DATA_V << CORDIC_RES2_DATA_S)
#define CORDIC_RES2_DATA_V 0xFFFFFFFFU
#define CORDIC_RES2_DATA_S 0
/** CORDIC_IO_INT_ENA_REG register
* Cordic interrupt enable signal configuration register.
*/
#define CORDIC_IO_INT_ENA_REG (DR_REG_CORDIC_BASE + 0x28)
/** CORDIC_CAL_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable CAL_DONE_INT.
*/
#define CORDIC_CAL_DONE_INT_ENA (BIT(0))
#define CORDIC_CAL_DONE_INT_ENA_M (CORDIC_CAL_DONE_INT_ENA_V << CORDIC_CAL_DONE_INT_ENA_S)
#define CORDIC_CAL_DONE_INT_ENA_V 0x00000001U
#define CORDIC_CAL_DONE_INT_ENA_S 0
/** CORDIC_DMA_ALL_CAL_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* Write 1 to enable DMA_ALL_CAL_DONE_INT.
*/
#define CORDIC_DMA_ALL_CAL_DONE_INT_ENA (BIT(1))
#define CORDIC_DMA_ALL_CAL_DONE_INT_ENA_M (CORDIC_DMA_ALL_CAL_DONE_INT_ENA_V << CORDIC_DMA_ALL_CAL_DONE_INT_ENA_S)
#define CORDIC_DMA_ALL_CAL_DONE_INT_ENA_V 0x00000001U
#define CORDIC_DMA_ALL_CAL_DONE_INT_ENA_S 1
/** CORDIC_OUT_AFIFO_WOVF_INT_ENA : R/W; bitpos: [2]; default: 0;
* Write 1 to enable OUT_AFIFO_WOVF_INT.
*/
#define CORDIC_OUT_AFIFO_WOVF_INT_ENA (BIT(2))
#define CORDIC_OUT_AFIFO_WOVF_INT_ENA_M (CORDIC_OUT_AFIFO_WOVF_INT_ENA_V << CORDIC_OUT_AFIFO_WOVF_INT_ENA_S)
#define CORDIC_OUT_AFIFO_WOVF_INT_ENA_V 0x00000001U
#define CORDIC_OUT_AFIFO_WOVF_INT_ENA_S 2
/** CORDIC_IN_AFIFO_RUDF_INT_ENA : R/W; bitpos: [3]; default: 0;
* Write 1 to enable IN_AFIFO_RUDF_INT.
*/
#define CORDIC_IN_AFIFO_RUDF_INT_ENA (BIT(3))
#define CORDIC_IN_AFIFO_RUDF_INT_ENA_M (CORDIC_IN_AFIFO_RUDF_INT_ENA_V << CORDIC_IN_AFIFO_RUDF_INT_ENA_S)
#define CORDIC_IN_AFIFO_RUDF_INT_ENA_V 0x00000001U
#define CORDIC_IN_AFIFO_RUDF_INT_ENA_S 3
/** CORDIC_ARG_NUM_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
* Write 1 to enable ARG_NUM_ERR_INT.
*/
#define CORDIC_ARG_NUM_ERR_INT_ENA (BIT(4))
#define CORDIC_ARG_NUM_ERR_INT_ENA_M (CORDIC_ARG_NUM_ERR_INT_ENA_V << CORDIC_ARG_NUM_ERR_INT_ENA_S)
#define CORDIC_ARG_NUM_ERR_INT_ENA_V 0x00000001U
#define CORDIC_ARG_NUM_ERR_INT_ENA_S 4
/** CORDIC_IO_INT_RAW_REG register
* Cordic interrupt raw signal status register.
*/
#define CORDIC_IO_INT_RAW_REG (DR_REG_CORDIC_BASE + 0x2c)
/** CORDIC_CAL_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of CAL_DONE_INT.
*/
#define CORDIC_CAL_DONE_INT_RAW (BIT(0))
#define CORDIC_CAL_DONE_INT_RAW_M (CORDIC_CAL_DONE_INT_RAW_V << CORDIC_CAL_DONE_INT_RAW_S)
#define CORDIC_CAL_DONE_INT_RAW_V 0x00000001U
#define CORDIC_CAL_DONE_INT_RAW_S 0
/** CORDIC_DMA_ALL_CAL_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of DMA_ALL_CAL_DONE_INT.
*/
#define CORDIC_DMA_ALL_CAL_DONE_INT_RAW (BIT(1))
#define CORDIC_DMA_ALL_CAL_DONE_INT_RAW_M (CORDIC_DMA_ALL_CAL_DONE_INT_RAW_V << CORDIC_DMA_ALL_CAL_DONE_INT_RAW_S)
#define CORDIC_DMA_ALL_CAL_DONE_INT_RAW_V 0x00000001U
#define CORDIC_DMA_ALL_CAL_DONE_INT_RAW_S 1
/** CORDIC_OUT_AFIFO_WOVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of OUT_AFIFO_WOVF_INT.
*/
#define CORDIC_OUT_AFIFO_WOVF_INT_RAW (BIT(2))
#define CORDIC_OUT_AFIFO_WOVF_INT_RAW_M (CORDIC_OUT_AFIFO_WOVF_INT_RAW_V << CORDIC_OUT_AFIFO_WOVF_INT_RAW_S)
#define CORDIC_OUT_AFIFO_WOVF_INT_RAW_V 0x00000001U
#define CORDIC_OUT_AFIFO_WOVF_INT_RAW_S 2
/** CORDIC_IN_AFIFO_RUDF_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
* The raw interrupt status of IN_AFIFO_RUDF_INT.
*/
#define CORDIC_IN_AFIFO_RUDF_INT_RAW (BIT(3))
#define CORDIC_IN_AFIFO_RUDF_INT_RAW_M (CORDIC_IN_AFIFO_RUDF_INT_RAW_V << CORDIC_IN_AFIFO_RUDF_INT_RAW_S)
#define CORDIC_IN_AFIFO_RUDF_INT_RAW_V 0x00000001U
#define CORDIC_IN_AFIFO_RUDF_INT_RAW_S 3
/** CORDIC_ARG_NUM_ERR_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
* The raw interrupt status of ARG_NUM_ERR_INT.
*/
#define CORDIC_ARG_NUM_ERR_INT_RAW (BIT(4))
#define CORDIC_ARG_NUM_ERR_INT_RAW_M (CORDIC_ARG_NUM_ERR_INT_RAW_V << CORDIC_ARG_NUM_ERR_INT_RAW_S)
#define CORDIC_ARG_NUM_ERR_INT_RAW_V 0x00000001U
#define CORDIC_ARG_NUM_ERR_INT_RAW_S 4
/** CORDIC_IO_INT_ST_REG register
* Cordic interrupt signal status register.
*/
#define CORDIC_IO_INT_ST_REG (DR_REG_CORDIC_BASE + 0x30)
/** CORDIC_CAL_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of CAL_DONE_INT.
*/
#define CORDIC_CAL_DONE_INT_ST (BIT(0))
#define CORDIC_CAL_DONE_INT_ST_M (CORDIC_CAL_DONE_INT_ST_V << CORDIC_CAL_DONE_INT_ST_S)
#define CORDIC_CAL_DONE_INT_ST_V 0x00000001U
#define CORDIC_CAL_DONE_INT_ST_S 0
/** CORDIC_DMA_ALL_CAL_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status of DMA_ALL_CAL_DONE_INT.
*/
#define CORDIC_DMA_ALL_CAL_DONE_INT_ST (BIT(1))
#define CORDIC_DMA_ALL_CAL_DONE_INT_ST_M (CORDIC_DMA_ALL_CAL_DONE_INT_ST_V << CORDIC_DMA_ALL_CAL_DONE_INT_ST_S)
#define CORDIC_DMA_ALL_CAL_DONE_INT_ST_V 0x00000001U
#define CORDIC_DMA_ALL_CAL_DONE_INT_ST_S 1
/** CORDIC_OUT_AFIFO_WOVF_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status of OUT_AFIFO_WOVF_INT.
*/
#define CORDIC_OUT_AFIFO_WOVF_INT_ST (BIT(2))
#define CORDIC_OUT_AFIFO_WOVF_INT_ST_M (CORDIC_OUT_AFIFO_WOVF_INT_ST_V << CORDIC_OUT_AFIFO_WOVF_INT_ST_S)
#define CORDIC_OUT_AFIFO_WOVF_INT_ST_V 0x00000001U
#define CORDIC_OUT_AFIFO_WOVF_INT_ST_S 2
/** CORDIC_IN_AFIFO_RUDF_INT_ST : RO; bitpos: [3]; default: 0;
* The masked interrupt status of IN_AFIFO_RUDF_INT.
*/
#define CORDIC_IN_AFIFO_RUDF_INT_ST (BIT(3))
#define CORDIC_IN_AFIFO_RUDF_INT_ST_M (CORDIC_IN_AFIFO_RUDF_INT_ST_V << CORDIC_IN_AFIFO_RUDF_INT_ST_S)
#define CORDIC_IN_AFIFO_RUDF_INT_ST_V 0x00000001U
#define CORDIC_IN_AFIFO_RUDF_INT_ST_S 3
/** CORDIC_ARG_NUM_ERR_INT_ST : RO; bitpos: [4]; default: 0;
* The masked interrupt status of ARG_NUM_ERR_INT.
*/
#define CORDIC_ARG_NUM_ERR_INT_ST (BIT(4))
#define CORDIC_ARG_NUM_ERR_INT_ST_M (CORDIC_ARG_NUM_ERR_INT_ST_V << CORDIC_ARG_NUM_ERR_INT_ST_S)
#define CORDIC_ARG_NUM_ERR_INT_ST_V 0x00000001U
#define CORDIC_ARG_NUM_ERR_INT_ST_S 4
/** CORDIC_IO_INT_CLR_REG register
* Cordic interrupt clear signal configuration register.
*/
#define CORDIC_IO_INT_CLR_REG (DR_REG_CORDIC_BASE + 0x34)
/** CORDIC_CAL_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear CAL_DONE_INT.
*/
#define CORDIC_CAL_DONE_INT_CLR (BIT(0))
#define CORDIC_CAL_DONE_INT_CLR_M (CORDIC_CAL_DONE_INT_CLR_V << CORDIC_CAL_DONE_INT_CLR_S)
#define CORDIC_CAL_DONE_INT_CLR_V 0x00000001U
#define CORDIC_CAL_DONE_INT_CLR_S 0
/** CORDIC_DMA_ALL_CAL_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear DMA_ALL_CAL_DONE_INT.
*/
#define CORDIC_DMA_ALL_CAL_DONE_INT_CLR (BIT(1))
#define CORDIC_DMA_ALL_CAL_DONE_INT_CLR_M (CORDIC_DMA_ALL_CAL_DONE_INT_CLR_V << CORDIC_DMA_ALL_CAL_DONE_INT_CLR_S)
#define CORDIC_DMA_ALL_CAL_DONE_INT_CLR_V 0x00000001U
#define CORDIC_DMA_ALL_CAL_DONE_INT_CLR_S 1
/** CORDIC_OUT_AFIFO_WOVF_INT_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear OUT_AFIFO_WOVF_INT.
*/
#define CORDIC_OUT_AFIFO_WOVF_INT_CLR (BIT(2))
#define CORDIC_OUT_AFIFO_WOVF_INT_CLR_M (CORDIC_OUT_AFIFO_WOVF_INT_CLR_V << CORDIC_OUT_AFIFO_WOVF_INT_CLR_S)
#define CORDIC_OUT_AFIFO_WOVF_INT_CLR_V 0x00000001U
#define CORDIC_OUT_AFIFO_WOVF_INT_CLR_S 2
/** CORDIC_IN_AFIFO_RUDF_INT_CLR : WT; bitpos: [3]; default: 0;
* Write 1 to clear IN_AFIFO_RUDF_INT.
*/
#define CORDIC_IN_AFIFO_RUDF_INT_CLR (BIT(3))
#define CORDIC_IN_AFIFO_RUDF_INT_CLR_M (CORDIC_IN_AFIFO_RUDF_INT_CLR_V << CORDIC_IN_AFIFO_RUDF_INT_CLR_S)
#define CORDIC_IN_AFIFO_RUDF_INT_CLR_V 0x00000001U
#define CORDIC_IN_AFIFO_RUDF_INT_CLR_S 3
/** CORDIC_ARG_NUM_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
* Write 1 to clear ARG_NUM_ERR_INT.
*/
#define CORDIC_ARG_NUM_ERR_INT_CLR (BIT(4))
#define CORDIC_ARG_NUM_ERR_INT_CLR_M (CORDIC_ARG_NUM_ERR_INT_CLR_V << CORDIC_ARG_NUM_ERR_INT_CLR_S)
#define CORDIC_ARG_NUM_ERR_INT_CLR_V 0x00000001U
#define CORDIC_ARG_NUM_ERR_INT_CLR_S 4
/** CORDIC_FIFO_CFG_REG register
* Cordic FIFO configuration register.
*/
#define CORDIC_FIFO_CFG_REG (DR_REG_CORDIC_BASE + 0x38)
/** CORDIC_INFIFO_RESET : WT; bitpos: [0]; default: 0;
* infifo_reset_register
*/
#define CORDIC_INFIFO_RESET (BIT(0))
#define CORDIC_INFIFO_RESET_M (CORDIC_INFIFO_RESET_V << CORDIC_INFIFO_RESET_S)
#define CORDIC_INFIFO_RESET_V 0x00000001U
#define CORDIC_INFIFO_RESET_S 0
/** CORDIC_OUTFIFO_RESET : WT; bitpos: [1]; default: 0;
* outfifo_reset_register
*/
#define CORDIC_OUTFIFO_RESET (BIT(1))
#define CORDIC_OUTFIFO_RESET_M (CORDIC_OUTFIFO_RESET_V << CORDIC_OUTFIFO_RESET_S)
#define CORDIC_OUTFIFO_RESET_V 0x00000001U
#define CORDIC_OUTFIFO_RESET_S 1
/** CORDIC_CLK_REG register
* Cordic clk configuration register.
*/
#define CORDIC_CLK_REG (DR_REG_CORDIC_BASE + 0x3c)
/** CORDIC_CLK_EN : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
#define CORDIC_CLK_EN (BIT(31))
#define CORDIC_CLK_EN_M (CORDIC_CLK_EN_V << CORDIC_CLK_EN_S)
#define CORDIC_CLK_EN_V 0x00000001U
#define CORDIC_CLK_EN_S 31
/** CORDIC_VERSION_REG register
* Version register.
*/
#define CORDIC_VERSION_REG (DR_REG_CORDIC_BASE + 0x40)
/** CORDIC_DATE : R/W; bitpos: [27:0]; default: 37818960;
* Version of this register file
*/
#define CORDIC_DATE 0x0FFFFFFFU
#define CORDIC_DATE_M (CORDIC_DATE_V << CORDIC_DATE_S)
#define CORDIC_DATE_V 0x0FFFFFFFU
#define CORDIC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: CORDIC Mode Configuration */
/** Type of csr_cfg register
* Cordic model config register
*/
typedef union {
struct {
/** func : R/W; bitpos: [3:0]; default: 0;
* Used to inicate the type of operation currently being performed
*/
uint32_t func:4;
/** press : R/W; bitpos: [7:4]; default: 0;
* Instruct the cordic calculate cycle number
*/
uint32_t press:4;
/** scale : R/W; bitpos: [11:8]; default: 0;
* The scaling of Input argument
*/
uint32_t scale:4;
uint32_t reserved_12:5;
/** work_mode : R/W; bitpos: [18:17]; default: 0;
* Select Cordic Module data transfer Mode,2'd0: reg_in,reg_out, no zero mode, 2'd1:
* dma_in, reg_out, no zero mode, 2'd2: dma_loop, 2'd3: reg_in, reg_out, zero mode
*/
uint32_t work_mode:2;
/** res_num : R/W; bitpos: [19]; default: 0;
* Result number
*/
uint32_t res_num:1;
/** arg_num : R/W; bitpos: [20]; default: 0;
* Argument number
*/
uint32_t arg_num:1;
/** res_size : R/W; bitpos: [21]; default: 0;
* Result Size, 0: q1.15, 1: q1.31
*/
uint32_t res_size:1;
/** arg_size : R/W; bitpos: [22]; default: 0;
* Argument Size, 0: q1.15, 1: q1.31
*/
uint32_t arg_size:1;
uint32_t reserved_23:6;
/** update_flag : R/W/SC; bitpos: [29]; default: 0;
* Used to synchronize register data to the computing core and start calculate
*/
uint32_t update_flag:1;
/** res_all_rdy_flag : RO/SS/SC; bitpos: [30]; default: 0;
* Used to indicate whether the operation all result has been stored in the result
* register
*/
uint32_t res_all_rdy_flag:1;
/** res_rdy_flag : RO/SS/SC; bitpos: [31]; default: 0;
* Used to indicate whether the operation result has been stored in the result register
*/
uint32_t res_rdy_flag:1;
};
uint32_t val;
} cordic_csr_cfg_reg_t;
/** Group: CORDIC ARG1 Configuration */
/** Type of arg1 register
* Cordic argument 1 config register
*/
typedef union {
struct {
/** arg1_data : R/W; bitpos: [31:0]; default: 0;
* First argument data for calculate
*/
uint32_t arg1_data:32;
};
uint32_t val;
} cordic_arg1_reg_t;
/** Group: CORDIC ARG2 Configuration */
/** Type of arg2 register
* Cordic argument 2 config register
*/
typedef union {
struct {
/** arg2_data : R/W; bitpos: [31:0]; default: 0;
* Second argument data for calculate
*/
uint32_t arg2_data:32;
};
uint32_t val;
} cordic_arg2_reg_t;
/** Group: CORDIC RES1 Receive */
/** Type of res1 register
* Cordic result 1 receive register
*/
typedef union {
struct {
/** res1_data : RO; bitpos: [31:0]; default: 0;
* First result data from calculate
*/
uint32_t res1_data:32;
};
uint32_t val;
} cordic_res1_reg_t;
/** Group: CORDIC RES2 Receive */
/** Type of res2 register
* Cordic result 2 receive register
*/
typedef union {
struct {
/** res2_data : RO; bitpos: [31:0]; default: 0;
* Second result data from calculate
*/
uint32_t res2_data:32;
};
uint32_t val;
} cordic_res2_reg_t;
/** Group: CORDIC Interrupt Configuration and Status */
/** Type of io_int_ena register
* Cordic interrupt enable signal configuration register.
*/
typedef union {
struct {
/** cal_done_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable CAL_DONE_INT.
*/
uint32_t cal_done_int_ena:1;
/** dma_all_cal_done_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable DMA_ALL_CAL_DONE_INT.
*/
uint32_t dma_all_cal_done_int_ena:1;
/** out_afifo_wovf_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable OUT_AFIFO_WOVF_INT.
*/
uint32_t out_afifo_wovf_int_ena:1;
/** in_afifo_rudf_int_ena : R/W; bitpos: [3]; default: 0;
* Write 1 to enable IN_AFIFO_RUDF_INT.
*/
uint32_t in_afifo_rudf_int_ena:1;
/** arg_num_err_int_ena : R/W; bitpos: [4]; default: 0;
* Write 1 to enable ARG_NUM_ERR_INT.
*/
uint32_t arg_num_err_int_ena:1;
uint32_t reserved_5:27;
};
uint32_t val;
} cordic_io_int_ena_reg_t;
/** Type of io_int_raw register
* Cordic interrupt raw signal status register.
*/
typedef union {
struct {
/** cal_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of CAL_DONE_INT.
*/
uint32_t cal_done_int_raw:1;
/** dma_all_cal_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of DMA_ALL_CAL_DONE_INT.
*/
uint32_t dma_all_cal_done_int_raw:1;
/** out_afifo_wovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of OUT_AFIFO_WOVF_INT.
*/
uint32_t out_afifo_wovf_int_raw:1;
/** in_afifo_rudf_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
* The raw interrupt status of IN_AFIFO_RUDF_INT.
*/
uint32_t in_afifo_rudf_int_raw:1;
/** arg_num_err_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
* The raw interrupt status of ARG_NUM_ERR_INT.
*/
uint32_t arg_num_err_int_raw:1;
uint32_t reserved_5:27;
};
uint32_t val;
} cordic_io_int_raw_reg_t;
/** Type of io_int_st register
* Cordic interrupt signal status register.
*/
typedef union {
struct {
/** cal_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of CAL_DONE_INT.
*/
uint32_t cal_done_int_st:1;
/** dma_all_cal_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status of DMA_ALL_CAL_DONE_INT.
*/
uint32_t dma_all_cal_done_int_st:1;
/** out_afifo_wovf_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status of OUT_AFIFO_WOVF_INT.
*/
uint32_t out_afifo_wovf_int_st:1;
/** in_afifo_rudf_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status of IN_AFIFO_RUDF_INT.
*/
uint32_t in_afifo_rudf_int_st:1;
/** arg_num_err_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status of ARG_NUM_ERR_INT.
*/
uint32_t arg_num_err_int_st:1;
uint32_t reserved_5:27;
};
uint32_t val;
} cordic_io_int_st_reg_t;
/** Type of io_int_clr register
* Cordic interrupt clear signal configuration register.
*/
typedef union {
struct {
/** cal_done_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear CAL_DONE_INT.
*/
uint32_t cal_done_int_clr:1;
/** dma_all_cal_done_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear DMA_ALL_CAL_DONE_INT.
*/
uint32_t dma_all_cal_done_int_clr:1;
/** out_afifo_wovf_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear OUT_AFIFO_WOVF_INT.
*/
uint32_t out_afifo_wovf_int_clr:1;
/** in_afifo_rudf_int_clr : WT; bitpos: [3]; default: 0;
* Write 1 to clear IN_AFIFO_RUDF_INT.
*/
uint32_t in_afifo_rudf_int_clr:1;
/** arg_num_err_int_clr : WT; bitpos: [4]; default: 0;
* Write 1 to clear ARG_NUM_ERR_INT.
*/
uint32_t arg_num_err_int_clr:1;
uint32_t reserved_5:27;
};
uint32_t val;
} cordic_io_int_clr_reg_t;
/** Group: CORDIC FIFO Configuration */
/** Type of fifo_cfg register
* Cordic FIFO configuration register.
*/
typedef union {
struct {
/** infifo_reset : WT; bitpos: [0]; default: 0;
* infifo_reset_register
*/
uint32_t infifo_reset:1;
/** outfifo_reset : WT; bitpos: [1]; default: 0;
* outfifo_reset_register
*/
uint32_t outfifo_reset:1;
uint32_t reserved_2:30;
};
uint32_t val;
} cordic_fifo_cfg_reg_t;
/** Group: CORDIC Clock Configuration */
/** Type of clk register
* Cordic clk configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
uint32_t clk_en:1;
};
uint32_t val;
} cordic_clk_reg_t;
/** Group: CORDIC Version Register */
/** Type of version register
* Version register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37818960;
* Version of this register file
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} cordic_version_reg_t;
typedef struct {
volatile cordic_csr_cfg_reg_t csr_cfg;
volatile cordic_arg1_reg_t arg1;
volatile cordic_arg2_reg_t arg2;
volatile cordic_res1_reg_t res1;
volatile cordic_res2_reg_t res2;
uint32_t reserved_014[5];
volatile cordic_io_int_ena_reg_t io_int_ena;
volatile cordic_io_int_raw_reg_t io_int_raw;
volatile cordic_io_int_st_reg_t io_int_st;
volatile cordic_io_int_clr_reg_t io_int_clr;
volatile cordic_fifo_cfg_reg_t fifo_cfg;
volatile cordic_clk_reg_t clk;
volatile cordic_version_reg_t version;
} cordic_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(cordic_dev_t) == 0x44, "Invalid size of cordic_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} cpu_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start_l : HRO; bitpos: [12:0]; default: 0;
* Low 12 bit, start address of region n.
*/
uint32_t regionn_addr_start_l:13;
/** regionn_addr_start : R/W; bitpos: [28:13]; default: 0;
* Configures start address of region n.
*/
uint32_t regionn_addr_start:16;
/** regionn_addr_start_h : HRO; bitpos: [31:29]; default: 2;
* High 13 bit, start address of region n.
*/
uint32_t regionn_addr_start_h:3;
};
uint32_t val;
} cpu_apm_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end_l : HRO; bitpos: [12:0]; default: 8191;
* Low 12 bit, end address of region n.
*/
uint32_t regionn_addr_end_l:13;
/** regionn_addr_end : R/W; bitpos: [28:13]; default: 65535;
* Configures end address of region n.
*/
uint32_t regionn_addr_end:16;
/** regionn_addr_end_h : HRO; bitpos: [31:29]; default: 2;
* High 13 bit, end address of region n.
*/
uint32_t regionn_addr_end_h:3;
};
uint32_t val;
} cpu_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
uint32_t reserved_11:1;
/** regionn_tee_x : R/W; bitpos: [12]; default: 1;
* Configures the execution authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_x:1;
/** regionn_tee_w : R/W; bitpos: [13]; default: 1;
* Configures the write authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_w:1;
/** regionn_tee_r : R/W; bitpos: [14]; default: 1;
* Configures the read authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_r:1;
uint32_t reserved_15:1;
/** regionn_lock : R/W; bitpos: [16]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_17:15;
};
uint32_t val;
} cpu_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_func_en:1;
/** m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
*/
uint32_t m2_func_en:1;
/** m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
*/
uint32_t m3_func_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cpu_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:8;
uint32_t reserved_8:8;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} cpu_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:8;
uint32_t reserved_8:8;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} cpu_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of m2_status register
* M2 status register
*/
typedef union {
struct {
/** m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m2_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of m2_status_clr register
* M2 status clear register
*/
typedef union {
struct {
/** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m2_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of m2_exception_info0 register
* M2 exception_info0 register
*/
typedef union {
struct {
/** m2_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m2_exception_region:8;
uint32_t reserved_8:8;
/** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m2_exception_mode:2;
/** m2_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m2_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of m2_exception_info1 register
* M2 exception_info1 register
*/
typedef union {
struct {
/** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m2_exception_addr:32;
};
uint32_t val;
} cpu_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of m3_status register
* M3 status register
*/
typedef union {
struct {
/** m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m3_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of m3_status_clr register
* M3 status clear register
*/
typedef union {
struct {
/** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m3_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of m3_exception_info0 register
* M3 exception_info0 register
*/
typedef union {
struct {
/** m3_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m3_exception_region:8;
uint32_t reserved_8:8;
/** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m3_exception_mode:2;
/** m3_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m3_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of m3_exception_info1 register
* M3 exception_info1 register
*/
typedef union {
struct {
/** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m3_exception_addr:32;
};
uint32_t val;
} cpu_apm_m3_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m1_apm_int_en:1;
/** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m2_apm_int_en:1;
/** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m3_apm_int_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cpu_apm_int_en_reg_t;
/** Type of bus_err_conf register
* APM interrupt enable register
*/
typedef union {
struct {
/** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
* Configures whether return error response to cpu when access blocked
* 0: disable error response
* 1: enable error response
*/
uint32_t bus_err_resp_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_bus_err_conf_reg_t;
/** Group: Clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 38822496;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} cpu_apm_date_reg_t;
typedef struct {
volatile cpu_apm_region_filter_en_reg_t region_filter_en;
volatile cpu_apm_regionn_addr_start_reg_t region0_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region0_addr_end;
volatile cpu_apm_regionn_attr_reg_t region0_attr;
volatile cpu_apm_regionn_addr_start_reg_t region1_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region1_addr_end;
volatile cpu_apm_regionn_attr_reg_t region1_attr;
volatile cpu_apm_regionn_addr_start_reg_t region2_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region2_addr_end;
volatile cpu_apm_regionn_attr_reg_t region2_attr;
volatile cpu_apm_regionn_addr_start_reg_t region3_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region3_addr_end;
volatile cpu_apm_regionn_attr_reg_t region3_attr;
volatile cpu_apm_regionn_addr_start_reg_t region4_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region4_addr_end;
volatile cpu_apm_regionn_attr_reg_t region4_attr;
volatile cpu_apm_regionn_addr_start_reg_t region5_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region5_addr_end;
volatile cpu_apm_regionn_attr_reg_t region5_attr;
volatile cpu_apm_regionn_addr_start_reg_t region6_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region6_addr_end;
volatile cpu_apm_regionn_attr_reg_t region6_attr;
volatile cpu_apm_regionn_addr_start_reg_t region7_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region7_addr_end;
volatile cpu_apm_regionn_attr_reg_t region7_attr;
uint32_t reserved_064[24];
volatile cpu_apm_func_ctrl_reg_t func_ctrl;
volatile cpu_apm_m0_status_reg_t m0_status;
volatile cpu_apm_m0_status_clr_reg_t m0_status_clr;
volatile cpu_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile cpu_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile cpu_apm_m1_status_reg_t m1_status;
volatile cpu_apm_m1_status_clr_reg_t m1_status_clr;
volatile cpu_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile cpu_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile cpu_apm_m2_status_reg_t m2_status;
volatile cpu_apm_m2_status_clr_reg_t m2_status_clr;
volatile cpu_apm_m2_exception_info0_reg_t m2_exception_info0;
volatile cpu_apm_m2_exception_info1_reg_t m2_exception_info1;
volatile cpu_apm_m3_status_reg_t m3_status;
volatile cpu_apm_m3_status_clr_reg_t m3_status_clr;
volatile cpu_apm_m3_exception_info0_reg_t m3_exception_info0;
volatile cpu_apm_m3_exception_info1_reg_t m3_exception_info1;
uint32_t reserved_108[4];
volatile cpu_apm_int_en_reg_t int_en;
volatile cpu_apm_bus_err_conf_reg_t bus_err_conf;
uint32_t reserved_120[182];
volatile cpu_apm_clock_gate_reg_t clock_gate;
volatile cpu_apm_date_reg_t date;
} cpu_apm_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(cpu_apm_dev_t) == 0x400, "Invalid size of cpu_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/dac_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DAC_PAD_CFG_REG register
* configure dac pad register
*/
#define DAC_PAD_CFG_REG (DR_REG_DAC_BASE + 0x0)
/** DAC_HS_MODE_PAD_0 : R/W; bitpos: [0]; default: 0;
* 1 to let DAC PAD 0 enter High speed mode
*/
#define DAC_HS_MODE_PAD_0 (BIT(0))
#define DAC_HS_MODE_PAD_0_M (DAC_HS_MODE_PAD_0_V << DAC_HS_MODE_PAD_0_S)
#define DAC_HS_MODE_PAD_0_V 0x00000001U
#define DAC_HS_MODE_PAD_0_S 0
/** DAC_XPD_PAD_0 : R/W; bitpos: [1]; default: 0;
* 1 to power on DAC PAD 0
*/
#define DAC_XPD_PAD_0 (BIT(1))
#define DAC_XPD_PAD_0_M (DAC_XPD_PAD_0_V << DAC_XPD_PAD_0_S)
#define DAC_XPD_PAD_0_V 0x00000001U
#define DAC_XPD_PAD_0_S 1
/** DAC_EN_ADC_MUX_PAD_0 : R/W; bitpos: [2]; default: 0;
* 1 to enable adc mux for DAC PAD 0
*/
#define DAC_EN_ADC_MUX_PAD_0 (BIT(2))
#define DAC_EN_ADC_MUX_PAD_0_M (DAC_EN_ADC_MUX_PAD_0_V << DAC_EN_ADC_MUX_PAD_0_S)
#define DAC_EN_ADC_MUX_PAD_0_V 0x00000001U
#define DAC_EN_ADC_MUX_PAD_0_S 2
/** DAC_DSAMP_LS_PAD_0 : R/W; bitpos: [3]; default: 0;
* 1 to start sample and hold mode for DAC PAD 0
*/
#define DAC_DSAMP_LS_PAD_0 (BIT(3))
#define DAC_DSAMP_LS_PAD_0_M (DAC_DSAMP_LS_PAD_0_V << DAC_DSAMP_LS_PAD_0_S)
#define DAC_DSAMP_LS_PAD_0_V 0x00000001U
#define DAC_DSAMP_LS_PAD_0_S 3
/** DAC_DCAL_LS_PAD_0 : R/W; bitpos: [4]; default: 0;
* 1 to Calibrate the buffer of DAC PAD 0 (DBUF of pad 1 must be 1 during this
* operation)
*/
#define DAC_DCAL_LS_PAD_0 (BIT(4))
#define DAC_DCAL_LS_PAD_0_M (DAC_DCAL_LS_PAD_0_V << DAC_DCAL_LS_PAD_0_S)
#define DAC_DCAL_LS_PAD_0_V 0x00000001U
#define DAC_DCAL_LS_PAD_0_S 4
/** DAC_DBUF_LS_PAD_0 : R/W; bitpos: [5]; default: 0;
* 1 to turn on the buffer of DAC PAD 0
*/
#define DAC_DBUF_LS_PAD_0 (BIT(5))
#define DAC_DBUF_LS_PAD_0_M (DAC_DBUF_LS_PAD_0_V << DAC_DBUF_LS_PAD_0_S)
#define DAC_DBUF_LS_PAD_0_V 0x00000001U
#define DAC_DBUF_LS_PAD_0_S 5
/** DAC_ON_LS_PAD_0 : R/W; bitpos: [6]; default: 0;
* 1 to turn on the DAC PAD 0 during sample and hold mode
*/
#define DAC_ON_LS_PAD_0 (BIT(6))
#define DAC_ON_LS_PAD_0_M (DAC_ON_LS_PAD_0_V << DAC_ON_LS_PAD_0_S)
#define DAC_ON_LS_PAD_0_V 0x00000001U
#define DAC_ON_LS_PAD_0_S 6
/** DAC_HS_MODE_PAD_1 : R/W; bitpos: [7]; default: 0;
* 1 to let DAC PAD 1 enter High speed mode
*/
#define DAC_HS_MODE_PAD_1 (BIT(7))
#define DAC_HS_MODE_PAD_1_M (DAC_HS_MODE_PAD_1_V << DAC_HS_MODE_PAD_1_S)
#define DAC_HS_MODE_PAD_1_V 0x00000001U
#define DAC_HS_MODE_PAD_1_S 7
/** DAC_XPD_PAD_1 : R/W; bitpos: [8]; default: 0;
* 1 to power on DAC PAD 1
*/
#define DAC_XPD_PAD_1 (BIT(8))
#define DAC_XPD_PAD_1_M (DAC_XPD_PAD_1_V << DAC_XPD_PAD_1_S)
#define DAC_XPD_PAD_1_V 0x00000001U
#define DAC_XPD_PAD_1_S 8
/** DAC_EN_ADC_MUX_PAD_1 : R/W; bitpos: [9]; default: 0;
* 1 to enable adc mux for DAC PAD 1
*/
#define DAC_EN_ADC_MUX_PAD_1 (BIT(9))
#define DAC_EN_ADC_MUX_PAD_1_M (DAC_EN_ADC_MUX_PAD_1_V << DAC_EN_ADC_MUX_PAD_1_S)
#define DAC_EN_ADC_MUX_PAD_1_V 0x00000001U
#define DAC_EN_ADC_MUX_PAD_1_S 9
/** DAC_DSAMP_LS_PAD_1 : R/W; bitpos: [10]; default: 0;
* 1 to start sample and hold mode for DAC PAD 1
*/
#define DAC_DSAMP_LS_PAD_1 (BIT(10))
#define DAC_DSAMP_LS_PAD_1_M (DAC_DSAMP_LS_PAD_1_V << DAC_DSAMP_LS_PAD_1_S)
#define DAC_DSAMP_LS_PAD_1_V 0x00000001U
#define DAC_DSAMP_LS_PAD_1_S 10
/** DAC_DCAL_LS_PAD_1 : R/W; bitpos: [11]; default: 0;
* 1 to Calibrate the buffer of DAC PAD 1 (DBUF of pad 1 must be 1 during this
* operation)
*/
#define DAC_DCAL_LS_PAD_1 (BIT(11))
#define DAC_DCAL_LS_PAD_1_M (DAC_DCAL_LS_PAD_1_V << DAC_DCAL_LS_PAD_1_S)
#define DAC_DCAL_LS_PAD_1_V 0x00000001U
#define DAC_DCAL_LS_PAD_1_S 11
/** DAC_DBUF_LS_PAD_1 : R/W; bitpos: [12]; default: 0;
* 1 to turn on the buffer of DAC PAD 1
*/
#define DAC_DBUF_LS_PAD_1 (BIT(12))
#define DAC_DBUF_LS_PAD_1_M (DAC_DBUF_LS_PAD_1_V << DAC_DBUF_LS_PAD_1_S)
#define DAC_DBUF_LS_PAD_1_V 0x00000001U
#define DAC_DBUF_LS_PAD_1_S 12
/** DAC_ON_LS_PAD_1 : R/W; bitpos: [13]; default: 0;
* 1 to turn on the DAC PAD 1 during sample and hold mode
*/
#define DAC_ON_LS_PAD_1 (BIT(13))
#define DAC_ON_LS_PAD_1_M (DAC_ON_LS_PAD_1_V << DAC_ON_LS_PAD_1_S)
#define DAC_ON_LS_PAD_1_V 0x00000001U
#define DAC_ON_LS_PAD_1_S 13
/** DAC_DIV_NUM : R/W; bitpos: [29:14]; default: 1;
* divide number between clk ls and clk hs
*/
#define DAC_DIV_NUM 0x0000FFFFU
#define DAC_DIV_NUM_M (DAC_DIV_NUM_V << DAC_DIV_NUM_S)
#define DAC_DIV_NUM_V 0x0000FFFFU
#define DAC_DIV_NUM_S 14
/** DAC_DBUF_RANGE_LS_PAD_0 : R/W; bitpos: [30]; default: 0;
* 1:when buffer is activated, allow using full code of maximum bitwidth
* 0:when buffer is not activated, should always be 0
*/
#define DAC_DBUF_RANGE_LS_PAD_0 (BIT(30))
#define DAC_DBUF_RANGE_LS_PAD_0_M (DAC_DBUF_RANGE_LS_PAD_0_V << DAC_DBUF_RANGE_LS_PAD_0_S)
#define DAC_DBUF_RANGE_LS_PAD_0_V 0x00000001U
#define DAC_DBUF_RANGE_LS_PAD_0_S 30
/** DAC_DBUF_RANGE_LS_PAD_1 : R/W; bitpos: [31]; default: 0;
* 1:when buffer is activated, allow using full code of maximum bitwidth
* 0:when buffer is not activated, should always be 0
*/
#define DAC_DBUF_RANGE_LS_PAD_1 (BIT(31))
#define DAC_DBUF_RANGE_LS_PAD_1_M (DAC_DBUF_RANGE_LS_PAD_1_V << DAC_DBUF_RANGE_LS_PAD_1_S)
#define DAC_DBUF_RANGE_LS_PAD_1_V 0x00000001U
#define DAC_DBUF_RANGE_LS_PAD_1_S 31
/** DAC_CALI_RESULT_REG register
* DAC CALI result register
*/
#define DAC_CALI_RESULT_REG (DR_REG_DAC_BASE + 0x4)
/** DAC_CALI_RESULT_PAD_0 : R/W; bitpos: [11:0]; default: 0;
* cali result register for pad 0 output
*/
#define DAC_CALI_RESULT_PAD_0 0x00000FFFU
#define DAC_CALI_RESULT_PAD_0_M (DAC_CALI_RESULT_PAD_0_V << DAC_CALI_RESULT_PAD_0_S)
#define DAC_CALI_RESULT_PAD_0_V 0x00000FFFU
#define DAC_CALI_RESULT_PAD_0_S 0
/** DAC_CALI_RESULT_PAD_1 : R/W; bitpos: [23:12]; default: 0;
* cali result register for pad 1 output
*/
#define DAC_CALI_RESULT_PAD_1 0x00000FFFU
#define DAC_CALI_RESULT_PAD_1_M (DAC_CALI_RESULT_PAD_1_V << DAC_CALI_RESULT_PAD_1_S)
#define DAC_CALI_RESULT_PAD_1_V 0x00000FFFU
#define DAC_CALI_RESULT_PAD_1_S 12
/** DAC_PDMA_CFG_REG register
* dac cfg register
*/
#define DAC_PDMA_CFG_REG (DR_REG_DAC_BASE + 0x8)
/** DAC_PDMA_ALTER_MODE : R/W; bitpos: [0]; default: 0;
* 1:make rotation between two pads when outputting data of ppdma input path requires
* reg_dac_1/0_data_sel = 1
* 0:no change
*/
#define DAC_PDMA_ALTER_MODE (BIT(0))
#define DAC_PDMA_ALTER_MODE_M (DAC_PDMA_ALTER_MODE_V << DAC_PDMA_ALTER_MODE_S)
#define DAC_PDMA_ALTER_MODE_V 0x00000001U
#define DAC_PDMA_ALTER_MODE_S 0
/** DAC_PDMA_RESET_FIFO : WT; bitpos: [1]; default: 0;
* 1:reset dac fifo
* 0:no change
*/
#define DAC_PDMA_RESET_FIFO (BIT(1))
#define DAC_PDMA_RESET_FIFO_M (DAC_PDMA_RESET_FIFO_V << DAC_PDMA_RESET_FIFO_S)
#define DAC_PDMA_RESET_FIFO_V 0x00000001U
#define DAC_PDMA_RESET_FIFO_S 1
/** DAC_PDMA_TRANS : R/W; bitpos: [2]; default: 0;
* 1:start transaction for pdma path output
* 0:stop transaction for pdma path output
*/
#define DAC_PDMA_TRANS (BIT(2))
#define DAC_PDMA_TRANS_M (DAC_PDMA_TRANS_V << DAC_PDMA_TRANS_S)
#define DAC_PDMA_TRANS_V 0x00000001U
#define DAC_PDMA_TRANS_S 2
/** DAC_PDMA_TIMER_CFG_REG register
* PDMA path timer register
*/
#define DAC_PDMA_TIMER_CFG_REG (DR_REG_DAC_BASE + 0xc)
/** DAC_PDMA_TIMER_EN : R/W; bitpos: [0]; default: 0;
* 1:enables using dac timer to reduce output frequency
* 0:no data output
*/
#define DAC_PDMA_TIMER_EN (BIT(0))
#define DAC_PDMA_TIMER_EN_M (DAC_PDMA_TIMER_EN_V << DAC_PDMA_TIMER_EN_S)
#define DAC_PDMA_TIMER_EN_V 0x00000001U
#define DAC_PDMA_TIMER_EN_S 0
/** DAC_PDMA_TIMER_TARGET : R/W; bitpos: [24:1]; default: 2;
* dac pdma timer wait target
*/
#define DAC_PDMA_TIMER_TARGET 0x00FFFFFFU
#define DAC_PDMA_TIMER_TARGET_M (DAC_PDMA_TIMER_TARGET_V << DAC_PDMA_TIMER_TARGET_S)
#define DAC_PDMA_TIMER_TARGET_V 0x00FFFFFFU
#define DAC_PDMA_TIMER_TARGET_S 1
/** DAC_DATA_OUTPUT_CFG_REG register
* dac DATA OUTPUT cfg register
*/
#define DAC_DATA_OUTPUT_CFG_REG (DR_REG_DAC_BASE + 0x10)
/** DAC_PAD_0_DATA_SEL : R/W; bitpos: [0]; default: 0;
* 1:output pdma data
* 0:output sintx data
*/
#define DAC_PAD_0_DATA_SEL (BIT(0))
#define DAC_PAD_0_DATA_SEL_M (DAC_PAD_0_DATA_SEL_V << DAC_PAD_0_DATA_SEL_S)
#define DAC_PAD_0_DATA_SEL_V 0x00000001U
#define DAC_PAD_0_DATA_SEL_S 0
/** DAC_PAD_1_DATA_SEL : R/W; bitpos: [1]; default: 0;
* 1:output pdma data
* 0:output sintx data
*/
#define DAC_PAD_1_DATA_SEL (BIT(1))
#define DAC_PAD_1_DATA_SEL_M (DAC_PAD_1_DATA_SEL_V << DAC_PAD_1_DATA_SEL_S)
#define DAC_PAD_1_DATA_SEL_V 0x00000001U
#define DAC_PAD_1_DATA_SEL_S 1
/** DAC_SINTX_CFG_REG register
* dac rstn register
*/
#define DAC_SINTX_CFG_REG (DR_REG_DAC_BASE + 0x14)
/** DAC_SW_TONE : R/W; bitpos: [0]; default: 0;
* 1:enable software adjusting current sintx output data
* 0:disable software adjustment
*/
#define DAC_SW_TONE (BIT(0))
#define DAC_SW_TONE_M (DAC_SW_TONE_V << DAC_SW_TONE_S)
#define DAC_SW_TONE_V 0x00000001U
#define DAC_SW_TONE_S 0
/** DAC_SW_FSTEP : R/W; bitpos: [16:1]; default: 1;
* software adjust angle velocity foot step for sintx LUT input
*/
#define DAC_SW_FSTEP 0x0000FFFFU
#define DAC_SW_FSTEP_M (DAC_SW_FSTEP_V << DAC_SW_FSTEP_S)
#define DAC_SW_FSTEP_V 0x0000FFFFU
#define DAC_SW_FSTEP_S 1
/** DAC_SCALE_1 : R/W; bitpos: [18:17]; default: 0;
* right shift scaling config for LUT output of sintx for pad 0
*/
#define DAC_SCALE_1 0x00000003U
#define DAC_SCALE_1_M (DAC_SCALE_1_V << DAC_SCALE_1_S)
#define DAC_SCALE_1_V 0x00000003U
#define DAC_SCALE_1_S 17
/** DAC_SCALE_2 : R/W; bitpos: [20:19]; default: 0;
* software adjust angle velocity foot step for sintx LUT input
*/
#define DAC_SCALE_2 0x00000003U
#define DAC_SCALE_2_M (DAC_SCALE_2_V << DAC_SCALE_2_S)
#define DAC_SCALE_2_V 0x00000003U
#define DAC_SCALE_2_S 19
/** DAC_INV_1 : R/W; bitpos: [22:21]; default: 0;
* bit 1: invert the highest bit of output for pad 0
* Bit 0: invert the entire output for pad 0
*/
#define DAC_INV_1 0x00000003U
#define DAC_INV_1_M (DAC_INV_1_V << DAC_INV_1_S)
#define DAC_INV_1_V 0x00000003U
#define DAC_INV_1_S 21
/** DAC_INV_2 : R/W; bitpos: [24:23]; default: 0;
* bit 1: invert the highest bit of output for pad 1
* Bit 0: invert the entire output for pad 1
*/
#define DAC_INV_2 0x00000003U
#define DAC_INV_2_M (DAC_INV_2_V << DAC_INV_2_S)
#define DAC_INV_2_V 0x00000003U
#define DAC_INV_2_S 23
/** DAC_SINTX_TIMER_CFG_REG register
* SINTX path timer register
*/
#define DAC_SINTX_TIMER_CFG_REG (DR_REG_DAC_BASE + 0x18)
/** DAC_SINTX_TIMER_EN : R/W; bitpos: [0]; default: 0;
* 1:enables using dac timer to reduce output frequency
* 0:no data output
*/
#define DAC_SINTX_TIMER_EN (BIT(0))
#define DAC_SINTX_TIMER_EN_M (DAC_SINTX_TIMER_EN_V << DAC_SINTX_TIMER_EN_S)
#define DAC_SINTX_TIMER_EN_V 0x00000001U
#define DAC_SINTX_TIMER_EN_S 0
/** DAC_SINTX_TIMER_TARGET : R/W; bitpos: [24:1]; default: 2;
* dac sintx timer wait target
*/
#define DAC_SINTX_TIMER_TARGET 0x00FFFFFFU
#define DAC_SINTX_TIMER_TARGET_M (DAC_SINTX_TIMER_TARGET_V << DAC_SINTX_TIMER_TARGET_S)
#define DAC_SINTX_TIMER_TARGET_V 0x00FFFFFFU
#define DAC_SINTX_TIMER_TARGET_S 1
/** DAC_SINTX_DATA_REG register
* dac output register for sintx path
*/
#define DAC_SINTX_DATA_REG (DR_REG_DAC_BASE + 0x1c)
/** DAC_DC_1 : R/W; bitpos: [11:0]; default: 0;
* the data output for DAC PAD0 for sintx path
*/
#define DAC_DC_1 0x00000FFFU
#define DAC_DC_1_M (DAC_DC_1_V << DAC_DC_1_S)
#define DAC_DC_1_V 0x00000FFFU
#define DAC_DC_1_S 0
/** DAC_DC_2 : R/W; bitpos: [23:12]; default: 0;
* the data output for DAC PAD1 for sintx path
*/
#define DAC_DC_2 0x00000FFFU
#define DAC_DC_2_M (DAC_DC_2_V << DAC_DC_2_S)
#define DAC_DC_2_V 0x00000FFFU
#define DAC_DC_2_S 12
/** DAC_CALI_REG register
* cali algorithm register for DAC
*/
#define DAC_CALI_REG (DR_REG_DAC_BASE + 0x20)
/** DAC_CALI_OUT_PAD_0 : RO; bitpos: [0]; default: 0;
* cali out from DAC PAD 0
*/
#define DAC_CALI_OUT_PAD_0 (BIT(0))
#define DAC_CALI_OUT_PAD_0_M (DAC_CALI_OUT_PAD_0_V << DAC_CALI_OUT_PAD_0_S)
#define DAC_CALI_OUT_PAD_0_V 0x00000001U
#define DAC_CALI_OUT_PAD_0_S 0
/** DAC_CALI_OUT_PAD_1 : RO; bitpos: [1]; default: 0;
* cali out from DAC PAD 1
*/
#define DAC_CALI_OUT_PAD_1 (BIT(1))
#define DAC_CALI_OUT_PAD_1_M (DAC_CALI_OUT_PAD_1_V << DAC_CALI_OUT_PAD_1_S)
#define DAC_CALI_OUT_PAD_1_V 0x00000001U
#define DAC_CALI_OUT_PAD_1_S 1
/** DAC_SAMPLE_WAIT_CFG_REG register
* cali sample phase duration register
*/
#define DAC_SAMPLE_WAIT_CFG_REG (DR_REG_DAC_BASE + 0x24)
/** DAC_WAIT_TARGET_SAMPLE_PAD_0 : R/W; bitpos: [15:0]; default: 630;
* sample wait target for DAC PAD 1
*/
#define DAC_WAIT_TARGET_SAMPLE_PAD_0 0x0000FFFFU
#define DAC_WAIT_TARGET_SAMPLE_PAD_0_M (DAC_WAIT_TARGET_SAMPLE_PAD_0_V << DAC_WAIT_TARGET_SAMPLE_PAD_0_S)
#define DAC_WAIT_TARGET_SAMPLE_PAD_0_V 0x0000FFFFU
#define DAC_WAIT_TARGET_SAMPLE_PAD_0_S 0
/** DAC_WAIT_TARGET_SAMPLE_PAD_1 : R/W; bitpos: [31:16]; default: 630;
* sample wait target for DAC PAD 0
*/
#define DAC_WAIT_TARGET_SAMPLE_PAD_1 0x0000FFFFU
#define DAC_WAIT_TARGET_SAMPLE_PAD_1_M (DAC_WAIT_TARGET_SAMPLE_PAD_1_V << DAC_WAIT_TARGET_SAMPLE_PAD_1_S)
#define DAC_WAIT_TARGET_SAMPLE_PAD_1_V 0x0000FFFFU
#define DAC_WAIT_TARGET_SAMPLE_PAD_1_S 16
/** DAC_HOLD_WAIT_CFG_REG register
* cali hold phase duration register
*/
#define DAC_HOLD_WAIT_CFG_REG (DR_REG_DAC_BASE + 0x28)
/** DAC_WAIT_TARGET_HOLD_PAD_0 : R/W; bitpos: [15:0]; default: 61;
* hold wait target for DAC PAD 0
*/
#define DAC_WAIT_TARGET_HOLD_PAD_0 0x0000FFFFU
#define DAC_WAIT_TARGET_HOLD_PAD_0_M (DAC_WAIT_TARGET_HOLD_PAD_0_V << DAC_WAIT_TARGET_HOLD_PAD_0_S)
#define DAC_WAIT_TARGET_HOLD_PAD_0_V 0x0000FFFFU
#define DAC_WAIT_TARGET_HOLD_PAD_0_S 0
/** DAC_WAIT_TARGET_HOLD_PAD_1 : R/W; bitpos: [31:16]; default: 61;
* hold wait target for DAC PAD 1
*/
#define DAC_WAIT_TARGET_HOLD_PAD_1 0x0000FFFFU
#define DAC_WAIT_TARGET_HOLD_PAD_1_M (DAC_WAIT_TARGET_HOLD_PAD_1_V << DAC_WAIT_TARGET_HOLD_PAD_1_S)
#define DAC_WAIT_TARGET_HOLD_PAD_1_V 0x0000FFFFU
#define DAC_WAIT_TARGET_HOLD_PAD_1_S 16
/** DAC_REFRESH_WAIT_CFG_REG register
* cali refresh phase duration register
*/
#define DAC_REFRESH_WAIT_CFG_REG (DR_REG_DAC_BASE + 0x2c)
/** DAC_WAIT_TARGET_REFRESH_PAD_0 : R/W; bitpos: [15:0]; default: 8;
* refresh wait target for DAC PAD 0
*/
#define DAC_WAIT_TARGET_REFRESH_PAD_0 0x0000FFFFU
#define DAC_WAIT_TARGET_REFRESH_PAD_0_M (DAC_WAIT_TARGET_REFRESH_PAD_0_V << DAC_WAIT_TARGET_REFRESH_PAD_0_S)
#define DAC_WAIT_TARGET_REFRESH_PAD_0_V 0x0000FFFFU
#define DAC_WAIT_TARGET_REFRESH_PAD_0_S 0
/** DAC_WAIT_TARGET_REFRESH_PAD_1 : R/W; bitpos: [31:16]; default: 8;
* refresh wait target for DAC PAD 1
*/
#define DAC_WAIT_TARGET_REFRESH_PAD_1 0x0000FFFFU
#define DAC_WAIT_TARGET_REFRESH_PAD_1_M (DAC_WAIT_TARGET_REFRESH_PAD_1_V << DAC_WAIT_TARGET_REFRESH_PAD_1_S)
#define DAC_WAIT_TARGET_REFRESH_PAD_1_V 0x0000FFFFU
#define DAC_WAIT_TARGET_REFRESH_PAD_1_S 16
/** DAC_PDMA_INT_RAW_REG register
* need_des
*/
#define DAC_PDMA_INT_RAW_REG (DR_REG_DAC_BASE + 0x30)
/** DAC_PDMA_EMPTY_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define DAC_PDMA_EMPTY_INT_RAW (BIT(31))
#define DAC_PDMA_EMPTY_INT_RAW_M (DAC_PDMA_EMPTY_INT_RAW_V << DAC_PDMA_EMPTY_INT_RAW_S)
#define DAC_PDMA_EMPTY_INT_RAW_V 0x00000001U
#define DAC_PDMA_EMPTY_INT_RAW_S 31
/** DAC_INT_ST_REG register
* need_des
*/
#define DAC_INT_ST_REG (DR_REG_DAC_BASE + 0x34)
/** DAC_PDMA_EMPTY_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define DAC_PDMA_EMPTY_INT_ST (BIT(31))
#define DAC_PDMA_EMPTY_INT_ST_M (DAC_PDMA_EMPTY_INT_ST_V << DAC_PDMA_EMPTY_INT_ST_S)
#define DAC_PDMA_EMPTY_INT_ST_V 0x00000001U
#define DAC_PDMA_EMPTY_INT_ST_S 31
/** DAC_INT_ENA_REG register
* need_des
*/
#define DAC_INT_ENA_REG (DR_REG_DAC_BASE + 0x38)
/** DAC_PDMA_EMPTY_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define DAC_PDMA_EMPTY_INT_ENA (BIT(31))
#define DAC_PDMA_EMPTY_INT_ENA_M (DAC_PDMA_EMPTY_INT_ENA_V << DAC_PDMA_EMPTY_INT_ENA_S)
#define DAC_PDMA_EMPTY_INT_ENA_V 0x00000001U
#define DAC_PDMA_EMPTY_INT_ENA_S 31
/** DAC_INT_CLR_REG register
* need_des
*/
#define DAC_INT_CLR_REG (DR_REG_DAC_BASE + 0x3c)
/** DAC_PDMA_EMPTY_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define DAC_PDMA_EMPTY_INT_CLR (BIT(31))
#define DAC_PDMA_EMPTY_INT_CLR_M (DAC_PDMA_EMPTY_INT_CLR_V << DAC_PDMA_EMPTY_INT_CLR_S)
#define DAC_PDMA_EMPTY_INT_CLR_V 0x00000001U
#define DAC_PDMA_EMPTY_INT_CLR_S 31
/** DAC_DATE_REG register
* need_des
*/
#define DAC_DATE_REG (DR_REG_DAC_BASE + 0x3fc)
/** DAC_DATE : R/W; bitpos: [30:0]; default: 2426393;
* need_des
*/
#define DAC_DATE 0x7FFFFFFFU
#define DAC_DATE_M (DAC_DATE_V << DAC_DATE_S)
#define DAC_DATE_V 0x7FFFFFFFU
#define DAC_DATE_S 0
/** DAC_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define DAC_CLK_EN (BIT(31))
#define DAC_CLK_EN_M (DAC_CLK_EN_V << DAC_CLK_EN_S)
#define DAC_CLK_EN_V 0x00000001U
#define DAC_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/dac_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of pad_cfg register
* configure dac pad register
*/
typedef union {
struct {
/** hs_mode_pad_0 : R/W; bitpos: [0]; default: 0;
* 1 to let DAC PAD 0 enter High speed mode
*/
uint32_t hs_mode_pad_0:1;
/** xpd_pad_0 : R/W; bitpos: [1]; default: 0;
* 1 to power on DAC PAD 0
*/
uint32_t xpd_pad_0:1;
/** en_adc_mux_pad_0 : R/W; bitpos: [2]; default: 0;
* 1 to enable adc mux for DAC PAD 0
*/
uint32_t en_adc_mux_pad_0:1;
/** dsamp_ls_pad_0 : R/W; bitpos: [3]; default: 0;
* 1 to start sample and hold mode for DAC PAD 0
*/
uint32_t dsamp_ls_pad_0:1;
/** dcal_ls_pad_0 : R/W; bitpos: [4]; default: 0;
* 1 to Calibrate the buffer of DAC PAD 0 (DBUF of pad 1 must be 1 during this
* operation)
*/
uint32_t dcal_ls_pad_0:1;
/** dbuf_ls_pad_0 : R/W; bitpos: [5]; default: 0;
* 1 to turn on the buffer of DAC PAD 0
*/
uint32_t dbuf_ls_pad_0:1;
/** on_ls_pad_0 : R/W; bitpos: [6]; default: 0;
* 1 to turn on the DAC PAD 0 during sample and hold mode
*/
uint32_t on_ls_pad_0:1;
/** hs_mode_pad_1 : R/W; bitpos: [7]; default: 0;
* 1 to let DAC PAD 1 enter High speed mode
*/
uint32_t hs_mode_pad_1:1;
/** xpd_pad_1 : R/W; bitpos: [8]; default: 0;
* 1 to power on DAC PAD 1
*/
uint32_t xpd_pad_1:1;
/** en_adc_mux_pad_1 : R/W; bitpos: [9]; default: 0;
* 1 to enable adc mux for DAC PAD 1
*/
uint32_t en_adc_mux_pad_1:1;
/** dsamp_ls_pad_1 : R/W; bitpos: [10]; default: 0;
* 1 to start sample and hold mode for DAC PAD 1
*/
uint32_t dsamp_ls_pad_1:1;
/** dcal_ls_pad_1 : R/W; bitpos: [11]; default: 0;
* 1 to Calibrate the buffer of DAC PAD 1 (DBUF of pad 1 must be 1 during this
* operation)
*/
uint32_t dcal_ls_pad_1:1;
/** dbuf_ls_pad_1 : R/W; bitpos: [12]; default: 0;
* 1 to turn on the buffer of DAC PAD 1
*/
uint32_t dbuf_ls_pad_1:1;
/** on_ls_pad_1 : R/W; bitpos: [13]; default: 0;
* 1 to turn on the DAC PAD 1 during sample and hold mode
*/
uint32_t on_ls_pad_1:1;
/** div_num : R/W; bitpos: [29:14]; default: 1;
* divide number between clk ls and clk hs
*/
uint32_t div_num:16;
/** dbuf_range_ls_pad_0 : R/W; bitpos: [30]; default: 0;
* 1:when buffer is activated, allow using full code of maximum bitwidth
* 0:when buffer is not activated, should always be 0
*/
uint32_t dbuf_range_ls_pad_0:1;
/** dbuf_range_ls_pad_1 : R/W; bitpos: [31]; default: 0;
* 1:when buffer is activated, allow using full code of maximum bitwidth
* 0:when buffer is not activated, should always be 0
*/
uint32_t dbuf_range_ls_pad_1:1;
};
uint32_t val;
} dac_pad_cfg_reg_t;
/** Type of cali_result register
* DAC CALI result register
*/
typedef union {
struct {
/** cali_result_pad_0 : R/W; bitpos: [11:0]; default: 0;
* cali result register for pad 0 output
*/
uint32_t cali_result_pad_0:12;
/** cali_result_pad_1 : R/W; bitpos: [23:12]; default: 0;
* cali result register for pad 1 output
*/
uint32_t cali_result_pad_1:12;
uint32_t reserved_24:8;
};
uint32_t val;
} dac_cali_result_reg_t;
/** Type of pdma_cfg register
* dac cfg register
*/
typedef union {
struct {
/** pdma_alter_mode : R/W; bitpos: [0]; default: 0;
* 1:make rotation between two pads when outputting data of ppdma input path requires
* reg_dac_1/0_data_sel = 1
* 0:no change
*/
uint32_t pdma_alter_mode:1;
/** pdma_reset_fifo : WT; bitpos: [1]; default: 0;
* 1:reset dac fifo
* 0:no change
*/
uint32_t pdma_reset_fifo:1;
/** pdma_trans : R/W; bitpos: [2]; default: 0;
* 1:start transaction for pdma path output
* 0:stop transaction for pdma path output
*/
uint32_t pdma_trans:1;
uint32_t reserved_3:29;
};
uint32_t val;
} dac_pdma_cfg_reg_t;
/** Type of pdma_timer_cfg register
* PDMA path timer register
*/
typedef union {
struct {
/** pdma_timer_en : R/W; bitpos: [0]; default: 0;
* 1:enables using dac timer to reduce output frequency
* 0:no data output
*/
uint32_t pdma_timer_en:1;
/** pdma_timer_target : R/W; bitpos: [24:1]; default: 2;
* dac pdma timer wait target
*/
uint32_t pdma_timer_target:24;
uint32_t reserved_25:7;
};
uint32_t val;
} dac_pdma_timer_cfg_reg_t;
/** Type of data_output_cfg register
* dac DATA OUTPUT cfg register
*/
typedef union {
struct {
/** pad_0_data_sel : R/W; bitpos: [0]; default: 0;
* 1:output pdma data
* 0:output sintx data
*/
uint32_t pad_0_data_sel:1;
/** pad_1_data_sel : R/W; bitpos: [1]; default: 0;
* 1:output pdma data
* 0:output sintx data
*/
uint32_t pad_1_data_sel:1;
uint32_t reserved_2:30;
};
uint32_t val;
} dac_data_output_cfg_reg_t;
/** Type of sintx_cfg register
* dac rstn register
*/
typedef union {
struct {
/** sw_tone : R/W; bitpos: [0]; default: 0;
* 1:enable software adjusting current sintx output data
* 0:disable software adjustment
*/
uint32_t sw_tone:1;
/** sw_fstep : R/W; bitpos: [16:1]; default: 1;
* software adjust angle velocity foot step for sintx LUT input
*/
uint32_t sw_fstep:16;
/** scale_1 : R/W; bitpos: [18:17]; default: 0;
* right shift scaling config for LUT output of sintx for pad 0
*/
uint32_t scale_1:2;
/** scale_2 : R/W; bitpos: [20:19]; default: 0;
* software adjust angle velocity foot step for sintx LUT input
*/
uint32_t scale_2:2;
/** inv_1 : R/W; bitpos: [22:21]; default: 0;
* bit 1: invert the highest bit of output for pad 0
* Bit 0: invert the entire output for pad 0
*/
uint32_t inv_1:2;
/** inv_2 : R/W; bitpos: [24:23]; default: 0;
* bit 1: invert the highest bit of output for pad 1
* Bit 0: invert the entire output for pad 1
*/
uint32_t inv_2:2;
uint32_t reserved_25:7;
};
uint32_t val;
} dac_sintx_cfg_reg_t;
/** Type of sintx_timer_cfg register
* SINTX path timer register
*/
typedef union {
struct {
/** sintx_timer_en : R/W; bitpos: [0]; default: 0;
* 1:enables using dac timer to reduce output frequency
* 0:no data output
*/
uint32_t sintx_timer_en:1;
/** sintx_timer_target : R/W; bitpos: [24:1]; default: 2;
* dac sintx timer wait target
*/
uint32_t sintx_timer_target:24;
uint32_t reserved_25:7;
};
uint32_t val;
} dac_sintx_timer_cfg_reg_t;
/** Type of sintx_data register
* dac output register for sintx path
*/
typedef union {
struct {
/** dc_1 : R/W; bitpos: [11:0]; default: 0;
* the data output for DAC PAD0 for sintx path
*/
uint32_t dc_1:12;
/** dc_2 : R/W; bitpos: [23:12]; default: 0;
* the data output for DAC PAD1 for sintx path
*/
uint32_t dc_2:12;
uint32_t reserved_24:8;
};
uint32_t val;
} dac_sintx_data_reg_t;
/** Type of cali register
* cali algorithm register for DAC
*/
typedef union {
struct {
/** cali_out_pad_0 : RO; bitpos: [0]; default: 0;
* cali out from DAC PAD 0
*/
uint32_t cali_out_pad_0:1;
/** cali_out_pad_1 : RO; bitpos: [1]; default: 0;
* cali out from DAC PAD 1
*/
uint32_t cali_out_pad_1:1;
uint32_t reserved_2:30;
};
uint32_t val;
} dac_cali_reg_t;
/** Type of sample_wait_cfg register
* cali sample phase duration register
*/
typedef union {
struct {
/** wait_target_sample_pad_0 : R/W; bitpos: [15:0]; default: 630;
* sample wait target for DAC PAD 1
*/
uint32_t wait_target_sample_pad_0:16;
/** wait_target_sample_pad_1 : R/W; bitpos: [31:16]; default: 630;
* sample wait target for DAC PAD 0
*/
uint32_t wait_target_sample_pad_1:16;
};
uint32_t val;
} dac_sample_wait_cfg_reg_t;
/** Type of hold_wait_cfg register
* cali hold phase duration register
*/
typedef union {
struct {
/** wait_target_hold_pad_0 : R/W; bitpos: [15:0]; default: 61;
* hold wait target for DAC PAD 0
*/
uint32_t wait_target_hold_pad_0:16;
/** wait_target_hold_pad_1 : R/W; bitpos: [31:16]; default: 61;
* hold wait target for DAC PAD 1
*/
uint32_t wait_target_hold_pad_1:16;
};
uint32_t val;
} dac_hold_wait_cfg_reg_t;
/** Type of refresh_wait_cfg register
* cali refresh phase duration register
*/
typedef union {
struct {
/** wait_target_refresh_pad_0 : R/W; bitpos: [15:0]; default: 8;
* refresh wait target for DAC PAD 0
*/
uint32_t wait_target_refresh_pad_0:16;
/** wait_target_refresh_pad_1 : R/W; bitpos: [31:16]; default: 8;
* refresh wait target for DAC PAD 1
*/
uint32_t wait_target_refresh_pad_1:16;
};
uint32_t val;
} dac_refresh_wait_cfg_reg_t;
/** Type of pdma_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** pdma_empty_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t pdma_empty_int_raw:1;
};
uint32_t val;
} dac_pdma_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** pdma_empty_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t pdma_empty_int_st:1;
};
uint32_t val;
} dac_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** pdma_empty_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t pdma_empty_int_ena:1;
};
uint32_t val;
} dac_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** pdma_empty_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t pdma_empty_int_clr:1;
};
uint32_t val;
} dac_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 2426393;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} dac_date_reg_t;
typedef struct {
volatile dac_pad_cfg_reg_t pad_cfg;
volatile dac_cali_result_reg_t cali_result;
volatile dac_pdma_cfg_reg_t pdma_cfg;
volatile dac_pdma_timer_cfg_reg_t pdma_timer_cfg;
volatile dac_data_output_cfg_reg_t data_output_cfg;
volatile dac_sintx_cfg_reg_t sintx_cfg;
volatile dac_sintx_timer_cfg_reg_t sintx_timer_cfg;
volatile dac_sintx_data_reg_t sintx_data;
volatile dac_cali_reg_t cali;
volatile dac_sample_wait_cfg_reg_t sample_wait_cfg;
volatile dac_hold_wait_cfg_reg_t hold_wait_cfg;
volatile dac_refresh_wait_cfg_reg_t refresh_wait_cfg;
volatile dac_pdma_int_raw_reg_t pdma_int_raw;
volatile dac_int_st_reg_t int_st;
volatile dac_int_ena_reg_t int_ena;
volatile dac_int_clr_reg_t int_clr;
uint32_t reserved_040[239];
volatile dac_date_reg_t date;
} dac_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(dac_dev_t) == 0x400, "Invalid size of dac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
* memory that stores Y
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
* memory that stores M
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
* memory that stores Rb
*/
#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
#define DS_RB_MEM_SIZE_BYTES 512
/** DS_BOX_MEM register
* memory that stores BOX
*/
#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
#define DS_BOX_MEM_SIZE_BYTES 48
/** DS_IV_MEM register
* memory that stores IV
*/
#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
#define DS_IV_MEM_SIZE_BYTES 16
/** DS_X_MEM register
* memory that stores X
*/
#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
#define DS_X_MEM_SIZE_BYTES 512
/** DS_Z_MEM register
* memory that stores Z
*/
#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
#define DS_Z_MEM_SIZE_BYTES 512
/** DS_SET_START_REG register
* Activates the DS module
*/
#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
/** DS_SET_START : WT; bitpos: [0]; default: 0;
* Configures whether or not to activate the DS peripheral.
* 0: Invalid
* 1: Activate the DS peripheral
*/
#define DS_SET_START (BIT(0))
#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
#define DS_SET_START_V 0x00000001U
#define DS_SET_START_S 0
/** DS_SET_CONTINUE_REG register
* DS continue control register
*/
#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
#define DS_SET_CONTINUE (BIT(0))
#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
#define DS_SET_CONTINUE_V 0x00000001U
#define DS_SET_CONTINUE_S 0
/** DS_SET_FINISH_REG register
* Ends DS operation
*/
#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
* Configures whether or not to end DS operation.
* 0: Invalid
* 1: End DS operation
*/
#define DS_SET_FINISH (BIT(0))
#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
#define DS_SET_FINISH_V 0x00000001U
#define DS_SET_FINISH_S 0
/** DS_QUERY_BUSY_REG register
* Status of the DS module
*/
#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
* Represents whether or not the DS module is idle.
* 0: The DS module is idle
* 1: The DS module is busy
*/
#define DS_QUERY_BUSY (BIT(0))
#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
#define DS_QUERY_BUSY_V 0x00000001U
#define DS_QUERY_BUSY_S 0
/** DS_QUERY_KEY_WRONG_REG register
* Checks the reason why \begin{math}DS_KEY\end{math} is not ready
*/
#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
* Represents the specific problem with HMAC initialization.
* 0: HMAC is not called
* 1-15: HMAC was activated, but the DS peripheral did not successfully receive the
* \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
*/
#define DS_QUERY_KEY_WRONG 0x0000000FU
#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
#define DS_QUERY_KEY_WRONG_V 0x0000000FU
#define DS_QUERY_KEY_WRONG_S 0
/** DS_QUERY_CHECK_REG register
* Queries DS check result
*/
#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
* Represents whether or not the MD check passes.
* 0: The MD check passes
* 1: The MD check fails
*/
#define DS_MD_ERROR (BIT(0))
#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
#define DS_MD_ERROR_V 0x00000001U
#define DS_MD_ERROR_S 0
/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
* Represents whether or not the padding check passes.
* 0: The padding check passes
* 1: The padding check fails
*/
#define DS_PADDING_BAD (BIT(1))
#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
#define DS_PADDING_BAD_V 0x00000001U
#define DS_PADDING_BAD_S 1
/** DS_STATIC_REG register
* DS configure key source register
*/
#define DS_STATIC_REG (DR_REG_DS_BASE + 0xe18)
/** DS_KEY_SOURCE : R/W; bitpos: [0]; default: 0;
* digital signature key source bit.
* 1'b0: key is from hmac.
* 1'b1: key is from key manager.
*/
#define DS_KEY_SOURCE (BIT(0))
#define DS_KEY_SOURCE_M (DS_KEY_SOURCE_V << DS_KEY_SOURCE_S)
#define DS_KEY_SOURCE_V 0x00000001U
#define DS_KEY_SOURCE_S 0
/** DS_SKIP_PADDING_CHECK : R/W; bitpos: [1]; default: 0;
* digital signature padding check bypass bit.
* 1'b0: padding check enabled.
* 1'b1: padding check skipped.
*/
#define DS_SKIP_PADDING_CHECK (BIT(1))
#define DS_SKIP_PADDING_CHECK_M (DS_SKIP_PADDING_CHECK_V << DS_SKIP_PADDING_CHECK_S)
#define DS_SKIP_PADDING_CHECK_V 0x00000001U
#define DS_SKIP_PADDING_CHECK_S 1
/** DS_DATE_REG register
* DS version control register
*/
#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
/** DS_DATE : R/W; bitpos: [29:0]; default: 539297817;
* ds version information
*/
#define DS_DATE 0x3FFFFFFFU
#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
#define DS_DATE_V 0x3FFFFFFFU
#define DS_DATE_S 0
/** DS_TIMEOUT_LIMIT_REG register
* DS timeout limit configure register
*/
#define DS_TIMEOUT_LIMIT_REG (DR_REG_DS_BASE + 0xe24)
/** DS_TIMEOUT_LIMIT : R/W; bitpos: [31:0]; default: 4294967295;
* The timeout limitation for waiting sub-IP.
*/
#define DS_TIMEOUT_LIMIT 0xFFFFFFFFU
#define DS_TIMEOUT_LIMIT_M (DS_TIMEOUT_LIMIT_V << DS_TIMEOUT_LIMIT_S)
#define DS_TIMEOUT_LIMIT_V 0xFFFFFFFFU
#define DS_TIMEOUT_LIMIT_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
* Activates the DS module
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
* Configures whether or not to activate the DS peripheral.
* 0: Invalid
* 1: Activate the DS peripheral
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_start_reg_t;
/** Type of set_continue register
* DS continue control register
*/
typedef union {
struct {
/** set_continue : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
uint32_t set_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_continue_reg_t;
/** Type of set_finish register
* Ends DS operation
*/
typedef union {
struct {
/** set_finish : WT; bitpos: [0]; default: 0;
* Configures whether or not to end DS operation.
* 0: Invalid
* 1: End DS operation
*/
uint32_t set_finish:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_finish_reg_t;
/** Type of query_busy register
* Status of the DS module
*/
typedef union {
struct {
/** query_busy : RO; bitpos: [0]; default: 0;
* Represents whether or not the DS module is idle.
* 0: The DS module is idle
* 1: The DS module is busy
*/
uint32_t query_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_query_busy_reg_t;
/** Type of query_key_wrong register
* Checks the reason why \begin{math}DS_KEY\end{math} is not ready
*/
typedef union {
struct {
/** query_key_wrong : RO; bitpos: [3:0]; default: 0;
* Represents the specific problem with HMAC initialization.
* 0: HMAC is not called
* 1-15: HMAC was activated, but the DS peripheral did not successfully receive the
* \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
*/
uint32_t query_key_wrong:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ds_query_key_wrong_reg_t;
/** Type of query_check register
* Queries DS check result
*/
typedef union {
struct {
/** md_error : RO; bitpos: [0]; default: 0;
* Represents whether or not the MD check passes.
* 0: The MD check passes
* 1: The MD check fails
*/
uint32_t md_error:1;
/** padding_bad : RO; bitpos: [1]; default: 0;
* Represents whether or not the padding check passes.
* 0: The padding check passes
* 1: The padding check fails
*/
uint32_t padding_bad:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_query_check_reg_t;
/** Group: Configuration registers */
/** Type of static register
* DS configure key source register
*/
typedef union {
struct {
/** key_source : R/W; bitpos: [0]; default: 0;
* digital signature key source bit.
* 1'b0: key is from hmac.
* 1'b1: key is from key manager.
*/
uint32_t key_source:1;
/** skip_padding_check : R/W; bitpos: [1]; default: 0;
* digital signature padding check bypass bit.
* 1'b0: padding check enabled.
* 1'b1: padding check skipped.
*/
uint32_t skip_padding_check:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_static_reg_t;
/** Type of timeout_limit register
* DS timeout limit configure register
*/
typedef union {
struct {
/** timeout_limit : R/W; bitpos: [31:0]; default: 4294967295;
* The timeout limitation for waiting sub-IP.
*/
uint32_t timeout_limit:32;
};
uint32_t val;
} ds_timeout_limit_reg_t;
/** Group: version control register */
/** Type of date register
* DS version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 539297817;
* ds version information
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} ds_date_reg_t;
typedef struct {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];
volatile uint32_t box[12];
volatile uint32_t iv[4];
uint32_t reserved_640[112];
volatile uint32_t x[128];
volatile uint32_t z[128];
uint32_t reserved_c00[128];
volatile ds_set_start_reg_t set_start;
volatile ds_set_continue_reg_t set_continue;
volatile ds_set_finish_reg_t set_finish;
volatile ds_query_busy_reg_t query_busy;
volatile ds_query_key_wrong_reg_t query_key_wrong;
volatile ds_query_check_reg_t query_check;
volatile ds_static_reg_t static;
uint32_t reserved_e1c;
volatile ds_date_reg_t date;
volatile ds_timeout_limit_reg_t timeout_limit;
} ds_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(ds_dev_t) == 0xe28, "Invalid size of ds_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* ECC raw interrupt status register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* ECC masked interrupt status register
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* ECC interrupt enable register
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* ECC interrupt clear register
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* ECC configuration register
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
* 2: P-384
* 3: SM2.
*/
#define ECC_MULT_KEY_LENGTH 0x00000003U
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000003U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
#define ECC_MULT_MOD_BASE (BIT(4))
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
#define ECC_MULT_MOD_BASE_V 0x00000001U
#define ECC_MULT_MOD_BASE_S 4
/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
#define ECC_MULT_WORK_MODE 0x0000000FU
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x0000000FU
#define ECC_MULT_WORK_MODE_S 5
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
#define ECC_MULT_SECURITY_MODE (BIT(9))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 9
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 29
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_CLK_EN (BIT(30))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 30
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
/** ECC_MULT_FREE_REG register
* ECC free status register
*/
#define ECC_MULT_FREE_REG (DR_REG_ECC_MULT_BASE + 0x20)
/** ECC_MULT_FREE : R/W; bitpos: [0]; default: 1;
* ECC mult free state register
* 0: non-free
* 1: free
*/
#define ECC_MULT_FREE (BIT(0))
#define ECC_MULT_FREE_M (ECC_MULT_FREE_V << ECC_MULT_FREE_S)
#define ECC_MULT_FREE_V 0x00000001U
#define ECC_MULT_FREE_S 0
/** ECC_MULT_DATE_REG register
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 38822288;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
/** ECC_MULT_K_MEM register
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 48
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x130)
#define ECC_MULT_PX_MEM_SIZE_BYTES 48
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x160)
#define ECC_MULT_PY_MEM_SIZE_BYTES 48
/** ECC_MULT_QX_MEM register
* The memory that stores Qx.
*/
#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x190)
#define ECC_MULT_QX_MEM_SIZE_BYTES 48
/** ECC_MULT_QY_MEM register
* The memory that stores Qy.
*/
#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x1c0)
#define ECC_MULT_QY_MEM_SIZE_BYTES 48
/** ECC_MULT_QZ_MEM register
* The memory that stores Qz.
*/
#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1f0)
#define ECC_MULT_QZ_MEM_SIZE_BYTES 48
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/ecc_mult_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
* ECC raw interrupt status register
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of int_st register
* ECC masked interrupt status register
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of int_ena register
* ECC interrupt enable register
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of int_clr register
* ECC interrupt clear register
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of conf register
* ECC configuration register
*/
typedef union {
struct {
/** start : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
uint32_t reset:1;
/** key_length : R/W; bitpos: [3:2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
* 2: P-384
* 3: SM2.
*/
uint32_t key_length:2;
/** mod_base : R/W; bitpos: [4]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
uint32_t mod_base:1;
/** work_mode : R/W; bitpos: [8:5]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
uint32_t work_mode:4;
/** security_mode : R/W; bitpos: [9]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
uint32_t security_mode:1;
uint32_t reserved_10:19;
/** verification_result : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
uint32_t verification_result:1;
/** clk_en : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t clk_en:1;
/** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t mem_clock_gate_force_on:1;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Status registers */
/** Type of free register
* ECC free status register
*/
typedef union {
struct {
/** free : R/W; bitpos: [0]; default: 1;
* ECC mult free state register
* 0: non-free
* 1: free
*/
uint32_t free:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_free_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 38822288;
* ECC mult version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t int_raw;
volatile ecc_mult_int_st_reg_t int_st;
volatile ecc_mult_int_ena_reg_t int_ena;
volatile ecc_mult_int_clr_reg_t int_clr;
volatile ecc_mult_conf_reg_t conf;
volatile ecc_mult_free_reg_t free;
uint32_t reserved_024[54];
volatile ecc_mult_date_reg_t date;
volatile uint32_t k[12];
volatile uint32_t px[12];
volatile uint32_t py[12];
volatile uint32_t qx[12];
volatile uint32_t qy[12];
volatile uint32_t qz[12];
} ecc_mult_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x220, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/ecdsa_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2.
*/
#define ECDSA_ECC_CURVE 0x00000003U
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000003U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(4))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 4
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(5))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 5
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(6))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 6
/** ECDSA_USE_HARDWARE_KEY : R/W; bitpos: [7]; default: 0;
* Configures the ECDSA use software key or hardware key.
* 0: Software key.
* 1: Hardware key.
*/
#define ECDSA_USE_HARDWARE_KEY (BIT(7))
#define ECDSA_USE_HARDWARE_KEY_M (ECDSA_USE_HARDWARE_KEY_V << ECDSA_USE_HARDWARE_KEY_S)
#define ECDSA_USE_HARDWARE_KEY_V 0x00000001U
#define ECDSA_USE_HARDWARE_KEY_S 7
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PREP_DONE_INT_RAW_S 0
/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PROC_DONE_INT_RAW_S 1
/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_RAW (BIT(2))
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
#define ECDSA_POST_DONE_INT_RAW_S 2
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 3
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ST (BIT(0))
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ST_S 0
/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ST (BIT(1))
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ST_S 1
/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ST (BIT(2))
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
#define ECDSA_POST_DONE_INT_ST_S 2
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 3
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ENA_S 0
/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ENA_S 1
/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ENA (BIT(2))
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
#define ECDSA_POST_DONE_INT_ENA_S 2
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 3
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PREP_DONE_INT_CLR_S 0
/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PROC_DONE_INT_CLR_S 1
/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_CLR (BIT(2))
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
#define ECDSA_POST_DONE_INT_CLR_S 2
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 3
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_TIMEOUT_LIMIT_REG register
* ECDSA timeout limit configure register
*/
#define ECDSA_TIMEOUT_LIMIT_REG (DR_REG_ECDSA_BASE + 0x28)
/** ECDSA_TIMEOUT_LIMIT : R/W; bitpos: [31:0]; default: 4294967295;
* The timeout limitation for waiting sub-IP.
*/
#define ECDSA_TIMEOUT_LIMIT 0xFFFFFFFFU
#define ECDSA_TIMEOUT_LIMIT_M (ECDSA_TIMEOUT_LIMIT_V << ECDSA_TIMEOUT_LIMIT_S)
#define ECDSA_TIMEOUT_LIMIT_V 0xFFFFFFFFU
#define ECDSA_TIMEOUT_LIMIT_S 0
/** ECDSA_FREE_REG register
* ECDSA free state
*/
#define ECDSA_FREE_REG (DR_REG_ECDSA_BASE + 0x2c)
/** ECDSA_FREE : R/W; bitpos: [0]; default: 1;
* Represents if ECDSA Accelerator is free or not.
* 0: non-free
* 1: free
*/
#define ECDSA_FREE (BIT(0))
#define ECDSA_FREE_M (ECDSA_FREE_V << ECDSA_FREE_S)
#define ECDSA_FREE_V 0x00000001U
#define ECDSA_FREE_S 0
/** ECDSA_KEY_0_REG register
* ECDSA key data register 0
*/
#define ECDSA_KEY_0_REG (DR_REG_ECDSA_BASE + 0x40)
/** ECDSA_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_0 that is a part of key material.
*/
#define ECDSA_KEY_0 0xFFFFFFFFU
#define ECDSA_KEY_0_M (ECDSA_KEY_0_V << ECDSA_KEY_0_S)
#define ECDSA_KEY_0_V 0xFFFFFFFFU
#define ECDSA_KEY_0_S 0
/** ECDSA_KEY_1_REG register
* ECDSA key data register 1
*/
#define ECDSA_KEY_1_REG (DR_REG_ECDSA_BASE + 0x44)
/** ECDSA_KEY_1 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_1 that is a part of key material.
*/
#define ECDSA_KEY_1 0xFFFFFFFFU
#define ECDSA_KEY_1_M (ECDSA_KEY_1_V << ECDSA_KEY_1_S)
#define ECDSA_KEY_1_V 0xFFFFFFFFU
#define ECDSA_KEY_1_S 0
/** ECDSA_KEY_2_REG register
* ECDSA key data register 2
*/
#define ECDSA_KEY_2_REG (DR_REG_ECDSA_BASE + 0x48)
/** ECDSA_KEY_2 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_2 that is a part of key material.
*/
#define ECDSA_KEY_2 0xFFFFFFFFU
#define ECDSA_KEY_2_M (ECDSA_KEY_2_V << ECDSA_KEY_2_S)
#define ECDSA_KEY_2_V 0xFFFFFFFFU
#define ECDSA_KEY_2_S 0
/** ECDSA_KEY_3_REG register
* ECDSA key data register 3
*/
#define ECDSA_KEY_3_REG (DR_REG_ECDSA_BASE + 0x4c)
/** ECDSA_KEY_3 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_3 that is a part of key material.
*/
#define ECDSA_KEY_3 0xFFFFFFFFU
#define ECDSA_KEY_3_M (ECDSA_KEY_3_V << ECDSA_KEY_3_S)
#define ECDSA_KEY_3_V 0xFFFFFFFFU
#define ECDSA_KEY_3_S 0
/** ECDSA_KEY_4_REG register
* ECDSA key data register 4
*/
#define ECDSA_KEY_4_REG (DR_REG_ECDSA_BASE + 0x50)
/** ECDSA_KEY_4 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_4 that is a part of key material.
*/
#define ECDSA_KEY_4 0xFFFFFFFFU
#define ECDSA_KEY_4_M (ECDSA_KEY_4_V << ECDSA_KEY_4_S)
#define ECDSA_KEY_4_V 0xFFFFFFFFU
#define ECDSA_KEY_4_S 0
/** ECDSA_KEY_5_REG register
* ECDSA key data register 5
*/
#define ECDSA_KEY_5_REG (DR_REG_ECDSA_BASE + 0x54)
/** ECDSA_KEY_5 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_5 that is a part of key material.
*/
#define ECDSA_KEY_5 0xFFFFFFFFU
#define ECDSA_KEY_5_M (ECDSA_KEY_5_V << ECDSA_KEY_5_S)
#define ECDSA_KEY_5_V 0xFFFFFFFFU
#define ECDSA_KEY_5_S 0
/** ECDSA_KEY_6_REG register
* ECDSA key data register 6
*/
#define ECDSA_KEY_6_REG (DR_REG_ECDSA_BASE + 0x58)
/** ECDSA_KEY_6 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_6 that is a part of key material.
*/
#define ECDSA_KEY_6 0xFFFFFFFFU
#define ECDSA_KEY_6_M (ECDSA_KEY_6_V << ECDSA_KEY_6_S)
#define ECDSA_KEY_6_V 0xFFFFFFFFU
#define ECDSA_KEY_6_S 0
/** ECDSA_KEY_7_REG register
* ECDSA key data register 7
*/
#define ECDSA_KEY_7_REG (DR_REG_ECDSA_BASE + 0x5c)
/** ECDSA_KEY_7 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_7 that is a part of key material.
*/
#define ECDSA_KEY_7 0xFFFFFFFFU
#define ECDSA_KEY_7_M (ECDSA_KEY_7_V << ECDSA_KEY_7_S)
#define ECDSA_KEY_7_V 0xFFFFFFFFU
#define ECDSA_KEY_7_S 0
/** ECDSA_KEY_8_REG register
* ECDSA key data register 8
*/
#define ECDSA_KEY_8_REG (DR_REG_ECDSA_BASE + 0x60)
/** ECDSA_KEY_8 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_8 that is a part of key material.
*/
#define ECDSA_KEY_8 0xFFFFFFFFU
#define ECDSA_KEY_8_M (ECDSA_KEY_8_V << ECDSA_KEY_8_S)
#define ECDSA_KEY_8_V 0xFFFFFFFFU
#define ECDSA_KEY_8_S 0
/** ECDSA_KEY_9_REG register
* ECDSA key data register 9
*/
#define ECDSA_KEY_9_REG (DR_REG_ECDSA_BASE + 0x64)
/** ECDSA_KEY_9 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_9 that is a part of key material.
*/
#define ECDSA_KEY_9 0xFFFFFFFFU
#define ECDSA_KEY_9_M (ECDSA_KEY_9_V << ECDSA_KEY_9_S)
#define ECDSA_KEY_9_V 0xFFFFFFFFU
#define ECDSA_KEY_9_S 0
/** ECDSA_KEY_10_REG register
* ECDSA key data register 10
*/
#define ECDSA_KEY_10_REG (DR_REG_ECDSA_BASE + 0x68)
/** ECDSA_KEY_10 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_10 that is a part of key material.
*/
#define ECDSA_KEY_10 0xFFFFFFFFU
#define ECDSA_KEY_10_M (ECDSA_KEY_10_V << ECDSA_KEY_10_S)
#define ECDSA_KEY_10_V 0xFFFFFFFFU
#define ECDSA_KEY_10_S 0
/** ECDSA_KEY_11_REG register
* ECDSA key data register 11
*/
#define ECDSA_KEY_11_REG (DR_REG_ECDSA_BASE + 0x6c)
/** ECDSA_KEY_11 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_11 that is a part of key material.
*/
#define ECDSA_KEY_11 0xFFFFFFFFU
#define ECDSA_KEY_11_M (ECDSA_KEY_11_V << ECDSA_KEY_11_S)
#define ECDSA_KEY_11_V 0xFFFFFFFFU
#define ECDSA_KEY_11_S 0
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 38830480;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others:
* invalid.
*/
#define ECDSA_SHA_MODE 0x0000000FU
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x0000000FU
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
#define ECDSA_R_MEM_SIZE_BYTES 48
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
#define ECDSA_S_MEM_SIZE_BYTES 48
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
#define ECDSA_Z_MEM_SIZE_BYTES 48
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
#define ECDSA_QAX_MEM_SIZE_BYTES 48
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
#define ECDSA_QAY_MEM_SIZE_BYTES 48
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/ecdsa_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
* ECDSA configure register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [3:2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2.
*/
uint32_t ecc_curve:2;
/** software_set_k : R/W; bitpos: [4]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [5]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [6]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
uint32_t deterministic_k:1;
/** use_hardware_key : R/W; bitpos: [7]; default: 0;
* Configures the ECDSA use software key or hardware key.
* 0: Software key.
* 1: Hardware key.
*/
uint32_t use_hardware_key:1;
uint32_t reserved_8:24;
};
uint32_t val;
} ecdsa_conf_reg_t;
/** Type of start register
* ECDSA start register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t get_done:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_start_reg_t;
/** Type of timeout_limit register
* ECDSA timeout limit configure register
*/
typedef union {
struct {
/** timeout_limit : R/W; bitpos: [31:0]; default: 4294967295;
* The timeout limitation for waiting sub-IP.
*/
uint32_t timeout_limit:32;
};
uint32_t val;
} ecdsa_timeout_limit_reg_t;
/** Group: Clock and reset registers */
/** Type of clk register
* ECDSA clock gate register
*/
typedef union {
struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* ECDSA interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_raw_reg_t;
/** Type of int_st register
* ECDSA interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_st_reg_t;
/** Type of int_ena register
* ECDSA interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_ena_reg_t;
/** Type of int_clr register
* ECDSA interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_clr_reg_t;
/** Group: Status registers */
/** Type of state register
* ECDSA status register
*/
typedef union {
struct {
/** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
uint32_t busy:2;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_state_reg_t;
/** Group: Result registers */
/** Type of result register
* ECDSA result register
*/
typedef union {
struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
uint32_t operation_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_result_reg_t;
/** Group: Status Register */
/** Type of free register
* ECDSA free state
*/
typedef union {
struct {
/** free : R/W; bitpos: [0]; default: 1;
* Represents if ECDSA Accelerator is free or not.
* 0: non-free
* 1: free
*/
uint32_t free:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_free_reg_t;
/** Group: Key Registers */
/** Type of key_0 register
* ECDSA key data register 0
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} ecdsa_key_0_reg_t;
/** Type of key_1 register
* ECDSA key data register 1
*/
typedef union {
struct {
/** key_1 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_1 that is a part of key material.
*/
uint32_t key_1:32;
};
uint32_t val;
} ecdsa_key_1_reg_t;
/** Type of key_2 register
* ECDSA key data register 2
*/
typedef union {
struct {
/** key_2 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_2 that is a part of key material.
*/
uint32_t key_2:32;
};
uint32_t val;
} ecdsa_key_2_reg_t;
/** Type of key_3 register
* ECDSA key data register 3
*/
typedef union {
struct {
/** key_3 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_3 that is a part of key material.
*/
uint32_t key_3:32;
};
uint32_t val;
} ecdsa_key_3_reg_t;
/** Type of key_4 register
* ECDSA key data register 4
*/
typedef union {
struct {
/** key_4 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_4 that is a part of key material.
*/
uint32_t key_4:32;
};
uint32_t val;
} ecdsa_key_4_reg_t;
/** Type of key_5 register
* ECDSA key data register 5
*/
typedef union {
struct {
/** key_5 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_5 that is a part of key material.
*/
uint32_t key_5:32;
};
uint32_t val;
} ecdsa_key_5_reg_t;
/** Type of key_6 register
* ECDSA key data register 6
*/
typedef union {
struct {
/** key_6 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_6 that is a part of key material.
*/
uint32_t key_6:32;
};
uint32_t val;
} ecdsa_key_6_reg_t;
/** Type of key_7 register
* ECDSA key data register 7
*/
typedef union {
struct {
/** key_7 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_7 that is a part of key material.
*/
uint32_t key_7:32;
};
uint32_t val;
} ecdsa_key_7_reg_t;
/** Type of key_8 register
* ECDSA key data register 8
*/
typedef union {
struct {
/** key_8 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_8 that is a part of key material.
*/
uint32_t key_8:32;
};
uint32_t val;
} ecdsa_key_8_reg_t;
/** Type of key_9 register
* ECDSA key data register 9
*/
typedef union {
struct {
/** key_9 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_9 that is a part of key material.
*/
uint32_t key_9:32;
};
uint32_t val;
} ecdsa_key_9_reg_t;
/** Type of key_10 register
* ECDSA key data register 10
*/
typedef union {
struct {
/** key_10 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_10 that is a part of key material.
*/
uint32_t key_10:32;
};
uint32_t val;
} ecdsa_key_10_reg_t;
/** Type of key_11 register
* ECDSA key data register 11
*/
typedef union {
struct {
/** key_11 : R/W; bitpos: [31:0]; default: 0;
* These bits stores key_11 that is a part of key material.
*/
uint32_t key_11:32;
};
uint32_t val;
} ecdsa_key_11_reg_t;
/** Group: SHA register */
/** Type of sha_mode register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_mode : R/W; bitpos: [3:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others:
* invalid.
*/
uint32_t sha_mode:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_sha_mode_reg_t;
/** Type of sha_start register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_start_reg_t;
/** Type of sha_continue register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_continue_reg_t;
/** Type of sha_busy register
* ECDSA status register
*/
typedef union {
struct {
/** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
uint32_t sha_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_busy_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 38830480;
* ECDSA version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecdsa_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
volatile ecdsa_int_raw_reg_t int_raw;
volatile ecdsa_int_st_reg_t int_st;
volatile ecdsa_int_ena_reg_t int_ena;
volatile ecdsa_int_clr_reg_t int_clr;
volatile ecdsa_start_reg_t start;
volatile ecdsa_state_reg_t state;
volatile ecdsa_result_reg_t result;
volatile ecdsa_timeout_limit_reg_t timeout_limit;
volatile ecdsa_free_reg_t free;
uint32_t reserved_030[4];
volatile ecdsa_key_0_reg_t key_0;
volatile ecdsa_key_1_reg_t key_1;
volatile ecdsa_key_2_reg_t key_2;
volatile ecdsa_key_3_reg_t key_3;
volatile ecdsa_key_4_reg_t key_4;
volatile ecdsa_key_5_reg_t key_5;
volatile ecdsa_key_6_reg_t key_6;
volatile ecdsa_key_7_reg_t key_7;
volatile ecdsa_key_8_reg_t key_8;
volatile ecdsa_key_9_reg_t key_9;
volatile ecdsa_key_10_reg_t key_10;
volatile ecdsa_key_11_reg_t key_11;
uint32_t reserved_070[35];
volatile ecdsa_date_reg_t date;
uint32_t reserved_100[64];
volatile ecdsa_sha_mode_reg_t sha_mode;
uint32_t reserved_204[3];
volatile ecdsa_sha_start_reg_t sha_start;
volatile ecdsa_sha_continue_reg_t sha_continue;
volatile ecdsa_sha_busy_reg_t sha_busy;
uint32_t reserved_21c[25];
volatile uint32_t message[16];
uint32_t reserved_2c0[72];
volatile uint32_t r[12];
volatile uint32_t s[12];
volatile uint32_t z[12];
volatile uint32_t qax[12];
volatile uint32_t qay[12];
} ecdsa_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* HMAC start control register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable HMAC.
*
* 0: Disable HMAC
*
* 1: Enable HMAC
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* HMAC parameter configuration register
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Configures the HMAC purpose, refer to the Table . "
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* HMAC parameters configuration register
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Configures HMAC key. There are six keys with index 0~5. Write the index of the
* selected key to this field.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* HMAC configuration completion register
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Configures whether to finish HMAC configuration.
*
* 0: No effect
*
* 1: Finish configuration
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* HMAC message control register
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Calls SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* HMAC message continue register
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Configures whether or not there are unprocessed message blocks.
*
* 0: No unprocessed message block
*
* 1: There are still some message blocks to be processed.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* HMAC message end register
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Configures whether to start hardware padding.
*
* 0: No effect
*
* 1: Start hardware padding
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* HMAC result reading finish register
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* Configures whether to exit upstream mode and clear calculation results.
*
* 0: Not exit
*
* 1: Exit upstream mode and clear calculation results.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate JTAG result register
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results when re-enabling JTAG in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate digital signature result register
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results of the DS module in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Stores matching results between keys generated by users and corresponding purposes
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Represents whether or not an HMAC key matches the purpose.
*
* 0: Match
*
* 1: Error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy state of HMAC module
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
* make sure HMAC is in an IDLE state.
*
* 0: Idle
*
* 1: HMAC is still working on the calculation
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_TIMEOUT_LIMIT_REG register
* HMAC timeout limit configure register
*/
#define HMAC_TIMEOUT_LIMIT_REG (DR_REG_HMAC_BASE + 0x70)
/** HMAC_TIMEOUT_LIMIT : R/W; bitpos: [31:0]; default: 4294967295;
* The timeout limitation for waiting sub-IP.
*/
#define HMAC_TIMEOUT_LIMIT 0xFFFFFFFFU
#define HMAC_TIMEOUT_LIMIT_M (HMAC_TIMEOUT_LIMIT_V << HMAC_TIMEOUT_LIMIT_S)
#define HMAC_TIMEOUT_LIMIT_V 0xFFFFFFFFU
#define HMAC_TIMEOUT_LIMIT_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Software padding register
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Configures whether or not the padding is applied by software.
*
* 0: Not applied by software
*
* 1: Applied by software
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* One block message register
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Write 1 to indicate there is only one block which already contains padding bits and
* there is no need for padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable JTAG authentication mode.
*
* 0: Disable
*
* 1: Enable
*
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Re-enable JTAG register 1
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* Writes the comparing input used for re-enabling JTAG.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Version control register
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 539297817;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control/Status Registers */
/** Type of set_start register
* HMAC start control register
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable HMAC.
*
* 0: Disable HMAC
*
* 1: Enable HMAC
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_finish register
* HMAC configuration completion register
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Configures whether to finish HMAC configuration.
*
* 0: No effect
*
* 1: Finish configuration
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* HMAC message control register
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Calls SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* HMAC message continue register
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Configures whether or not there are unprocessed message blocks.
*
* 0: No unprocessed message block
*
* 1: There are still some message blocks to be processed.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* HMAC message end register
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Configures whether to start hardware padding.
*
* 0: No effect
*
* 1: Start hardware padding
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* HMAC result reading finish register
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* Configures whether to exit upstream mode and clear calculation results.
*
* 0: Not exit
*
* 1: Exit upstream mode and clear calculation results.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate JTAG result register
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results when re-enabling JTAG in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate digital signature result register
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results of the DS module in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of query_error register
* Stores matching results between keys generated by users and corresponding purposes
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Represents whether or not an HMAC key matches the purpose.
*
* 0: Match
*
* 1: Error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy state of HMAC module
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
* make sure HMAC is in an IDLE state.
*
* 0: Idle
*
* 1: HMAC is still working on the calculation
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Type of set_message_pad register
* Software padding register
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Configures whether or not the padding is applied by software.
*
* 0: Not applied by software
*
* 1: Applied by software
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* One block message register
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Write 1 to indicate there is only one block which already contains padding bits and
* there is no need for padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Group: Configuration Registers */
/** Type of set_para_purpose register
* HMAC parameter configuration register
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Configures the HMAC purpose, refer to the Table . "
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* HMAC parameters configuration register
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Configures HMAC key. There are six keys with index 0~5. Write the index of the
* selected key to this field.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of wr_jtag register
* Re-enable JTAG register 1
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* Writes the comparing input used for re-enabling JTAG.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Configuration registers */
/** Type of timeout_limit register
* HMAC timeout limit configure register
*/
typedef union {
struct {
/** timeout_limit : R/W; bitpos: [31:0]; default: 4294967295;
* The timeout limitation for waiting sub-IP.
*/
uint32_t timeout_limit:32;
};
uint32_t val;
} hmac_timeout_limit_reg_t;
/** Group: Memory Type */
/** Group: Configuration Register */
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable JTAG authentication mode.
*
* 0: Disable
*
* 1: Enable
*
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Group: Version Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 539297817;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
volatile hmac_timeout_limit_reg_t timeout_limit;
uint32_t reserved_074[3];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

839
components/soc/esp32s31/register/soc/hp_alive_sys_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HP_ALIVE_SYS_HP_CLK_CTRL_REG register
* HP Clock Control Register.
*/
#define HP_ALIVE_SYS_HP_CLK_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x0)
/** HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN : R/W; bitpos: [17]; default: 1;
* XTALx2 80M Clock Enable.
*/
#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN (BIT(17))
#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_M (HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_V << HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_S 17
/** HP_ALIVE_SYS_HP_ROOT_CLK_EN : R/W; bitpos: [18]; default: 1;
* HP SoC Root Clock Enable.
*/
#define HP_ALIVE_SYS_HP_ROOT_CLK_EN (BIT(18))
#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_M (HP_ALIVE_SYS_HP_ROOT_CLK_EN_V << HP_ALIVE_SYS_HP_ROOT_CLK_EN_S)
#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_S 18
/** HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN : R/W; bitpos: [19]; default: 1;
* XTAL 32K Clock Enable.
*/
#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN (BIT(19))
#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_M (HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_V << HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_S)
#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_S 19
/** HP_ALIVE_SYS_HP_RC_32K_CLK_EN : R/W; bitpos: [20]; default: 1;
* RC 32K Clock Enable.
*/
#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN (BIT(20))
#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_M (HP_ALIVE_SYS_HP_RC_32K_CLK_EN_V << HP_ALIVE_SYS_HP_RC_32K_CLK_EN_S)
#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_S 20
/** HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN : R/W; bitpos: [21]; default: 1;
* SOSC 150K Clock Enable.
*/
#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN (BIT(21))
#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_M (HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_V << HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_S 21
/** HP_ALIVE_SYS_HP_PLL_80M_CLK_EN : R/W; bitpos: [22]; default: 1;
* PLL 8M Clock Enable.
*/
#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN (BIT(22))
#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_M (HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_V << HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_S 22
/** HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [23]; default: 1;
* AUDIO PLL Clock Enable.
*/
#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN (BIT(23))
#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_M (HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_V << HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_S)
#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_S 23
/** HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [24]; default: 1;
* reserved
*/
#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN (BIT(24))
#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_M (HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_S 24
/** HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [25]; default: 1;
* reserved
*/
#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN (BIT(25))
#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_M (HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_S 25
/** HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [26]; default: 1;
* reserved
*/
#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN (BIT(26))
#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_M (HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_S 26
/** HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN : R/W; bitpos: [27]; default: 1;
* FOSC 20M Clock Enable.
*/
#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN (BIT(27))
#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_M (HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_V << HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_S 27
/** HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN : R/W; bitpos: [28]; default: 1;
* XTAL 40M Clock Enable.
*/
#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN (BIT(28))
#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_M (HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_V << HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_S 28
/** HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN : R/W; bitpos: [29]; default: 1;
* CPLL 300M Clock Enable.
*/
#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN (BIT(29))
#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_M (HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_V << HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_S 29
/** HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN : R/W; bitpos: [30]; default: 1;
* SPLL 480M Clock Enable.
*/
#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN (BIT(30))
#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_M (HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_V << HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_S 30
/** HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN : R/W; bitpos: [31]; default: 1;
* MPLL 500M Clock Enable.
*/
#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN (BIT(31))
#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_M (HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_V << HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_S)
#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_S 31
/** HP_ALIVE_SYS_HP_PAD_PARLIO_CTRL_REG register
* HP Clock Control Register.
*/
#define HP_ALIVE_SYS_HP_PAD_PARLIO_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x4)
/** HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [30]; default: 1;
* PARLIO TX Clock From Pad Enable.
*/
#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN (BIT(30))
#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_M (HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_S 30
/** HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [31]; default: 1;
* PARLIO RX Clock From Pad Enable.
*/
#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_M (HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_S 31
/** HP_ALIVE_SYS_HP_PAD_I2S0_CTRL_REG register
* HP Clock Control Register.
*/
#define HP_ALIVE_SYS_HP_PAD_I2S0_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x8)
/** HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [31]; default: 1;
* I2S0 MCLK Clock From Pad Enable.
*/
#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_M (HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_V << HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_S 31
/** HP_ALIVE_SYS_HP_PAD_I2S1_CTRL_REG register
* HP Clock Control Register.
*/
#define HP_ALIVE_SYS_HP_PAD_I2S1_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xc)
/** HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [31]; default: 1;
* I2S1 MCLK Clock From Pad Enable.
*/
#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_M (HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_V << HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_S 31
/** HP_ALIVE_SYS_HP_PAD_UART0_CTRL_REG register
* HP Clock Control Register.
*/
#define HP_ALIVE_SYS_HP_PAD_UART0_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x10)
/** HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
* UART0 SLP Clock From Pad Enable.
*/
#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_M (HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_S 31
/** HP_ALIVE_SYS_HP_PAD_UART1_CTRL_REG register
* HP Clock Control Register.
*/
#define HP_ALIVE_SYS_HP_PAD_UART1_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x14)
/** HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
* UART1 SLP Clock From Pad Enable.
*/
#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_M (HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_S 31
/** HP_ALIVE_SYS_HP_PAD_UART2_CTRL_REG register
* HP Clock Control Register.
*/
#define HP_ALIVE_SYS_HP_PAD_UART2_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x18)
/** HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
* UART2 SLP Clock From Pad Enable.
*/
#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_M (HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_S 31
/** HP_ALIVE_SYS_HP_PAD_UART3_CTRL_REG register
* HP Clock Control Register.
*/
#define HP_ALIVE_SYS_HP_PAD_UART3_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x1c)
/** HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
* UART3 SLP Clock From Pad Enable.
*/
#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN (BIT(31))
#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_M (HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_S)
#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_S 31
/** HP_ALIVE_SYS_MODEM_CLK_AON_REG register
* need_des
*/
#define HP_ALIVE_SYS_MODEM_CLK_AON_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x20)
/** HP_ALIVE_SYS_MODEM_CLK_AON_SEL : R/W; bitpos: [31]; default: 1;
* Modem clk aon sel. 0: foscl 1:xtal
*/
#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL (BIT(31))
#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_M (HP_ALIVE_SYS_MODEM_CLK_AON_SEL_V << HP_ALIVE_SYS_MODEM_CLK_AON_SEL_S)
#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_V 0x00000001U
#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_S 31
/** HP_ALIVE_SYS_USB_CTRL_REG register
* need_des
*/
#define HP_ALIVE_SYS_USB_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x24)
/** HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS : R/W; bitpos: [0]; default: 0;
* phy chrgvbus
*/
#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS (BIT(0))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_M (HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_V << HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_V 0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_S 0
/** HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS : R/W; bitpos: [1]; default: 0;
* phy dischrgvbus
*/
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS (BIT(1))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_M (HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_V 0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_S 1
/** HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN : R/W; bitpos: [2]; default: 0;
* phy dmpulldown
*/
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN (BIT(2))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_M (HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_V 0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_S 2
/** HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN : R/W; bitpos: [3]; default: 0;
* phy dppulldown
*/
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN (BIT(3))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_M (HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_V 0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_S 3
/** HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP : R/W; bitpos: [4]; default: 0;
* phy idpullup
*/
#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP (BIT(4))
#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_M (HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_V << HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_S)
#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_V 0x00000001U
#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_S 4
/** HP_ALIVE_SYS_HP_TCM_MEM_LP_CTRL_REG register
* configure rmemory power in lp system register
*/
#define HP_ALIVE_SYS_HP_TCM_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x28)
/** HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
* Configures layer0 hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE 0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_M (HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_V 0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_S 0
/** HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
* Set this bit to power down layer0 hp_sram memory.
*/
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN (BIT(2))
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_M (HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_S)
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_S 2
/** HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control layer0 hp_sram memory, disable hardware
* control.
*/
#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL (BIT(3))
#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_M (HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_V 0x00000001U
#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_S 3
/** HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 0;
* Configures layer1 hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE 0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_M (HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_V 0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_S 4
/** HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN : R/W; bitpos: [6]; default: 0;
* Set this bit to power down layer1 hp_sram memory.
*/
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN (BIT(6))
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_M (HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_S)
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_S 6
/** HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL : R/W; bitpos: [7]; default: 0;
* Set this bit to force software control layer1 hp_sram memory, disable hardware
* control.
*/
#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL (BIT(7))
#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_M (HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_V 0x00000001U
#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_S 7
/** HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE : R/W; bitpos: [9:8]; default: 0;
* Configures layer2 hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE 0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_M (HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_V 0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_S 8
/** HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN : R/W; bitpos: [10]; default: 0;
* Set this bit to power down layer2 hp_sram memory.
*/
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN (BIT(10))
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_M (HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_S)
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_S 10
/** HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL : R/W; bitpos: [11]; default: 0;
* Set this bit to force software control layer2 hp_sram memory, disable hardware
* control.
*/
#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL (BIT(11))
#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_M (HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_V 0x00000001U
#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_S 11
/** HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE : R/W; bitpos: [13:12]; default: 0;
* Configures layer3 hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE 0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_M (HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_V 0x00000003U
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_S 12
/** HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN : R/W; bitpos: [14]; default: 0;
* Set this bit to power down layer3 hp_sram memory.
*/
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN (BIT(14))
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_M (HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_S)
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_V 0x00000001U
#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_S 14
/** HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL : R/W; bitpos: [15]; default: 0;
* Set this bit to force software control layer3 hp_sram memory, disable hardware
* control.
*/
#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL (BIT(15))
#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_M (HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_V 0x00000001U
#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_S 15
/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_CTRL_REG register
* configure rmemory power in lp system register
*/
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x2c)
/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
* Configures flash_mmu memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE 0x00000003U
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_M (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_V 0x00000003U
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_S 0
/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
* Set this bit to power down flash_mmu memory.
*/
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN (BIT(2))
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_M (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_S)
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_V 0x00000001U
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_S 2
/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control flash_mmu memory, disable hardware control.
*/
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL (BIT(3))
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_M (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_V 0x00000001U
#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_S 3
/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_CTRL_REG register
* configure rmemory power in lp system register
*/
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x30)
/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
* Configures psram_mmu memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE 0x00000003U
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_M (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_S)
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_V 0x00000003U
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_S 0
/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
* Set this bit to power down psram_mmu memory.
*/
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN (BIT(2))
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_M (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_S)
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_V 0x00000001U
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_S 2
/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control psram_mmu memory, disable hardware control.
*/
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL (BIT(3))
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_M (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_S)
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_V 0x00000001U
#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_S 3
/** HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_REG register
* spram mem aux ctrl , control TOP/CNNT/MODEM power domain
*/
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x34)
/** HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* spram mem aux ctrl , control TOP/CNNT/MODEM power domain
*/
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_M (HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_S 0
/** HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_REG register
* sprf mem aux ctrl , control TOP/CNNT power domain
*/
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x38)
/** HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* sprf mem aux ctrl , control TOP/CNNT/MODEM power domain
*/
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_M (HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_S 0
/** HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_REG register
* need_des
*/
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x40)
/** HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
* sdprf mem aux ctrl , control TOP/CNNT/MODEM power domain
*/
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_M (HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_S 0
/** HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_REG register
* need_des
*/
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x44)
/** HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
* sprom mem aux ctrl , control CPU power domain
*/
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_M (HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_S 0
/** HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_REG register
* need_des
*/
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x48)
/** HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_M (HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_CONF_0_REG register
* intr hp2lp configuration register 0
*/
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_0_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x7c)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_0 : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_EN_0 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_M (HP_ALIVE_SYS_INTR_HP2LP_EN_0_V << HP_ALIVE_SYS_INTR_HP2LP_EN_0_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_CONF_1_REG register
* intr hp2lp configuration register 1
*/
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_1_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x80)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_1 : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_EN_1 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_M (HP_ALIVE_SYS_INTR_HP2LP_EN_1_V << HP_ALIVE_SYS_INTR_HP2LP_EN_1_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_CONF_2_REG register
* intr hp2lp configuration register 2
*/
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_2_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x84)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_2 : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_EN_2 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_M (HP_ALIVE_SYS_INTR_HP2LP_EN_2_V << HP_ALIVE_SYS_INTR_HP2LP_EN_2_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_CONF_3_REG register
* intr hp2lp configuration register 3
*/
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_3_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x88)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_3 : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_EN_3 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_M (HP_ALIVE_SYS_INTR_HP2LP_EN_3_V << HP_ALIVE_SYS_INTR_HP2LP_EN_3_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_CONF_4_REG register
* intr hp2lp configuration register 4
*/
#define HP_ALIVE_SYS_INTR_HP2LP_CONF_4_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x8c)
/** HP_ALIVE_SYS_INTR_HP2LP_EN_4 : R/W; bitpos: [7:0]; default: 255;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_EN_4 0x000000FFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_M (HP_ALIVE_SYS_INTR_HP2LP_EN_4_V << HP_ALIVE_SYS_INTR_HP2LP_EN_4_S)
#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_V 0x000000FFU
#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_REG register
* intr hp2lp status register 0
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x90)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_M (HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_REG register
* intr hp2lp status register 1
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x94)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_M (HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_REG register
* intr hp2lp status register 2
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x98)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_M (HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_REG register
* intr hp2lp status register 3
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x9c)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_3 : RO; bitpos: [31:0]; default: 0;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_M (HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_S 0
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_REG register
* intr hp2lp status register 4
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa0)
/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_4 : RO; bitpos: [7:0]; default: 0;
* reserved
*/
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4 0x000000FFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_M (HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_S)
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_V 0x000000FFU
#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_S 0
/** HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_REG register
* spram mem aux ctrl , control CPU power domain
*/
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa4)
/** HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* spram mem aux ctrl , control CPU power domain
*/
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_M (HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_S)
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_S 0
/** HP_ALIVE_SYS_BUS_CLOCK_GATE_BYPASS_REG register
* bus clock gating bypass configuration register
*/
#define HP_ALIVE_SYS_BUS_CLOCK_GATE_BYPASS_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa8)
/** HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS : R/W; bitpos: [0]; default: 1;
* Set 1 to bypass the clock gating for ahb bus
*/
#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS (BIT(0))
#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_M (HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_V 0x00000001U
#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_S 0
/** HP_ALIVE_SYS_APB_CLK_GATING_BYPASS : R/W; bitpos: [1]; default: 1;
* Set 1 to bypass the clock gating for apb bus
*/
#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS (BIT(1))
#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_M (HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_V 0x00000001U
#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_S 1
/** HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS : R/W; bitpos: [2]; default: 1;
* Set 1 to bypass the clock gating for axi bus
*/
#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS (BIT(2))
#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_M (HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_V 0x00000001U
#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_S 2
/** HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS : R/W; bitpos: [3]; default: 1;
* Set 1 to bypass the clock gating for mem bus
*/
#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS (BIT(3))
#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_M (HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_V 0x00000001U
#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_S 3
/** HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS : R/W; bitpos: [4]; default: 1;
* Set 1 to bypass the clock gating for ahb mtx
*/
#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS (BIT(4))
#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_M (HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_S)
#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_V 0x00000001U
#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_S 4
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_REG register
* bus clock gating bypass configuration register
*/
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xac)
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB : R/W; bitpos: [0]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB (BIT(0))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_M (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_V 0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_S 0
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS : R/W; bitpos: [1]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS (BIT(1))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_M (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_V 0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_S 1
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU : R/W; bitpos: [2]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU (BIT(2))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_M (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_V 0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_S 2
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST : R/W; bitpos: [3]; default: 1;
* Set 1 to bypass none-power_on reset source
*/
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST (BIT(3))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_M (HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_V 0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_S 3
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG : R/W; bitpos: [4]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG (BIT(4))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_M (HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_V 0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_S 4
/** HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX : R/W; bitpos: [5]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX (BIT(5))
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_M (HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_S)
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_V 0x00000001U
#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_S 5
/** HP_ALIVE_SYS_RST_BYPASS_LOCK : R/W; bitpos: [6]; default: 0;
* Set 1 to lock reset event bypass configuration
*/
#define HP_ALIVE_SYS_RST_BYPASS_LOCK (BIT(6))
#define HP_ALIVE_SYS_RST_BYPASS_LOCK_M (HP_ALIVE_SYS_RST_BYPASS_LOCK_V << HP_ALIVE_SYS_RST_BYPASS_LOCK_S)
#define HP_ALIVE_SYS_RST_BYPASS_LOCK_V 0x00000001U
#define HP_ALIVE_SYS_RST_BYPASS_LOCK_S 6
/** HP_ALIVE_SYS_USB_OTGHS_CTRL_REG register
* usb_otghs Control configuration register
*/
#define HP_ALIVE_SYS_USB_OTGHS_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xb0)
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force use reg_usb_otghs_phy_pll_en
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN (BIT(0))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_S 0
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN : R/W; bitpos: [1]; default: 0;
* pll_en for phy inf
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN (BIT(1))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_S 1
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN : R/W; bitpos: [2]; default: 1;
* Set this bit as 1 to force use reg_usb_otghs_phy_suspendm
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN (BIT(2))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_S 2
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM : R/W; bitpos: [3]; default: 0;
* phy suspendm
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM (BIT(3))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_S 3
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN : R/W; bitpos: [4]; default: 0;
* Set this bit as 1 to force use reg_usb_otghs_phy_reset
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN (BIT(4))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_S 4
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET : R/W; bitpos: [5]; default: 0;
* phy reset
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET (BIT(5))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_S 5
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN : R/W; bitpos: [6]; default: 0;
* phy txbitstuff_en
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN (BIT(6))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_S 6
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM : R/W; bitpos: [7]; default: 0;
* phy otg_suspendm
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM (BIT(7))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_S 7
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE : R/W; bitpos: [8]; default: 1;
* phy refclk_mode
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE (BIT(8))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_S 8
/** HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE : R/W; bitpos: [10:9]; default: 0;
* usb otghs core ss_scaledown_mode
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE 0x00000003U
#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_M (HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_V << HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_V 0x00000003U
#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_S 9
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST : R/W; bitpos: [11]; default: 0;
* phy self_test
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST (BIT(11))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_S 11
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE : RO; bitpos: [12]; default: 0;
* phy test_bist
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE (BIT(12))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_S 12
/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO : RO; bitpos: [13]; default: 0;
* phy dto
*/
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO (BIT(13))
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_M (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_S)
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_V 0x00000001U
#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_S 13
/** HP_ALIVE_SYS_DATE_REG register
* need_des
*/
#define HP_ALIVE_SYS_DATE_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x3fc)
/** HP_ALIVE_SYS_DATE : R/W; bitpos: [30:0]; default: 38834448;
* need_des
*/
#define HP_ALIVE_SYS_DATE 0x7FFFFFFFU
#define HP_ALIVE_SYS_DATE_M (HP_ALIVE_SYS_DATE_V << HP_ALIVE_SYS_DATE_S)
#define HP_ALIVE_SYS_DATE_V 0x7FFFFFFFU
#define HP_ALIVE_SYS_DATE_S 0
/** HP_ALIVE_SYS_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define HP_ALIVE_SYS_CLK_EN (BIT(31))
#define HP_ALIVE_SYS_CLK_EN_M (HP_ALIVE_SYS_CLK_EN_V << HP_ALIVE_SYS_CLK_EN_S)
#define HP_ALIVE_SYS_CLK_EN_V 0x00000001U
#define HP_ALIVE_SYS_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/hp_alive_sys_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of hp_clk_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:17;
/** hp_xtalx2_80m_clk_en : R/W; bitpos: [17]; default: 1;
* XTALx2 80M Clock Enable.
*/
uint32_t hp_xtalx2_80m_clk_en:1;
/** hp_root_clk_en : R/W; bitpos: [18]; default: 1;
* HP SoC Root Clock Enable.
*/
uint32_t hp_root_clk_en:1;
/** hp_xtal_32k_clk_en : R/W; bitpos: [19]; default: 1;
* XTAL 32K Clock Enable.
*/
uint32_t hp_xtal_32k_clk_en:1;
/** hp_rc_32k_clk_en : R/W; bitpos: [20]; default: 1;
* RC 32K Clock Enable.
*/
uint32_t hp_rc_32k_clk_en:1;
/** hp_sosc_150k_clk_en : R/W; bitpos: [21]; default: 1;
* SOSC 150K Clock Enable.
*/
uint32_t hp_sosc_150k_clk_en:1;
/** hp_pll_80m_clk_en : R/W; bitpos: [22]; default: 1;
* PLL 8M Clock Enable.
*/
uint32_t hp_pll_80m_clk_en:1;
/** hp_audio_pll_clk_en : R/W; bitpos: [23]; default: 1;
* AUDIO PLL Clock Enable.
*/
uint32_t hp_audio_pll_clk_en:1;
/** hp_sdio_pll2_clk_en : R/W; bitpos: [24]; default: 1;
* reserved
*/
uint32_t hp_sdio_pll2_clk_en:1;
/** hp_sdio_pll1_clk_en : R/W; bitpos: [25]; default: 1;
* reserved
*/
uint32_t hp_sdio_pll1_clk_en:1;
/** hp_sdio_pll0_clk_en : R/W; bitpos: [26]; default: 1;
* reserved
*/
uint32_t hp_sdio_pll0_clk_en:1;
/** hp_fosc_20m_clk_en : R/W; bitpos: [27]; default: 1;
* FOSC 20M Clock Enable.
*/
uint32_t hp_fosc_20m_clk_en:1;
/** hp_xtal_40m_clk_en : R/W; bitpos: [28]; default: 1;
* XTAL 40M Clock Enable.
*/
uint32_t hp_xtal_40m_clk_en:1;
/** hp_cpll_300m_clk_en : R/W; bitpos: [29]; default: 1;
* CPLL 300M Clock Enable.
*/
uint32_t hp_cpll_300m_clk_en:1;
/** hp_spll_480m_clk_en : R/W; bitpos: [30]; default: 1;
* SPLL 480M Clock Enable.
*/
uint32_t hp_spll_480m_clk_en:1;
/** hp_mpll_500m_clk_en : R/W; bitpos: [31]; default: 1;
* MPLL 500M Clock Enable.
*/
uint32_t hp_mpll_500m_clk_en:1;
};
uint32_t val;
} hp_alive_sys_hp_clk_ctrl_reg_t;
/** Type of hp_pad_parlio_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** hp_pad_parlio_tx_clk_en : R/W; bitpos: [30]; default: 1;
* PARLIO TX Clock From Pad Enable.
*/
uint32_t hp_pad_parlio_tx_clk_en:1;
/** hp_pad_parlio_rx_clk_en : R/W; bitpos: [31]; default: 1;
* PARLIO RX Clock From Pad Enable.
*/
uint32_t hp_pad_parlio_rx_clk_en:1;
};
uint32_t val;
} hp_alive_sys_hp_pad_parlio_ctrl_reg_t;
/** Type of hp_pad_i2s0_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** hp_pad_i2s0_mclk_en : R/W; bitpos: [31]; default: 1;
* I2S0 MCLK Clock From Pad Enable.
*/
uint32_t hp_pad_i2s0_mclk_en:1;
};
uint32_t val;
} hp_alive_sys_hp_pad_i2s0_ctrl_reg_t;
/** Type of hp_pad_i2s1_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** hp_pad_i2s1_mclk_en : R/W; bitpos: [31]; default: 1;
* I2S1 MCLK Clock From Pad Enable.
*/
uint32_t hp_pad_i2s1_mclk_en:1;
};
uint32_t val;
} hp_alive_sys_hp_pad_i2s1_ctrl_reg_t;
/** Type of hp_pad_uart0_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** hp_pad_uart0_slp_clk_en : R/W; bitpos: [31]; default: 1;
* UART0 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart0_slp_clk_en:1;
};
uint32_t val;
} hp_alive_sys_hp_pad_uart0_ctrl_reg_t;
/** Type of hp_pad_uart1_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** hp_pad_uart1_slp_clk_en : R/W; bitpos: [31]; default: 1;
* UART1 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart1_slp_clk_en:1;
};
uint32_t val;
} hp_alive_sys_hp_pad_uart1_ctrl_reg_t;
/** Type of hp_pad_uart2_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** hp_pad_uart2_slp_clk_en : R/W; bitpos: [31]; default: 1;
* UART2 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart2_slp_clk_en:1;
};
uint32_t val;
} hp_alive_sys_hp_pad_uart2_ctrl_reg_t;
/** Type of hp_pad_uart3_ctrl register
* HP Clock Control Register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** hp_pad_uart3_slp_clk_en : R/W; bitpos: [31]; default: 1;
* UART3 SLP Clock From Pad Enable.
*/
uint32_t hp_pad_uart3_slp_clk_en:1;
};
uint32_t val;
} hp_alive_sys_hp_pad_uart3_ctrl_reg_t;
/** Type of modem_clk_aon register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** modem_clk_aon_sel : R/W; bitpos: [31]; default: 1;
* Modem clk aon sel. 0: foscl 1:xtal
*/
uint32_t modem_clk_aon_sel:1;
};
uint32_t val;
} hp_alive_sys_modem_clk_aon_reg_t;
/** Type of usb_ctrl register
* need_des
*/
typedef union {
struct {
/** usb_otghs_phy_chrgvbus : R/W; bitpos: [0]; default: 0;
* phy chrgvbus
*/
uint32_t usb_otghs_phy_chrgvbus:1;
/** usb_otghs_phy_dischrgvbus : R/W; bitpos: [1]; default: 0;
* phy dischrgvbus
*/
uint32_t usb_otghs_phy_dischrgvbus:1;
/** usb_otghs_phy_dmpulldown : R/W; bitpos: [2]; default: 0;
* phy dmpulldown
*/
uint32_t usb_otghs_phy_dmpulldown:1;
/** usb_otghs_phy_dppulldown : R/W; bitpos: [3]; default: 0;
* phy dppulldown
*/
uint32_t usb_otghs_phy_dppulldown:1;
/** usb_otghs_phy_idpullup : R/W; bitpos: [4]; default: 0;
* phy idpullup
*/
uint32_t usb_otghs_phy_idpullup:1;
uint32_t reserved_5:27;
};
uint32_t val;
} hp_alive_sys_usb_ctrl_reg_t;
/** Type of hp_tcm_mem_lp_ctrl register
* configure rmemory power in lp system register
*/
typedef union {
struct {
/** hp_tcm_l0_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
* Configures layer0 hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
uint32_t hp_tcm_l0_mem_lp_mode:2;
/** hp_tcm_l0_mem_lp_en : R/W; bitpos: [2]; default: 0;
* Set this bit to power down layer0 hp_sram memory.
*/
uint32_t hp_tcm_l0_mem_lp_en:1;
/** hp_tcm_mem_l0_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control layer0 hp_sram memory, disable hardware
* control.
*/
uint32_t hp_tcm_mem_l0_lp_force_ctrl:1;
/** hp_tcm_l1_mem_lp_mode : R/W; bitpos: [5:4]; default: 0;
* Configures layer1 hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
uint32_t hp_tcm_l1_mem_lp_mode:2;
/** hp_tcm_l1_mem_lp_en : R/W; bitpos: [6]; default: 0;
* Set this bit to power down layer1 hp_sram memory.
*/
uint32_t hp_tcm_l1_mem_lp_en:1;
/** hp_tcm_mem_l1_lp_force_ctrl : R/W; bitpos: [7]; default: 0;
* Set this bit to force software control layer1 hp_sram memory, disable hardware
* control.
*/
uint32_t hp_tcm_mem_l1_lp_force_ctrl:1;
/** hp_tcm_l2_mem_lp_mode : R/W; bitpos: [9:8]; default: 0;
* Configures layer2 hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
uint32_t hp_tcm_l2_mem_lp_mode:2;
/** hp_tcm_l2_mem_lp_en : R/W; bitpos: [10]; default: 0;
* Set this bit to power down layer2 hp_sram memory.
*/
uint32_t hp_tcm_l2_mem_lp_en:1;
/** hp_tcm_mem_l2_lp_force_ctrl : R/W; bitpos: [11]; default: 0;
* Set this bit to force software control layer2 hp_sram memory, disable hardware
* control.
*/
uint32_t hp_tcm_mem_l2_lp_force_ctrl:1;
/** hp_tcm_l3_mem_lp_mode : R/W; bitpos: [13:12]; default: 0;
* Configures layer3 hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
uint32_t hp_tcm_l3_mem_lp_mode:2;
/** hp_tcm_l3_mem_lp_en : R/W; bitpos: [14]; default: 0;
* Set this bit to power down layer3 hp_sram memory.
*/
uint32_t hp_tcm_l3_mem_lp_en:1;
/** hp_tcm_mem_l3_lp_force_ctrl : R/W; bitpos: [15]; default: 0;
* Set this bit to force software control layer3 hp_sram memory, disable hardware
* control.
*/
uint32_t hp_tcm_mem_l3_lp_force_ctrl:1;
uint32_t reserved_16:16;
};
uint32_t val;
} hp_alive_sys_hp_tcm_mem_lp_ctrl_reg_t;
/** Type of flash_mmu_mem_lp_ctrl register
* configure rmemory power in lp system register
*/
typedef union {
struct {
/** flash_mmu_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
* Configures flash_mmu memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
uint32_t flash_mmu_mem_lp_mode:2;
/** flash_mmu_mem_lp_en : R/W; bitpos: [2]; default: 0;
* Set this bit to power down flash_mmu memory.
*/
uint32_t flash_mmu_mem_lp_en:1;
/** flash_mmu_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control flash_mmu memory, disable hardware control.
*/
uint32_t flash_mmu_mem_lp_force_ctrl:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_alive_sys_flash_mmu_mem_lp_ctrl_reg_t;
/** Type of psram_mmu_mem_lp_ctrl register
* configure rmemory power in lp system register
*/
typedef union {
struct {
/** psram_mmu_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
* Configures psram_mmu memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
uint32_t psram_mmu_mem_lp_mode:2;
/** psram_mmu_mem_lp_en : R/W; bitpos: [2]; default: 0;
* Set this bit to power down psram_mmu memory.
*/
uint32_t psram_mmu_mem_lp_en:1;
/** psram_mmu_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control psram_mmu memory, disable hardware control.
*/
uint32_t psram_mmu_mem_lp_force_ctrl:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_alive_sys_psram_mmu_mem_lp_ctrl_reg_t;
/** Type of spram_mem_aux_ctrl register
* spram mem aux ctrl , control TOP/CNNT/MODEM power domain
*/
typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* spram mem aux ctrl , control TOP/CNNT/MODEM power domain
*/
uint32_t spram_mem_aux_ctrl:32;
};
uint32_t val;
} hp_alive_sys_spram_mem_aux_ctrl_reg_t;
/** Type of sprf_mem_aux_ctrl register
* sprf mem aux ctrl , control TOP/CNNT power domain
*/
typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* sprf mem aux ctrl , control TOP/CNNT/MODEM power domain
*/
uint32_t sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_alive_sys_sprf_mem_aux_ctrl_reg_t;
/** Type of sdprf_mem_aux_ctrl register
* need_des
*/
typedef union {
struct {
/** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
* sdprf mem aux ctrl , control TOP/CNNT/MODEM power domain
*/
uint32_t sdprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_alive_sys_sdprf_mem_aux_ctrl_reg_t;
/** Type of cpu_sprom_mem_aux_ctrl register
* need_des
*/
typedef union {
struct {
/** cpu_sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
* sprom mem aux ctrl , control CPU power domain
*/
uint32_t cpu_sprom_mem_aux_ctrl:32;
};
uint32_t val;
} hp_alive_sys_cpu_sprom_mem_aux_ctrl_reg_t;
/** Type of cpu_sprf_mem_aux_ctrl register
* need_des
*/
typedef union {
struct {
/** cpu_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
uint32_t cpu_sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_alive_sys_cpu_sprf_mem_aux_ctrl_reg_t;
/** Type of cpu_spram_mem_aux_ctrl register
* spram mem aux ctrl , control CPU power domain
*/
typedef union {
struct {
/** cpu_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* spram mem aux ctrl , control CPU power domain
*/
uint32_t cpu_spram_mem_aux_ctrl:32;
};
uint32_t val;
} hp_alive_sys_cpu_spram_mem_aux_ctrl_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 38834448;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} hp_alive_sys_date_reg_t;
/** Group: Configuration Register */
/** Type of intr_hp2lp_conf_0 register
* intr hp2lp configuration register 0
*/
typedef union {
struct {
/** intr_hp2lp_en_0 : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
uint32_t intr_hp2lp_en_0:32;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_conf_0_reg_t;
/** Type of intr_hp2lp_conf_1 register
* intr hp2lp configuration register 1
*/
typedef union {
struct {
/** intr_hp2lp_en_1 : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
uint32_t intr_hp2lp_en_1:32;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_conf_1_reg_t;
/** Type of intr_hp2lp_conf_2 register
* intr hp2lp configuration register 2
*/
typedef union {
struct {
/** intr_hp2lp_en_2 : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
uint32_t intr_hp2lp_en_2:32;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_conf_2_reg_t;
/** Type of intr_hp2lp_conf_3 register
* intr hp2lp configuration register 3
*/
typedef union {
struct {
/** intr_hp2lp_en_3 : R/W; bitpos: [31:0]; default: 4294967295;
* reserved
*/
uint32_t intr_hp2lp_en_3:32;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_conf_3_reg_t;
/** Type of intr_hp2lp_conf_4 register
* intr hp2lp configuration register 4
*/
typedef union {
struct {
/** intr_hp2lp_en_4 : R/W; bitpos: [7:0]; default: 255;
* reserved
*/
uint32_t intr_hp2lp_en_4:8;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_conf_4_reg_t;
/** Type of bus_clock_gate_bypass register
* bus clock gating bypass configuration register
*/
typedef union {
struct {
/** ahb_clk_gating_bypass : R/W; bitpos: [0]; default: 1;
* Set 1 to bypass the clock gating for ahb bus
*/
uint32_t ahb_clk_gating_bypass:1;
/** apb_clk_gating_bypass : R/W; bitpos: [1]; default: 1;
* Set 1 to bypass the clock gating for apb bus
*/
uint32_t apb_clk_gating_bypass:1;
/** axi_clk_gating_bypass : R/W; bitpos: [2]; default: 1;
* Set 1 to bypass the clock gating for axi bus
*/
uint32_t axi_clk_gating_bypass:1;
/** mem_clk_gating_bypass : R/W; bitpos: [3]; default: 1;
* Set 1 to bypass the clock gating for mem bus
*/
uint32_t mem_clk_gating_bypass:1;
/** ahb_mtx_clk_gating_bypass : R/W; bitpos: [4]; default: 1;
* Set 1 to bypass the clock gating for ahb mtx
*/
uint32_t ahb_mtx_clk_gating_bypass:1;
uint32_t reserved_5:27;
};
uint32_t val;
} hp_alive_sys_bus_clock_gate_bypass_reg_t;
/** Type of rst_event_bypass register
* bus clock gating bypass configuration register
*/
typedef union {
struct {
/** rst_event_bypass_icmapb : R/W; bitpos: [0]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
uint32_t rst_event_bypass_icmapb:1;
/** rst_event_bypass_icmsys : R/W; bitpos: [1]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
uint32_t rst_event_bypass_icmsys:1;
/** rst_event_bypass_icmcpu : R/W; bitpos: [2]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
uint32_t rst_event_bypass_icmcpu:1;
/** rst_event_bypass_clkrst : R/W; bitpos: [3]; default: 1;
* Set 1 to bypass none-power_on reset source
*/
uint32_t rst_event_bypass_clkrst:1;
/** rst_event_bypass_clkrst_reg : R/W; bitpos: [4]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
uint32_t rst_event_bypass_clkrst_reg:1;
/** rst_event_bypass_iomux : R/W; bitpos: [5]; default: 0;
* Set 1 to bypass none-power_on reset source
*/
uint32_t rst_event_bypass_iomux:1;
/** rst_bypass_lock : R/W; bitpos: [6]; default: 0;
* Set 1 to lock reset event bypass configuration
*/
uint32_t rst_bypass_lock:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_alive_sys_rst_event_bypass_reg_t;
/** Type of usb_otghs_ctrl register
* usb_otghs Control configuration register
*/
typedef union {
struct {
/** reg_usb_otghs_phy_pll_force_en : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force use reg_usb_otghs_phy_pll_en
*/
uint32_t reg_usb_otghs_phy_pll_force_en:1;
/** reg_usb_otghs_phy_pll_en : R/W; bitpos: [1]; default: 0;
* pll_en for phy inf
*/
uint32_t reg_usb_otghs_phy_pll_en:1;
/** reg_usb_otghs_phy_suspendm_force_en : R/W; bitpos: [2]; default: 1;
* Set this bit as 1 to force use reg_usb_otghs_phy_suspendm
*/
uint32_t reg_usb_otghs_phy_suspendm_force_en:1;
/** reg_usb_otghs_phy_suspendm : R/W; bitpos: [3]; default: 0;
* phy suspendm
*/
uint32_t reg_usb_otghs_phy_suspendm:1;
/** reg_usb_otghs_phy_reset_force_en : R/W; bitpos: [4]; default: 0;
* Set this bit as 1 to force use reg_usb_otghs_phy_reset
*/
uint32_t reg_usb_otghs_phy_reset_force_en:1;
/** reg_usb_otghs_phy_reset : R/W; bitpos: [5]; default: 0;
* phy reset
*/
uint32_t reg_usb_otghs_phy_reset:1;
/** reg_usb_otghs_phy_txbitstuff_en : R/W; bitpos: [6]; default: 0;
* phy txbitstuff_en
*/
uint32_t reg_usb_otghs_phy_txbitstuff_en:1;
/** reg_usb_otghs_phy_otg_suspendm : R/W; bitpos: [7]; default: 0;
* phy otg_suspendm
*/
uint32_t reg_usb_otghs_phy_otg_suspendm:1;
/** reg_usb_otghs_phy_refclk_mode : R/W; bitpos: [8]; default: 1;
* phy refclk_mode
*/
uint32_t reg_usb_otghs_phy_refclk_mode:1;
/** reg_usb_otghs_core_ss_scaledown_mode : R/W; bitpos: [10:9]; default: 0;
* usb otghs core ss_scaledown_mode
*/
uint32_t reg_usb_otghs_core_ss_scaledown_mode:2;
/** reg_usb_otghs_phy_self_test : R/W; bitpos: [11]; default: 0;
* phy self_test
*/
uint32_t reg_usb_otghs_phy_self_test:1;
/** reg_usb_otghs_phy_test_done : RO; bitpos: [12]; default: 0;
* phy test_bist
*/
uint32_t reg_usb_otghs_phy_test_done:1;
/** reg_usb_otghs_phy_dto : RO; bitpos: [13]; default: 0;
* phy dto
*/
uint32_t reg_usb_otghs_phy_dto:1;
uint32_t reserved_14:18;
};
uint32_t val;
} hp_alive_sys_usb_otghs_ctrl_reg_t;
/** Group: Status Register */
/** Type of intr_hp2lp_status_0 register
* intr hp2lp status register 0
*/
typedef union {
struct {
/** intr_hp2lp_status_0 : RO; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t intr_hp2lp_status_0:32;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_status_0_reg_t;
/** Type of intr_hp2lp_status_1 register
* intr hp2lp status register 1
*/
typedef union {
struct {
/** intr_hp2lp_status_1 : RO; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t intr_hp2lp_status_1:32;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_status_1_reg_t;
/** Type of intr_hp2lp_status_2 register
* intr hp2lp status register 2
*/
typedef union {
struct {
/** intr_hp2lp_status_2 : RO; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t intr_hp2lp_status_2:32;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_status_2_reg_t;
/** Type of intr_hp2lp_status_3 register
* intr hp2lp status register 3
*/
typedef union {
struct {
/** intr_hp2lp_status_3 : RO; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t intr_hp2lp_status_3:32;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_status_3_reg_t;
/** Type of intr_hp2lp_status_4 register
* intr hp2lp status register 4
*/
typedef union {
struct {
/** intr_hp2lp_status_4 : RO; bitpos: [7:0]; default: 0;
* reserved
*/
uint32_t intr_hp2lp_status_4:8;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_alive_sys_intr_hp2lp_status_4_reg_t;
typedef struct {
volatile hp_alive_sys_hp_clk_ctrl_reg_t hp_clk_ctrl;
volatile hp_alive_sys_hp_pad_parlio_ctrl_reg_t hp_pad_parlio_ctrl;
volatile hp_alive_sys_hp_pad_i2s0_ctrl_reg_t hp_pad_i2s0_ctrl;
volatile hp_alive_sys_hp_pad_i2s1_ctrl_reg_t hp_pad_i2s1_ctrl;
volatile hp_alive_sys_hp_pad_uart0_ctrl_reg_t hp_pad_uart0_ctrl;
volatile hp_alive_sys_hp_pad_uart1_ctrl_reg_t hp_pad_uart1_ctrl;
volatile hp_alive_sys_hp_pad_uart2_ctrl_reg_t hp_pad_uart2_ctrl;
volatile hp_alive_sys_hp_pad_uart3_ctrl_reg_t hp_pad_uart3_ctrl;
volatile hp_alive_sys_modem_clk_aon_reg_t modem_clk_aon;
volatile hp_alive_sys_usb_ctrl_reg_t usb_ctrl;
volatile hp_alive_sys_hp_tcm_mem_lp_ctrl_reg_t hp_tcm_mem_lp_ctrl;
volatile hp_alive_sys_flash_mmu_mem_lp_ctrl_reg_t flash_mmu_mem_lp_ctrl;
volatile hp_alive_sys_psram_mmu_mem_lp_ctrl_reg_t psram_mmu_mem_lp_ctrl;
volatile hp_alive_sys_spram_mem_aux_ctrl_reg_t spram_mem_aux_ctrl;
volatile hp_alive_sys_sprf_mem_aux_ctrl_reg_t sprf_mem_aux_ctrl;
uint32_t reserved_03c;
volatile hp_alive_sys_sdprf_mem_aux_ctrl_reg_t sdprf_mem_aux_ctrl;
volatile hp_alive_sys_cpu_sprom_mem_aux_ctrl_reg_t cpu_sprom_mem_aux_ctrl;
volatile hp_alive_sys_cpu_sprf_mem_aux_ctrl_reg_t cpu_sprf_mem_aux_ctrl;
uint32_t reserved_04c[12];
volatile hp_alive_sys_intr_hp2lp_conf_0_reg_t intr_hp2lp_conf_0;
volatile hp_alive_sys_intr_hp2lp_conf_1_reg_t intr_hp2lp_conf_1;
volatile hp_alive_sys_intr_hp2lp_conf_2_reg_t intr_hp2lp_conf_2;
volatile hp_alive_sys_intr_hp2lp_conf_3_reg_t intr_hp2lp_conf_3;
volatile hp_alive_sys_intr_hp2lp_conf_4_reg_t intr_hp2lp_conf_4;
volatile hp_alive_sys_intr_hp2lp_status_0_reg_t intr_hp2lp_status_0;
volatile hp_alive_sys_intr_hp2lp_status_1_reg_t intr_hp2lp_status_1;
volatile hp_alive_sys_intr_hp2lp_status_2_reg_t intr_hp2lp_status_2;
volatile hp_alive_sys_intr_hp2lp_status_3_reg_t intr_hp2lp_status_3;
volatile hp_alive_sys_intr_hp2lp_status_4_reg_t intr_hp2lp_status_4;
volatile hp_alive_sys_cpu_spram_mem_aux_ctrl_reg_t cpu_spram_mem_aux_ctrl;
volatile hp_alive_sys_bus_clock_gate_bypass_reg_t bus_clock_gate_bypass;
volatile hp_alive_sys_rst_event_bypass_reg_t rst_event_bypass;
volatile hp_alive_sys_usb_otghs_ctrl_reg_t usb_otghs_ctrl;
uint32_t reserved_0b4[210];
volatile hp_alive_sys_date_reg_t date;
} hp_alive_sys_dev_t;
extern hp_alive_sys_dev_t HP_ALIVE_SYS;
#ifndef __cplusplus
_Static_assert(sizeof(hp_alive_sys_dev_t) == 0x400, "Invalid size of hp_alive_sys_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [15:0]; default: 1;
* Configure bit $n (0-15) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t region_filter_en:16;
uint32_t reserved_16:16;
};
uint32_t val;
} hp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region n.
*/
uint32_t regionn_addr_start:32;
};
uint32_t val;
} hp_apm_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region n.
*/
uint32_t regionn_addr_end:32;
};
uint32_t val;
} hp_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
uint32_t reserved_11:1;
/** regionn_tee_x : R/W; bitpos: [12]; default: 1;
* Configures the execution authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_x:1;
/** regionn_tee_w : R/W; bitpos: [13]; default: 1;
* Configures the write authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_w:1;
/** regionn_tee_r : R/W; bitpos: [14]; default: 1;
* Configures the read authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_r:1;
uint32_t reserved_15:1;
/** regionn_lock : R/W; bitpos: [16]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hp_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_func_en:1;
/** m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
*/
uint32_t m2_func_en:1;
/** m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
*/
uint32_t m3_func_en:1;
/** m4_func_en : R/W; bitpos: [4]; default: 1;
* PMS M4 function enable
*/
uint32_t m4_func_en:1;
/** m5_func_en : R/W; bitpos: [5]; default: 1;
* PMS M5 function enable
*/
uint32_t m5_func_en:1;
/** m6_func_en : R/W; bitpos: [6]; default: 1;
* PMS M6 function enable
*/
uint32_t m6_func_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:16;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [23:18]; default: 0;
* Represents exception id information.
*/
uint32_t m0_exception_id:6;
uint32_t reserved_24:8;
};
uint32_t val;
} hp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} hp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:16;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [23:18]; default: 0;
* Represents exception id information.
*/
uint32_t m1_exception_id:6;
uint32_t reserved_24:8;
};
uint32_t val;
} hp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} hp_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of m2_status register
* M2 status register
*/
typedef union {
struct {
/** m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m2_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of m2_status_clr register
* M2 status clear register
*/
typedef union {
struct {
/** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m2_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of m2_exception_info0 register
* M2 exception_info0 register
*/
typedef union {
struct {
/** m2_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m2_exception_region:16;
/** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m2_exception_mode:2;
/** m2_exception_id : RO; bitpos: [23:18]; default: 0;
* Represents exception id information.
*/
uint32_t m2_exception_id:6;
uint32_t reserved_24:8;
};
uint32_t val;
} hp_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of m2_exception_info1 register
* M2 exception_info1 register
*/
typedef union {
struct {
/** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m2_exception_addr:32;
};
uint32_t val;
} hp_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of m3_status register
* M3 status register
*/
typedef union {
struct {
/** m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m3_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of m3_status_clr register
* M3 status clear register
*/
typedef union {
struct {
/** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m3_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of m3_exception_info0 register
* M3 exception_info0 register
*/
typedef union {
struct {
/** m3_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m3_exception_region:16;
/** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m3_exception_mode:2;
/** m3_exception_id : RO; bitpos: [23:18]; default: 0;
* Represents exception id information.
*/
uint32_t m3_exception_id:6;
uint32_t reserved_24:8;
};
uint32_t val;
} hp_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of m3_exception_info1 register
* M3 exception_info1 register
*/
typedef union {
struct {
/** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m3_exception_addr:32;
};
uint32_t val;
} hp_apm_m3_exception_info1_reg_t;
/** Group: M4 status register */
/** Type of m4_status register
* M4 status register
*/
typedef union {
struct {
/** m4_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m4_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m4_status_reg_t;
/** Group: M4 status clear register */
/** Type of m4_status_clr register
* M4 status clear register
*/
typedef union {
struct {
/** m4_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m4_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m4_status_clr_reg_t;
/** Group: M4 exception_info0 register */
/** Type of m4_exception_info0 register
* M4 exception_info0 register
*/
typedef union {
struct {
/** m4_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m4_exception_region:16;
/** m4_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m4_exception_mode:2;
/** m4_exception_id : RO; bitpos: [23:18]; default: 0;
* Represents exception id information.
*/
uint32_t m4_exception_id:6;
uint32_t reserved_24:8;
};
uint32_t val;
} hp_apm_m4_exception_info0_reg_t;
/** Group: M4 exception_info1 register */
/** Type of m4_exception_info1 register
* M4 exception_info1 register
*/
typedef union {
struct {
/** m4_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m4_exception_addr:32;
};
uint32_t val;
} hp_apm_m4_exception_info1_reg_t;
/** Group: M5 status register */
/** Type of m5_status register
* M5 status register
*/
typedef union {
struct {
/** m5_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m5_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m5_status_reg_t;
/** Group: M5 status clear register */
/** Type of m5_status_clr register
* M5 status clear register
*/
typedef union {
struct {
/** m5_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m5_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m5_status_clr_reg_t;
/** Group: M5 exception_info0 register */
/** Type of m5_exception_info0 register
* M5 exception_info0 register
*/
typedef union {
struct {
/** m5_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m5_exception_region:16;
/** m5_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m5_exception_mode:2;
/** m5_exception_id : RO; bitpos: [24:18]; default: 0;
* Represents exception id information.
*/
uint32_t m5_exception_id:7;
uint32_t reserved_25:7;
};
uint32_t val;
} hp_apm_m5_exception_info0_reg_t;
/** Group: M5 exception_info1 register */
/** Type of m5_exception_info1 register
* M5 exception_info1 register
*/
typedef union {
struct {
/** m5_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m5_exception_addr:32;
};
uint32_t val;
} hp_apm_m5_exception_info1_reg_t;
/** Group: M6 status register */
/** Type of m6_status register
* M6 status register
*/
typedef union {
struct {
/** m6_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m6_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m6_status_reg_t;
/** Group: M6 status clear register */
/** Type of m6_status_clr register
* M6 status clear register
*/
typedef union {
struct {
/** m6_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m6_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m6_status_clr_reg_t;
/** Group: M6 exception_info0 register */
/** Type of m6_exception_info0 register
* M6 exception_info0 register
*/
typedef union {
struct {
/** m6_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m6_exception_region:16;
/** m6_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m6_exception_mode:2;
/** m6_exception_id : RO; bitpos: [24:18]; default: 0;
* Represents exception id information.
*/
uint32_t m6_exception_id:7;
uint32_t reserved_25:7;
};
uint32_t val;
} hp_apm_m6_exception_info0_reg_t;
/** Group: M6 exception_info1 register */
/** Type of m6_exception_info1 register
* M6 exception_info1 register
*/
typedef union {
struct {
/** m6_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m6_exception_addr:32;
};
uint32_t val;
} hp_apm_m6_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m1_apm_int_en:1;
/** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m2_apm_int_en:1;
/** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m3_apm_int_en:1;
/** m4_apm_int_en : R/W; bitpos: [4]; default: 0;
* Configures to enable APM M4 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m4_apm_int_en:1;
/** m5_apm_int_en : R/W; bitpos: [5]; default: 0;
* Configures to enable APM M5 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m5_apm_int_en:1;
/** m6_apm_int_en : R/W; bitpos: [6]; default: 0;
* Configures to enable APM M6 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m6_apm_int_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_apm_int_en_reg_t;
/** Type of bus_err_conf register
* APM interrupt enable register
*/
typedef union {
struct {
/** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
* Configures whether return error response to cpu when access blocked
* 0: disable error response
* 1: enable error response
*/
uint32_t bus_err_resp_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_bus_err_conf_reg_t;
/** Group: APM transmission config register */
/** Type of axi_block_en register
* M6 status clear register
*/
typedef union {
struct {
/** axi_block_en : R/W; bitpos: [0]; default: 1;
* Configures to if block transmission when get exceltion.
* 0: transparent transmission to slave
* 1: don't transparent transmission to slave
*/
uint32_t axi_block_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_axi_block_en_reg_t;
/** Group: Clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 38822496;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_apm_date_reg_t;
typedef struct {
volatile hp_apm_region_filter_en_reg_t region_filter_en;
volatile hp_apm_regionn_addr_start_reg_t region0_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region0_addr_end;
volatile hp_apm_regionn_attr_reg_t region0_attr;
volatile hp_apm_regionn_addr_start_reg_t region1_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region1_addr_end;
volatile hp_apm_regionn_attr_reg_t region1_attr;
volatile hp_apm_regionn_addr_start_reg_t region2_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region2_addr_end;
volatile hp_apm_regionn_attr_reg_t region2_attr;
volatile hp_apm_regionn_addr_start_reg_t region3_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region3_addr_end;
volatile hp_apm_regionn_attr_reg_t region3_attr;
volatile hp_apm_regionn_addr_start_reg_t region4_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region4_addr_end;
volatile hp_apm_regionn_attr_reg_t region4_attr;
volatile hp_apm_regionn_addr_start_reg_t region5_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region5_addr_end;
volatile hp_apm_regionn_attr_reg_t region5_attr;
volatile hp_apm_regionn_addr_start_reg_t region6_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region6_addr_end;
volatile hp_apm_regionn_attr_reg_t region6_attr;
volatile hp_apm_regionn_addr_start_reg_t region7_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region7_addr_end;
volatile hp_apm_regionn_attr_reg_t region7_attr;
volatile hp_apm_regionn_addr_start_reg_t region8_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region8_addr_end;
volatile hp_apm_regionn_attr_reg_t region8_attr;
volatile hp_apm_regionn_addr_start_reg_t region9_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region9_addr_end;
volatile hp_apm_regionn_attr_reg_t region9_attr;
volatile hp_apm_regionn_addr_start_reg_t region10_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region10_addr_end;
volatile hp_apm_regionn_attr_reg_t region10_attr;
volatile hp_apm_regionn_addr_start_reg_t region11_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region11_addr_end;
volatile hp_apm_regionn_attr_reg_t region11_attr;
volatile hp_apm_regionn_addr_start_reg_t region12_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region12_addr_end;
volatile hp_apm_regionn_attr_reg_t region12_attr;
volatile hp_apm_regionn_addr_start_reg_t region13_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region13_addr_end;
volatile hp_apm_regionn_attr_reg_t region13_attr;
volatile hp_apm_regionn_addr_start_reg_t region14_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region14_addr_end;
volatile hp_apm_regionn_attr_reg_t region14_attr;
volatile hp_apm_regionn_addr_start_reg_t region15_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region15_addr_end;
volatile hp_apm_regionn_attr_reg_t region15_attr;
volatile hp_apm_func_ctrl_reg_t func_ctrl;
volatile hp_apm_m0_status_reg_t m0_status;
volatile hp_apm_m0_status_clr_reg_t m0_status_clr;
volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile hp_apm_m1_status_reg_t m1_status;
volatile hp_apm_m1_status_clr_reg_t m1_status_clr;
volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile hp_apm_m2_status_reg_t m2_status;
volatile hp_apm_m2_status_clr_reg_t m2_status_clr;
volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0;
volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1;
volatile hp_apm_m3_status_reg_t m3_status;
volatile hp_apm_m3_status_clr_reg_t m3_status_clr;
volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0;
volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1;
volatile hp_apm_m4_status_reg_t m4_status;
volatile hp_apm_m4_status_clr_reg_t m4_status_clr;
volatile hp_apm_m4_exception_info0_reg_t m4_exception_info0;
volatile hp_apm_m4_exception_info1_reg_t m4_exception_info1;
volatile hp_apm_m5_status_reg_t m5_status;
volatile hp_apm_m5_status_clr_reg_t m5_status_clr;
volatile hp_apm_m5_exception_info0_reg_t m5_exception_info0;
volatile hp_apm_m5_exception_info1_reg_t m5_exception_info1;
uint32_t reserved_128;
volatile hp_apm_m6_status_reg_t m6_status;
volatile hp_apm_m6_status_clr_reg_t m6_status_clr;
volatile hp_apm_m6_exception_info0_reg_t m6_exception_info0;
volatile hp_apm_m6_exception_info1_reg_t m6_exception_info1;
uint32_t reserved_13c[4];
volatile hp_apm_int_en_reg_t int_en;
volatile hp_apm_axi_block_en_reg_t axi_block_en;
volatile hp_apm_bus_err_conf_reg_t bus_err_conf;
uint32_t reserved_158[168];
volatile hp_apm_clock_gate_reg_t clock_gate;
volatile hp_apm_date_reg_t date;
} hp_apm_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(hp_apm_dev_t) == 0x400, "Invalid size of hp_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_mem_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start_l : HRO; bitpos: [6:0]; default: 0;
* Low 12 bit, start address of region n.
*/
uint32_t regionn_addr_start_l:7;
/** regionn_addr_start : R/W; bitpos: [18:7]; default: 0;
* Configures start address of region n.
*/
uint32_t regionn_addr_start:12;
/** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 1504;
* High 13 bit, start address of region n.
*/
uint32_t regionn_addr_start_h:13;
};
uint32_t val;
} hp_mem_apm_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end_l : HRO; bitpos: [6:0]; default: 127;
* Low 12 bit, end address of region n.
*/
uint32_t regionn_addr_end_l:7;
/** regionn_addr_end : R/W; bitpos: [18:7]; default: 4095;
* Configures end address of region n.
*/
uint32_t regionn_addr_end:12;
/** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 1504;
* High 13 bit, end address of region n.
*/
uint32_t regionn_addr_end_h:13;
};
uint32_t val;
} hp_mem_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
uint32_t reserved_11:1;
/** regionn_tee_x : R/W; bitpos: [12]; default: 1;
* Configures the execution authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_x:1;
/** regionn_tee_w : R/W; bitpos: [13]; default: 1;
* Configures the write authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_w:1;
/** regionn_tee_r : R/W; bitpos: [14]; default: 1;
* Configures the read authority of TEE_MODE in region n.
*/
uint32_t regionn_tee_r:1;
uint32_t reserved_15:1;
/** regionn_lock : R/W; bitpos: [16]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hp_mem_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_func_en:1;
/** m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
*/
uint32_t m2_func_en:1;
/** m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
*/
uint32_t m3_func_en:1;
/** m4_func_en : R/W; bitpos: [4]; default: 1;
* PMS M4 function enable
*/
uint32_t m4_func_en:1;
/** m5_func_en : R/W; bitpos: [5]; default: 1;
* PMS M5 function enable
*/
uint32_t m5_func_en:1;
uint32_t reserved_6:26;
};
uint32_t val;
} hp_mem_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:8;
uint32_t reserved_8:8;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_mem_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:8;
uint32_t reserved_8:8;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_mem_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of m2_status register
* M2 status register
*/
typedef union {
struct {
/** m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m2_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of m2_status_clr register
* M2 status clear register
*/
typedef union {
struct {
/** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m2_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of m2_exception_info0 register
* M2 exception_info0 register
*/
typedef union {
struct {
/** m2_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m2_exception_region:8;
uint32_t reserved_8:8;
/** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m2_exception_mode:2;
/** m2_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m2_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_mem_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of m2_exception_info1 register
* M2 exception_info1 register
*/
typedef union {
struct {
/** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m2_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of m3_status register
* M3 status register
*/
typedef union {
struct {
/** m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m3_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of m3_status_clr register
* M3 status clear register
*/
typedef union {
struct {
/** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m3_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of m3_exception_info0 register
* M3 exception_info0 register
*/
typedef union {
struct {
/** m3_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m3_exception_region:8;
uint32_t reserved_8:8;
/** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m3_exception_mode:2;
/** m3_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m3_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_mem_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of m3_exception_info1 register
* M3 exception_info1 register
*/
typedef union {
struct {
/** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m3_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m3_exception_info1_reg_t;
/** Group: M4 status register */
/** Type of m4_status register
* M4 status register
*/
typedef union {
struct {
/** m4_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m4_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m4_status_reg_t;
/** Group: M4 status clear register */
/** Type of m4_status_clr register
* M4 status clear register
*/
typedef union {
struct {
/** m4_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m4_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m4_status_clr_reg_t;
/** Group: M4 exception_info0 register */
/** Type of m4_exception_info0 register
* M4 exception_info0 register
*/
typedef union {
struct {
/** m4_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m4_exception_region:8;
uint32_t reserved_8:8;
/** m4_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m4_exception_mode:2;
/** m4_exception_id : RO; bitpos: [24:18]; default: 0;
* Represents exception id information.
*/
uint32_t m4_exception_id:7;
uint32_t reserved_25:7;
};
uint32_t val;
} hp_mem_apm_m4_exception_info0_reg_t;
/** Group: M4 exception_info1 register */
/** Type of m4_exception_info1 register
* M4 exception_info1 register
*/
typedef union {
struct {
/** m4_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m4_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m4_exception_info1_reg_t;
/** Group: M5 status register */
/** Type of m5_status register
* M5 status register
*/
typedef union {
struct {
/** m5_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m5_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m5_status_reg_t;
/** Group: M5 status clear register */
/** Type of m5_status_clr register
* M5 status clear register
*/
typedef union {
struct {
/** m5_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m5_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m5_status_clr_reg_t;
/** Group: M5 exception_info0 register */
/** Type of m5_exception_info0 register
* M5 exception_info0 register
*/
typedef union {
struct {
/** m5_exception_region : RO; bitpos: [7:0]; default: 0;
* Represents exception region.
*/
uint32_t m5_exception_region:8;
uint32_t reserved_8:8;
/** m5_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m5_exception_mode:2;
/** m5_exception_id : RO; bitpos: [23:18]; default: 0;
* Represents exception id information.
*/
uint32_t m5_exception_id:6;
uint32_t reserved_24:8;
};
uint32_t val;
} hp_mem_apm_m5_exception_info0_reg_t;
/** Group: M5 exception_info1 register */
/** Type of m5_exception_info1 register
* M5 exception_info1 register
*/
typedef union {
struct {
/** m5_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m5_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m5_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m1_apm_int_en:1;
/** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m2_apm_int_en:1;
/** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m3_apm_int_en:1;
/** m4_apm_int_en : R/W; bitpos: [4]; default: 0;
* Configures to enable APM M4 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m4_apm_int_en:1;
/** m5_apm_int_en : R/W; bitpos: [5]; default: 0;
* Configures to enable APM M5 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m5_apm_int_en:1;
uint32_t reserved_6:26;
};
uint32_t val;
} hp_mem_apm_int_en_reg_t;
/** Type of bus_err_conf register
* APM interrupt enable register
*/
typedef union {
struct {
/** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
* Configures whether return error response to cpu when access blocked
* 0: disable error response
* 1: enable error response
*/
uint32_t bus_err_resp_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_bus_err_conf_reg_t;
/** Group: Clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 38822496;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_mem_apm_date_reg_t;
typedef struct {
volatile hp_mem_apm_region_filter_en_reg_t region_filter_en;
volatile hp_mem_apm_regionn_addr_start_reg_t region0_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region0_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region0_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region1_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region1_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region1_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region2_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region2_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region2_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region3_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region3_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region3_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region4_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region4_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region4_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region5_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region5_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region5_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region6_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region6_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region6_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region7_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region7_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region7_attr;
uint32_t reserved_064[24];
volatile hp_mem_apm_func_ctrl_reg_t func_ctrl;
volatile hp_mem_apm_m0_status_reg_t m0_status;
volatile hp_mem_apm_m0_status_clr_reg_t m0_status_clr;
volatile hp_mem_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile hp_mem_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile hp_mem_apm_m1_status_reg_t m1_status;
volatile hp_mem_apm_m1_status_clr_reg_t m1_status_clr;
volatile hp_mem_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile hp_mem_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile hp_mem_apm_m2_status_reg_t m2_status;
volatile hp_mem_apm_m2_status_clr_reg_t m2_status_clr;
volatile hp_mem_apm_m2_exception_info0_reg_t m2_exception_info0;
volatile hp_mem_apm_m2_exception_info1_reg_t m2_exception_info1;
volatile hp_mem_apm_m3_status_reg_t m3_status;
volatile hp_mem_apm_m3_status_clr_reg_t m3_status_clr;
volatile hp_mem_apm_m3_exception_info0_reg_t m3_exception_info0;
volatile hp_mem_apm_m3_exception_info1_reg_t m3_exception_info1;
volatile hp_mem_apm_m4_status_reg_t m4_status;
volatile hp_mem_apm_m4_status_clr_reg_t m4_status_clr;
volatile hp_mem_apm_m4_exception_info0_reg_t m4_exception_info0;
volatile hp_mem_apm_m4_exception_info1_reg_t m4_exception_info1;
volatile hp_mem_apm_m5_status_reg_t m5_status;
volatile hp_mem_apm_m5_status_clr_reg_t m5_status_clr;
volatile hp_mem_apm_m5_exception_info0_reg_t m5_exception_info0;
volatile hp_mem_apm_m5_exception_info1_reg_t m5_exception_info1;
volatile hp_mem_apm_int_en_reg_t int_en;
volatile hp_mem_apm_bus_err_conf_reg_t bus_err_conf;
uint32_t reserved_130[178];
volatile hp_mem_apm_clock_gate_reg_t clock_gate;
volatile hp_mem_apm_date_reg_t date;
} hp_mem_apm_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(hp_mem_apm_dev_t) == 0x400, "Invalid size of hp_mem_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
* HUK Generator clock gate control register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_V 0x00000001U
#define HUK_CLK_EN_S 0
/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define HUK_MEM_CG_FORCE_ON (BIT(1))
#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
#define HUK_MEM_CG_FORCE_ON_V 0x00000001U
#define HUK_MEM_CG_FORCE_ON_S 1
/** HUK_INT_RAW_REG register
* HUK Generator interrupt raw register, valid in level.
*/
#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_RAW (BIT(0))
#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
#define HUK_PREP_DONE_INT_RAW_V 0x00000001U
#define HUK_PREP_DONE_INT_RAW_S 0
/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_RAW (BIT(1))
#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
#define HUK_PROC_DONE_INT_RAW_V 0x00000001U
#define HUK_PROC_DONE_INT_RAW_S 1
/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_RAW (BIT(2))
#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
#define HUK_POST_DONE_INT_RAW_V 0x00000001U
#define HUK_POST_DONE_INT_RAW_S 2
/** HUK_INT_ST_REG register
* HUK Generator interrupt status register.
*/
#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ST (BIT(0))
#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
#define HUK_PREP_DONE_INT_ST_V 0x00000001U
#define HUK_PREP_DONE_INT_ST_S 0
/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ST (BIT(1))
#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
#define HUK_PROC_DONE_INT_ST_V 0x00000001U
#define HUK_PROC_DONE_INT_ST_S 1
/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ST (BIT(2))
#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
#define HUK_POST_DONE_INT_ST_V 0x00000001U
#define HUK_POST_DONE_INT_ST_S 2
/** HUK_INT_ENA_REG register
* HUK Generator interrupt enable register.
*/
#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ENA (BIT(0))
#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
#define HUK_PREP_DONE_INT_ENA_V 0x00000001U
#define HUK_PREP_DONE_INT_ENA_S 0
/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ENA (BIT(1))
#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
#define HUK_PROC_DONE_INT_ENA_V 0x00000001U
#define HUK_PROC_DONE_INT_ENA_S 1
/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ENA (BIT(2))
#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
#define HUK_POST_DONE_INT_ENA_V 0x00000001U
#define HUK_POST_DONE_INT_ENA_S 2
/** HUK_INT_CLR_REG register
* HUK Generator interrupt clear register.
*/
#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_CLR (BIT(0))
#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
#define HUK_PREP_DONE_INT_CLR_V 0x00000001U
#define HUK_PREP_DONE_INT_CLR_S 0
/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_CLR (BIT(1))
#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
#define HUK_PROC_DONE_INT_CLR_V 0x00000001U
#define HUK_PROC_DONE_INT_CLR_S 1
/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_CLR (BIT(2))
#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
#define HUK_POST_DONE_INT_CLR_V 0x00000001U
#define HUK_POST_DONE_INT_CLR_S 2
/** HUK_CONF_REG register
* HUK Generator configuration register
*/
#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
/** HUK_MODE : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
#define HUK_MODE (BIT(0))
#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S)
#define HUK_MODE_V 0x00000001U
#define HUK_MODE_S 0
/** HUK_START_REG register
* HUK Generator control register
*/
#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
/** HUK_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
#define HUK_START (BIT(0))
#define HUK_START_M (HUK_START_V << HUK_START_S)
#define HUK_START_V 0x00000001U
#define HUK_START_S 0
/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
#define HUK_CONTINUE (BIT(1))
#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S)
#define HUK_CONTINUE_V 0x00000001U
#define HUK_CONTINUE_S 1
/** HUK_STATE_REG register
* HUK Generator state register
*/
#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define HUK_STATE 0x00000003U
#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S)
#define HUK_STATE_V 0x00000003U
#define HUK_STATE_S 0
/** HUK_STATUS_REG register
* HUK Generator HUK status register
*/
#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
#define HUK_STATUS 0x00000003U
#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S)
#define HUK_STATUS_V 0x00000003U
#define HUK_STATUS_S 0
/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
#define HUK_RISK_LEVEL 0x00000007U
#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
#define HUK_RISK_LEVEL_V 0x00000007U
#define HUK_RISK_LEVEL_S 2
/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0;
* The update request of HUK info. 0: User can update HUK info according to the risk
* level. 1: The HUK info is expired, and user need to update it.
*/
#define HUK_UPDATE_REQ (BIT(5))
#define HUK_UPDATE_REQ_M (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S)
#define HUK_UPDATE_REQ_V 0x00000001U
#define HUK_UPDATE_REQ_S 5
/** HUK_DATE_REG register
* Version control register
*/
#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232;
* HUK Generator version control register.
*/
#define HUK_DATE 0x0FFFFFFFU
#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S)
#define HUK_DATE_V 0x0FFFFFFFU
#define HUK_DATE_S 0
/** HUK_INFO_MEM register
* The memory that stores HUK info.
*/
#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
#define HUK_INFO_MEM_SIZE_BYTES 384
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* HUK Generator clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* HUK Generator interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_raw_reg_t;
/** Type of int_st register
* HUK Generator interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_st_reg_t;
/** Type of int_ena register
* HUK Generator interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_ena_reg_t;
/** Type of int_clr register
* HUK Generator interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_clr_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* HUK Generator configuration register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
uint32_t mode:1;
uint32_t reserved_1:31;
};
uint32_t val;
} huk_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* HUK Generator control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
uint32_t continue:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_start_reg_t;
/** Group: State registers */
/** Type of state register
* HUK Generator state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_state_reg_t;
/** Group: Result registers */
/** Type of status register
* HUK Generator HUK status register
*/
typedef union {
struct {
/** status : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
uint32_t status:2;
/** risk_level : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
uint32_t risk_level:3;
/** update_req : RO; bitpos: [5]; default: 0;
* The update request of HUK info. 0: User can update HUK info according to the risk
* level. 1: The HUK info is expired, and user need to update it.
*/
uint32_t update_req:1;
uint32_t reserved_6:26;
};
uint32_t val;
} huk_status_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37765232;
* HUK Generator version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} huk_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile huk_clk_reg_t clk;
volatile huk_int_raw_reg_t int_raw;
volatile huk_int_st_reg_t int_st;
volatile huk_int_ena_reg_t int_ena;
volatile huk_int_clr_reg_t int_clr;
uint32_t reserved_018[2];
volatile huk_conf_reg_t conf;
volatile huk_start_reg_t start;
volatile huk_state_reg_t state;
uint32_t reserved_02c[2];
volatile huk_status_reg_t status;
uint32_t reserved_038[49];
volatile huk_date_reg_t date;
volatile uint32_t info[96];
} huk_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ICM_VER_DATE_REG register
* NA
*/
#define ICM_VER_DATE_REG (DR_REG_ICM_BASE + 0x0)
/** ICM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539296517;
* NA
*/
#define ICM_REG_VER_DATE 0xFFFFFFFFU
#define ICM_REG_VER_DATE_M (ICM_REG_VER_DATE_V << ICM_REG_VER_DATE_S)
#define ICM_REG_VER_DATE_V 0xFFFFFFFFU
#define ICM_REG_VER_DATE_S 0
/** ICM_CLK_EN_REG register
* NA
*/
#define ICM_CLK_EN_REG (DR_REG_ICM_BASE + 0x4)
/** ICM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_CLK_EN (BIT(0))
#define ICM_REG_CLK_EN_M (ICM_REG_CLK_EN_V << ICM_REG_CLK_EN_S)
#define ICM_REG_CLK_EN_V 0x00000001U
#define ICM_REG_CLK_EN_S 0
/** ICM_MST_ARQOS_REG0_REG register
* NA
*/
#define ICM_MST_ARQOS_REG0_REG (DR_REG_ICM_BASE + 0x28)
/** ICM_REG_CPU_ARQOS : R/W; bitpos: [3:0]; default: 0;
* NA
*/
#define ICM_REG_CPU_ARQOS 0x0000000FU
#define ICM_REG_CPU_ARQOS_M (ICM_REG_CPU_ARQOS_V << ICM_REG_CPU_ARQOS_S)
#define ICM_REG_CPU_ARQOS_V 0x0000000FU
#define ICM_REG_CPU_ARQOS_S 0
/** ICM_REG_CACHE_ARQOS : R/W; bitpos: [7:4]; default: 0;
* NA
*/
#define ICM_REG_CACHE_ARQOS 0x0000000FU
#define ICM_REG_CACHE_ARQOS_M (ICM_REG_CACHE_ARQOS_V << ICM_REG_CACHE_ARQOS_S)
#define ICM_REG_CACHE_ARQOS_V 0x0000000FU
#define ICM_REG_CACHE_ARQOS_S 4
/** ICM_REG_DMA2D_ARQOS : R/W; bitpos: [11:8]; default: 0;
* NA
*/
#define ICM_REG_DMA2D_ARQOS 0x0000000FU
#define ICM_REG_DMA2D_ARQOS_M (ICM_REG_DMA2D_ARQOS_V << ICM_REG_DMA2D_ARQOS_S)
#define ICM_REG_DMA2D_ARQOS_V 0x0000000FU
#define ICM_REG_DMA2D_ARQOS_S 8
/** ICM_REG_AXI_PDMA_INT_ARQOS : R/W; bitpos: [15:12]; default: 0;
* NA
*/
#define ICM_REG_AXI_PDMA_INT_ARQOS 0x0000000FU
#define ICM_REG_AXI_PDMA_INT_ARQOS_M (ICM_REG_AXI_PDMA_INT_ARQOS_V << ICM_REG_AXI_PDMA_INT_ARQOS_S)
#define ICM_REG_AXI_PDMA_INT_ARQOS_V 0x0000000FU
#define ICM_REG_AXI_PDMA_INT_ARQOS_S 12
/** ICM_REG_GMAC_ARQOS : R/W; bitpos: [19:16]; default: 0;
* NA
*/
#define ICM_REG_GMAC_ARQOS 0x0000000FU
#define ICM_REG_GMAC_ARQOS_M (ICM_REG_GMAC_ARQOS_V << ICM_REG_GMAC_ARQOS_S)
#define ICM_REG_GMAC_ARQOS_V 0x0000000FU
#define ICM_REG_GMAC_ARQOS_S 16
/** ICM_REG_AXI_SDMMC_INT_ARQOS : R/W; bitpos: [23:20]; default: 0;
* NA
*/
#define ICM_REG_AXI_SDMMC_INT_ARQOS 0x0000000FU
#define ICM_REG_AXI_SDMMC_INT_ARQOS_M (ICM_REG_AXI_SDMMC_INT_ARQOS_V << ICM_REG_AXI_SDMMC_INT_ARQOS_S)
#define ICM_REG_AXI_SDMMC_INT_ARQOS_V 0x0000000FU
#define ICM_REG_AXI_SDMMC_INT_ARQOS_S 20
/** ICM_MST_AWQOS_REG0_REG register
* NA
*/
#define ICM_MST_AWQOS_REG0_REG (DR_REG_ICM_BASE + 0x30)
/** ICM_REG_CPU_AWQOS : R/W; bitpos: [3:0]; default: 0;
* NA
*/
#define ICM_REG_CPU_AWQOS 0x0000000FU
#define ICM_REG_CPU_AWQOS_M (ICM_REG_CPU_AWQOS_V << ICM_REG_CPU_AWQOS_S)
#define ICM_REG_CPU_AWQOS_V 0x0000000FU
#define ICM_REG_CPU_AWQOS_S 0
/** ICM_REG_CACHE_AWQOS : R/W; bitpos: [7:4]; default: 0;
* NA
*/
#define ICM_REG_CACHE_AWQOS 0x0000000FU
#define ICM_REG_CACHE_AWQOS_M (ICM_REG_CACHE_AWQOS_V << ICM_REG_CACHE_AWQOS_S)
#define ICM_REG_CACHE_AWQOS_V 0x0000000FU
#define ICM_REG_CACHE_AWQOS_S 4
/** ICM_REG_DMA2D_AWQOS : R/W; bitpos: [11:8]; default: 0;
* NA
*/
#define ICM_REG_DMA2D_AWQOS 0x0000000FU
#define ICM_REG_DMA2D_AWQOS_M (ICM_REG_DMA2D_AWQOS_V << ICM_REG_DMA2D_AWQOS_S)
#define ICM_REG_DMA2D_AWQOS_V 0x0000000FU
#define ICM_REG_DMA2D_AWQOS_S 8
/** ICM_REG_PDMA_INT_AWQOS : R/W; bitpos: [15:12]; default: 0;
* NA
*/
#define ICM_REG_PDMA_INT_AWQOS 0x0000000FU
#define ICM_REG_PDMA_INT_AWQOS_M (ICM_REG_PDMA_INT_AWQOS_V << ICM_REG_PDMA_INT_AWQOS_S)
#define ICM_REG_PDMA_INT_AWQOS_V 0x0000000FU
#define ICM_REG_PDMA_INT_AWQOS_S 12
/** ICM_REG_GMAC_AWQOS : R/W; bitpos: [19:16]; default: 0;
* NA
*/
#define ICM_REG_GMAC_AWQOS 0x0000000FU
#define ICM_REG_GMAC_AWQOS_M (ICM_REG_GMAC_AWQOS_V << ICM_REG_GMAC_AWQOS_S)
#define ICM_REG_GMAC_AWQOS_V 0x0000000FU
#define ICM_REG_GMAC_AWQOS_S 16
/** ICM_REG_AXI_SDMMC_INT_AWQOS : R/W; bitpos: [23:20]; default: 0;
* NA
*/
#define ICM_REG_AXI_SDMMC_INT_AWQOS 0x0000000FU
#define ICM_REG_AXI_SDMMC_INT_AWQOS_M (ICM_REG_AXI_SDMMC_INT_AWQOS_V << ICM_REG_AXI_SDMMC_INT_AWQOS_S)
#define ICM_REG_AXI_SDMMC_INT_AWQOS_V 0x0000000FU
#define ICM_REG_AXI_SDMMC_INT_AWQOS_S 20
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: ICM VER DATE REG */
/** Type of ver_date register
* NA
*/
typedef union {
struct {
/** reg_ver_date : R/W; bitpos: [31:0]; default: 539296517;
* NA
*/
uint32_t reg_ver_date:32;
};
uint32_t val;
} icm_ver_date_reg_t;
/** Group: ICM CLK EN REG */
/** Type of clk_en register
* NA
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} icm_clk_en_reg_t;
/** Group: ICM MST ARQOS REG0 REG */
/** Type of mst_arqos_reg0 register
* NA
*/
typedef union {
struct {
/** reg_cpu_arqos : R/W; bitpos: [3:0]; default: 0;
* NA
*/
uint32_t reg_cpu_arqos:4;
/** reg_cache_arqos : R/W; bitpos: [7:4]; default: 0;
* NA
*/
uint32_t reg_cache_arqos:4;
/** reg_dma2d_arqos : R/W; bitpos: [11:8]; default: 0;
* NA
*/
uint32_t reg_dma2d_arqos:4;
/** reg_axi_pdma_int_arqos : R/W; bitpos: [15:12]; default: 0;
* NA
*/
uint32_t reg_axi_pdma_int_arqos:4;
/** reg_gmac_arqos : R/W; bitpos: [19:16]; default: 0;
* NA
*/
uint32_t reg_gmac_arqos:4;
/** reg_axi_sdmmc_int_arqos : R/W; bitpos: [23:20]; default: 0;
* NA
*/
uint32_t reg_axi_sdmmc_int_arqos:4;
uint32_t reserved_24:8;
};
uint32_t val;
} icm_mst_arqos_reg0_reg_t;
/** Group: ICM MST AWQOS REG0 REG */
/** Type of mst_awqos_reg0 register
* NA
*/
typedef union {
struct {
/** reg_cpu_awqos : R/W; bitpos: [3:0]; default: 0;
* NA
*/
uint32_t reg_cpu_awqos:4;
/** reg_cache_awqos : R/W; bitpos: [7:4]; default: 0;
* NA
*/
uint32_t reg_cache_awqos:4;
/** reg_dma2d_awqos : R/W; bitpos: [11:8]; default: 0;
* NA
*/
uint32_t reg_dma2d_awqos:4;
/** reg_pdma_int_awqos : R/W; bitpos: [15:12]; default: 0;
* NA
*/
uint32_t reg_pdma_int_awqos:4;
/** reg_gmac_awqos : R/W; bitpos: [19:16]; default: 0;
* NA
*/
uint32_t reg_gmac_awqos:4;
/** reg_axi_sdmmc_int_awqos : R/W; bitpos: [23:20]; default: 0;
* NA
*/
uint32_t reg_axi_sdmmc_int_awqos:4;
uint32_t reserved_24:8;
};
uint32_t val;
} icm_mst_awqos_reg0_reg_t;
typedef struct {
volatile icm_ver_date_reg_t ver_date;
volatile icm_clk_en_reg_t clk_en;
uint32_t reserved_008[8];
volatile icm_mst_arqos_reg0_reg_t mst_arqos_reg0;
uint32_t reserved_02c;
volatile icm_mst_awqos_reg0_reg_t mst_awqos_reg0;
} icm_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(icm_dev_t) == 0x34, "Invalid size of icm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_XTAL32K_HYS_P
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_XTAL32K_HYS_N
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_GPIO2
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_GPIO3
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_GPIO4
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_GPIO5
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_TOUCH_GPIO6
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_TOUCH_GPIO7
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_TOUCH_GPIO8
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_TOUCH_GPIO9
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_TOUCH_GPIO10
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_TOUCH_GPIO11
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_TOUCH_GPIO12
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_TOUCH_GPIO13
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_TOUCH_GPIO14
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_TOUCH_GPIO15
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_TOUCH_GPIO16
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_TOUCH_GPIO17
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_TOUCH_GPIO18
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_TOUCH_GPIO19
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_GPIO20
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_GPIO21
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_GPIO22
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_GPIO23
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_GPIO24
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_GPIO25
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_U_GPIO26
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_U_GPIO27
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_U_GPIO28
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_U_GPIO29
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_U_GPIO30
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_U_GPIO31
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_U_GPIO32
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_U_USB_GPIO33
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_U_USB_GPIO34
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_U_GPIO35
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_U_GPIO36
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_U_GPIO37
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_U_GPIO38
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_U_GPIO39
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_U_GPIO40
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_U_GPIO41
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_U_ADC_GPIO42
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U_ADC_GPIO43
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U_ADC_GPIO44
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_U_ADC_GPIO45
#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_U_ADC_GPIO46
#define IO_MUX_GPIO47_REG PERIPHS_IO_MUX_U_ADC_GPIO47
#define IO_MUX_GPIO48_REG PERIPHS_IO_MUX_U_ADC_GPIO48
#define IO_MUX_GPIO49_REG PERIPHS_IO_MUX_U_ADC_GPIO49
#define IO_MUX_GPIO50_REG PERIPHS_IO_MUX_U_ADC_GPIO50
#define IO_MUX_GPIO51_REG PERIPHS_IO_MUX_U_ADC_GPIO51
#define IO_MUX_GPIO52_REG PERIPHS_IO_MUX_U_ADC_GPIO52
#define IO_MUX_GPIO53_REG PERIPHS_IO_MUX_U_ADC_GPIO53
#define IO_MUX_GPIO54_REG PERIPHS_IO_MUX_U_ADC_GPIO54
#define IO_MUX_GPIO55_REG PERIPHS_IO_MUX_U_ADC_GPIO55
#define IO_MUX_GPIO56_REG PERIPHS_IO_MUX_U_ADC_GPIO56
#define IO_MUX_GPIO57_REG PERIPHS_IO_MUX_U_ADC_GPIO57
#define IO_MUX_GPIO58_REG PERIPHS_IO_MUX_U_GPIO58
#define IO_MUX_GPIO59_REG PERIPHS_IO_MUX_U_GPIO59
#define IO_MUX_GPIO60_REG PERIPHS_IO_MUX_U_GPIO60
#define IO_MUX_GPIO61_REG PERIPHS_IO_MUX_U_GPIO61
#define IO_MUX_GPIO62_REG PERIPHS_IO_MUX_U_GPIO62
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define MAX_RTC_GPIO_NUM 7
#define MAX_PAD_GPIO_NUM 62
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_U_XTAL32K_HYS_P (REG_IO_MUX_BASE + 0x0)
#define FUNC_XTAL_32K_N_GPIO0_0 0
#define FUNC_XTAL_32K_N_GPIO0 1
#define PERIPHS_IO_MUX_U_XTAL32K_HYS_N (REG_IO_MUX_BASE + 0x4)
#define FUNC_XTAL_32K_P_GPIO1_0 0
#define FUNC_XTAL_32K_P_GPIO1 1
#define PERIPHS_IO_MUX_U_GPIO2 (REG_IO_MUX_BASE + 0x8)
#define FUNC_GPIO2_GPIO2_0 0
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_LCD_DATA19_OUT_PAD 3
#define PERIPHS_IO_MUX_U_GPIO3 (REG_IO_MUX_BASE + 0xc)
#define FUNC_GPIO3_GPIO3_0 0
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_LCD_DATA20_OUT_PAD 3
#define PERIPHS_IO_MUX_U_GPIO4 (REG_IO_MUX_BASE + 0x10)
#define FUNC_GPIO4_GPIO4_0 0
#define FUNC_GPIO4_GPIO4 1
#define FUNC_GPIO4_LCD_DATA21_OUT_PAD 3
#define PERIPHS_IO_MUX_U_GPIO5 (REG_IO_MUX_BASE + 0x14)
#define FUNC_GPIO5_GPIO5_0 0
#define FUNC_GPIO5_GPIO5 1
#define FUNC_GPIO5_LCD_DATA22_OUT_PAD 3
#define PERIPHS_IO_MUX_U_TOUCH_GPIO6 (REG_IO_MUX_BASE + 0x18)
#define FUNC_GPIO6_GPIO6_0 0
#define FUNC_GPIO6_GPIO6 1
#define PERIPHS_IO_MUX_U_TOUCH_GPIO7 (REG_IO_MUX_BASE + 0x1c)
#define FUNC_GPIO7_GPIO7_0 0
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_LCD_DATA23_OUT_PAD 3
#define PERIPHS_IO_MUX_U_TOUCH_GPIO8 (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO8_GPIO8_0 0
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GMAC_PHY_TXD0_PAD 2
#define FUNC_GPIO8_LCD_DATA0_OUT_PAD 3
#define PERIPHS_IO_MUX_U_TOUCH_GPIO9 (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO9_SPI2_HOLD_PAD 0
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GMAC_PHY_TXD1_PAD 2
#define FUNC_GPIO9_LCD_DATA1_OUT_PAD 3
#define FUNC_GPIO9_DBG_PSRAM_CK_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO10 (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO10_SPI2_CS_PAD 0
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_GMAC_PHY_TXD2_PAD 2
#define FUNC_GPIO10_LCD_DATA2_OUT_PAD 3
#define FUNC_GPIO10_DBG_PSRAM_CS_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO11 (REG_IO_MUX_BASE + 0x2c)
#define FUNC_GPIO11_SPI2_D_PAD 0
#define FUNC_GPIO11_GPIO11 1
#define FUNC_GPIO11_GMAC_PHY_TXD3_PAD 2
#define FUNC_GPIO11_LCD_DATA3_OUT_PAD 3
#define FUNC_GPIO11_DBG_PSRAM_D_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO12 (REG_IO_MUX_BASE + 0x30)
#define FUNC_GPIO12_SPI2_CK_PAD 0
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GMAC_PHY_TXEN_PAD 2
#define FUNC_GPIO12_LCD_DATA4_OUT_PAD 3
#define FUNC_GPIO12_DBG_PSRAM_Q_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO13 (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO13_SPI2_Q_PAD 0
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GMAC_RMII_CLK_PAD 2
#define FUNC_GPIO13_LCD_DATA5_OUT_PAD 3
#define FUNC_GPIO13_DBG_PSRAM_WP_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO14 (REG_IO_MUX_BASE + 0x38)
#define FUNC_GPIO14_SPI2_WP_PAD 0
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GMAC_RX_CLK_PAD 2
#define FUNC_GPIO14_LCD_DATA6_OUT_PAD 3
#define FUNC_GPIO14_DBG_PSRAM_HOLD_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO15 (REG_IO_MUX_BASE + 0x3c)
#define FUNC_GPIO15_SPI2_IO4_PAD 0
#define FUNC_GPIO15_GPIO15 1
#define FUNC_GPIO15_GMAC_PHY_RXDV_PAD 2
#define FUNC_GPIO15_LCD_DATA7_OUT_PAD 3
#define FUNC_GPIO15_DBG_PSRAM_DQ4_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO16 (REG_IO_MUX_BASE + 0x40)
#define FUNC_GPIO16_SPI2_IO5_PAD 0
#define FUNC_GPIO16_GPIO16 1
#define FUNC_GPIO16_GMAC_PHY_RXD3_PAD 2
#define FUNC_GPIO16_LCD_DATA8_OUT_PAD 3
#define FUNC_GPIO16_DBG_PSRAM_DQ5_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO17 (REG_IO_MUX_BASE + 0x44)
#define FUNC_GPIO17_SPI2_IO6_PAD 0
#define FUNC_GPIO17_GPIO17 1
#define FUNC_GPIO17_GMAC_PHY_RXD2_PAD 2
#define FUNC_GPIO17_LCD_DATA9_OUT_PAD 3
#define FUNC_GPIO17_DBG_PSRAM_DQ6_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO18 (REG_IO_MUX_BASE + 0x48)
#define FUNC_GPIO18_SPI2_IO7_PAD 0
#define FUNC_GPIO18_GPIO18 1
#define FUNC_GPIO18_GMAC_PHY_RXD1_PAD 2
#define FUNC_GPIO18_LCD_DATA10_OUT_PAD 3
#define FUNC_GPIO18_DBG_PSRAM_DQ7_PAD 4
#define PERIPHS_IO_MUX_U_TOUCH_GPIO19 (REG_IO_MUX_BASE + 0x4c)
#define FUNC_GPIO19_SPI2_DQS_PAD 0
#define FUNC_GPIO19_GPIO19 1
#define FUNC_GPIO19_GMAC_PHY_RXD0_PAD 2
#define FUNC_GPIO19_LCD_DATA11_OUT_PAD 3
#define FUNC_GPIO19_DBG_PSRAM_DQS_0_PAD 4
#define PERIPHS_IO_MUX_U_GPIO20 (REG_IO_MUX_BASE + 0x50)
#define FUNC_SDIO_DATA0_GPIO20_0 0
#define FUNC_SDIO_DATA0_GPIO20 1
#define FUNC_SDIO_DATA0_SPI2_CK_PAD 2
#define FUNC_SDIO_DATA0_DBG_FLASH_CK_PAD 4
#define PERIPHS_IO_MUX_U_GPIO21 (REG_IO_MUX_BASE + 0x54)
#define FUNC_SDIO_DATA1_GPIO21_0 0
#define FUNC_SDIO_DATA1_GPIO21 1
#define FUNC_SDIO_DATA1_SPI2_D_PAD 2
#define FUNC_SDIO_DATA1_DBG_FLASH_D_PAD 4
#define PERIPHS_IO_MUX_U_GPIO22 (REG_IO_MUX_BASE + 0x58)
#define FUNC_SDIO_DATA2_GPIO22_0 0
#define FUNC_SDIO_DATA2_GPIO22 1
#define FUNC_SDIO_DATA2_SPI2_Q_PAD 2
#define FUNC_SDIO_DATA2_DBG_FLASH_CS_PAD 4
#define PERIPHS_IO_MUX_U_GPIO23 (REG_IO_MUX_BASE + 0x5c)
#define FUNC_SDIO_DATA3_GPIO23_0 0
#define FUNC_SDIO_DATA3_GPIO23 1
#define FUNC_SDIO_DATA3_SPI2_CS_PAD 2
#define FUNC_SDIO_DATA3_DBG_FLASH_Q_PAD 4
#define PERIPHS_IO_MUX_U_GPIO24 (REG_IO_MUX_BASE + 0x60)
#define FUNC_SDIO_CLK_GPIO24_0 0
#define FUNC_SDIO_CLK_GPIO24 1
#define FUNC_SDIO_CLK_SPI2_HOLD_PAD 2
#define FUNC_SDIO_CLK_DBG_FLASH_WP_PAD 4
#define PERIPHS_IO_MUX_U_GPIO25 (REG_IO_MUX_BASE + 0x64)
#define FUNC_SDIO_CMD_GPIO25_0 0
#define FUNC_SDIO_CMD_GPIO25 1
#define FUNC_SDIO_CMD_SPI2_WP_PAD 2
#define FUNC_SDIO_CMD_DBG_FLASH_HOLD_PAD 4
#define PERIPHS_IO_MUX_U_GPIO26 (REG_IO_MUX_BASE + 0x68)
#define FUNC_SPICS_FLASH_CS_PAD 0
#define FUNC_SPICS_GPIO26 1
#define PERIPHS_IO_MUX_U_GPIO27 (REG_IO_MUX_BASE + 0x6c)
#define FUNC_SPIQ_FLASH_Q_PAD 0
#define FUNC_SPIQ_GPIO27 1
#define PERIPHS_IO_MUX_U_GPIO28 (REG_IO_MUX_BASE + 0x70)
#define FUNC_SPIWP_FLASH_WP_PAD 0
#define FUNC_SPIWP_GPIO28 1
#define PERIPHS_IO_MUX_U_GPIO29 (REG_IO_MUX_BASE + 0x74)
#define FUNC_VDD_SPI_GPIO29_0 0
#define FUNC_VDD_SPI_GPIO29 1
#define PERIPHS_IO_MUX_U_GPIO30 (REG_IO_MUX_BASE + 0x78)
#define FUNC_SPIHD_FLASH_HOLD_PAD 0
#define FUNC_SPIHD_GPIO30 1
#define PERIPHS_IO_MUX_U_GPIO31 (REG_IO_MUX_BASE + 0x7c)
#define FUNC_SPICLK_FLASH_CK_PAD 0
#define FUNC_SPICLK_GPIO31 1
#define PERIPHS_IO_MUX_U_GPIO32 (REG_IO_MUX_BASE + 0x80)
#define FUNC_SPID_FLASH_D_PAD 0
#define FUNC_SPID_GPIO32 1
#define PERIPHS_IO_MUX_U_USB_GPIO33 (REG_IO_MUX_BASE + 0x84)
#define FUNC_GPIO33_GPIO33_0 0
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_LCD_DATA12_OUT_PAD 3
#define PERIPHS_IO_MUX_U_USB_GPIO34 (REG_IO_MUX_BASE + 0x88)
#define FUNC_GPIO34_GPIO34_0 0
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_LCD_DATA13_OUT_PAD 3
#define PERIPHS_IO_MUX_U_GPIO35 (REG_IO_MUX_BASE + 0x8c)
#define FUNC_GPIO35_GPIO35_0 0
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_REF_GMAC_CLK_PAD 2
#define FUNC_GPIO35_LCD_DATA14_OUT_PAD 3
#define FUNC_GPIO35_SD2_CDATA0_PAD 4
// Strapping: LDO sel
#define PERIPHS_IO_MUX_U_GPIO36 (REG_IO_MUX_BASE + 0x90)
#define FUNC_GPIO36_GPIO36_0 0
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GMAC_PHY_RXDV_PAD 2
#define FUNC_GPIO36_LCD_DATA15_OUT_PAD 3
#define FUNC_GPIO36_SD2_CDATA1_PAD 4
// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag
#define PERIPHS_IO_MUX_U_GPIO37 (REG_IO_MUX_BASE + 0x94)
#define FUNC_GPIO37_GPIO37_0 0
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_GMAC_PHY_TXEN_PAD 2
#define FUNC_GPIO37_LCD_DATA16_OUT_PAD 3
#define FUNC_GPIO37_SD2_CDATA2_PAD 4
// Strapping: Boot Mode select 0
#define PERIPHS_IO_MUX_U_GPIO38 (REG_IO_MUX_BASE + 0x98)
#define FUNC_GPIO38_GPIO38_0 0
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_GMAC_PHY_RXD3_PAD 2
#define FUNC_GPIO38_LCD_DATA17_OUT_PAD 3
#define FUNC_GPIO38_SD2_CDATA3_PAD 4
// Strapping: Boot Mode select 1
#define PERIPHS_IO_MUX_U_GPIO39 (REG_IO_MUX_BASE + 0x9c)
#define FUNC_GPIO39_GPIO39_0 0
#define FUNC_GPIO39_GPIO39 1
#define FUNC_GPIO39_GMAC_PHY_RXD2_PAD 2
#define FUNC_GPIO39_LCD_DATA18_OUT_PAD 3
#define FUNC_GPIO39_SD2_CCLK_PAD 4
// Strapping: Boot Mode select 2
#define PERIPHS_IO_MUX_U_GPIO40 (REG_IO_MUX_BASE + 0xa0)
#define FUNC_GPIO40_GPIO40_0 0
#define FUNC_GPIO40_GPIO40 1
#define FUNC_GPIO40_GMAC_PHY_RXD1_PAD 2
#define FUNC_GPIO40_LCD_PCLK_PAD 3
#define FUNC_GPIO40_SD2_CCMD_PAD 4
#define PERIPHS_IO_MUX_U_GPIO41 (REG_IO_MUX_BASE + 0xa4)
#define FUNC_GPIO41_GPIO41_0 0
#define FUNC_GPIO41_GPIO41 1
#define FUNC_GPIO41_GMAC_PHY_RXD0_PAD 2
#define PERIPHS_IO_MUX_U_ADC_GPIO42 (REG_IO_MUX_BASE + 0xa8)
#define FUNC_GPIO42_GPIO42_0 0
#define FUNC_GPIO42_GPIO42 1
#define FUNC_GPIO42_GMAC_RX_CLK_PAD 2
#define PERIPHS_IO_MUX_U_ADC_GPIO43 (REG_IO_MUX_BASE + 0xac)
#define FUNC_GPIO43_GPIO43_0 0
#define FUNC_GPIO43_GPIO43 1
#define FUNC_GPIO43_GMAC_RMII_CLK_PAD 2
#define FUNC_GPIO43_LCD_H_ENABLE_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO44 (REG_IO_MUX_BASE + 0xb0)
#define FUNC_GPIO44_GPIO44_0 0
#define FUNC_GPIO44_GPIO44 1
#define FUNC_GPIO44_GMAC_PHY_TXD0_PAD 2
#define FUNC_GPIO44_LCD_H_SYNC_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO45 (REG_IO_MUX_BASE + 0xb4)
#define FUNC_GPIO45_GPIO45_0 0
#define FUNC_GPIO45_GPIO45 1
#define FUNC_GPIO45_GMAC_PHY_TXD1_PAD 2
#define FUNC_GPIO45_LCD_V_SYNC_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO46 (REG_IO_MUX_BASE + 0xb8)
#define FUNC_GPIO46_GPIO46_0 0
#define FUNC_GPIO46_GPIO46 1
#define FUNC_GPIO46_GMAC_PHY_TXD2_PAD 2
#define FUNC_GPIO46_CAM_DATA0_IN_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO47 (REG_IO_MUX_BASE + 0xbc)
#define FUNC_GPIO47_GPIO47_0 0
#define FUNC_GPIO47_GPIO47 1
#define FUNC_GPIO47_GMAC_PHY_TXD3_PAD 2
#define FUNC_GPIO47_CAM_DATA1_IN_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO48 (REG_IO_MUX_BASE + 0xc0)
#define FUNC_GPIO48_GPIO48_0 0
#define FUNC_GPIO48_GPIO48 1
#define FUNC_GPIO48_CAM_DATA2_IN_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO49 (REG_IO_MUX_BASE + 0xc4)
#define FUNC_GPIO49_GPIO49_0 0
#define FUNC_GPIO49_GPIO49 1
#define FUNC_GPIO49_CAM_DATA3_IN_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO50 (REG_IO_MUX_BASE + 0xc8)
#define FUNC_GPIO50_GPIO50_0 0
#define FUNC_GPIO50_GPIO50 1
#define FUNC_GPIO50_CAM_DATA4_IN_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO51 (REG_IO_MUX_BASE + 0xcc)
#define FUNC_GPIO51_GPIO51_0 0
#define FUNC_GPIO51_GPIO51 1
#define FUNC_GPIO51_CAM_DATA5_IN_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO52 (REG_IO_MUX_BASE + 0xd0)
#define FUNC_GPIO52_GPIO52_0 0
#define FUNC_GPIO52_GPIO52 1
#define FUNC_GPIO52_SPI2_CS_PAD 2
#define FUNC_GPIO52_CAM_DATA6_IN_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO53 (REG_IO_MUX_BASE + 0xd4)
#define FUNC_GPIO53_GPIO53_0 0
#define FUNC_GPIO53_GPIO53 1
#define FUNC_GPIO53_SPI2_CK_PAD 2
#define FUNC_GPIO53_CAM_DATA7_IN_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO54 (REG_IO_MUX_BASE + 0xd8)
#define FUNC_MTDO_MTDO 0
#define FUNC_MTDO_GPIO54 1
#define FUNC_MTDO_SPI2_D_PAD 2
#define FUNC_MTDO_CAM_PCLK_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO55 (REG_IO_MUX_BASE + 0xdc)
#define FUNC_MTCK_MTCK 0
#define FUNC_MTCK_GPIO55 1
#define FUNC_MTCK_SPI2_Q_PAD 2
#define FUNC_MTCK_CAM_XCLK_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO56 (REG_IO_MUX_BASE + 0xe0)
#define FUNC_MTDI_MTDI 0
#define FUNC_MTDI_GPIO56 1
#define FUNC_MTDI_SPI2_HOLD_PAD 2
#define FUNC_MTDI_CAM_V_SYNC_PAD 3
#define PERIPHS_IO_MUX_U_ADC_GPIO57 (REG_IO_MUX_BASE + 0xe4)
#define FUNC_MTMS_MTMS 0
#define FUNC_MTMS_GPIO57 1
#define FUNC_MTMS_SPI2_WP_PAD 2
#define FUNC_MTMS_CAM_H_SYNC_PAD 3
#define PERIPHS_IO_MUX_U_GPIO58 (REG_IO_MUX_BASE + 0xe8)
#define FUNC_GPIO58_UART0_TXD_PAD 0
#define FUNC_GPIO58_GPIO58 1
#define PERIPHS_IO_MUX_U_GPIO59 (REG_IO_MUX_BASE + 0xec)
#define FUNC_GPIO59_UART0_RXD_PAD 0
#define FUNC_GPIO59_GPIO59 1
// Strapping: Boot Mode select 3
#define PERIPHS_IO_MUX_U_GPIO60 (REG_IO_MUX_BASE + 0xf0)
#define FUNC_GPIO60_GPIO60_0 0
#define FUNC_GPIO60_GPIO60 1
// Strapping: Boot Mode select 4
#define PERIPHS_IO_MUX_U_GPIO61 (REG_IO_MUX_BASE + 0xf4)
#define FUNC_GPIO61_GPIO61_0 0
#define FUNC_GPIO61_GPIO61 1
#define PERIPHS_IO_MUX_U_GPIO62 (REG_IO_MUX_BASE + 0xf8)
#define FUNC_GPIO62_GPIO62_0 0
#define FUNC_GPIO62_GPIO62 1
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0x1FC)
/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2502070 ; */
/*description: Version control register.*/
#define IO_MUX_REG_DATE 0x0FFFFFFF
#define IO_MUX_REG_DATE_M ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S))
#define IO_MUX_REG_DATE_V 0xFFFFFFF
#define IO_MUX_REG_DATE_S 0

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components/soc/esp32s31/register/soc/io_mux_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of gpio register
* IO MUX configuration register for GPIOn
*/
typedef union {
struct {
/** gpio_mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_mcu_oe:1;
/** gpio_slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for GPIOn.
* 0: Not enter
* 1: Enter
*/
uint32_t gpio_slp_sel:1;
/** gpio_mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_mcu_wpd:1;
/** gpio_mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_mcu_wpu:1;
/** gpio_mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_mcu_ie:1;
/** gpio_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of GPIOn during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t gpio_mcu_drv:2;
/** gpio_fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_fun_wpd:1;
/** gpio_fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_fun_wpu:1;
/** gpio_fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_fun_ie:1;
/** gpio_fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of GPIOn.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t gpio_fun_drv:2;
/** gpio_mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
uint32_t gpio_mcu_sel:3;
/** gpio_filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_filter_en:1;
/** gpio_hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* IO_MUX_GPIOn_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
uint32_t gpio_hys_en:1;
/** gpio_hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for GPIOn.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN
*/
uint32_t gpio_hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} io_mux_gpio_reg_t;
/** Group: Version Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 38805616;
* Version control register
*/
uint32_t reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} io_mux_date_reg_t;
typedef struct io_mux_dev_t {
volatile io_mux_gpio_reg_t gpio[63];
uint32_t reserved_0fc[64];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/iomux_mspi_pin_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** IOMUX_MSPI_PIN_CLK_EN0_REG register
* apb registers auto clock gating reg
*/
#define IOMUX_MSPI_PIN_CLK_EN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x0)
/** IOMUX_MSPI_PIN_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* 1: auto clock gating on
* 0: auto clock gating off
*/
#define IOMUX_MSPI_PIN_REG_CLK_EN (BIT(0))
#define IOMUX_MSPI_PIN_REG_CLK_EN_M (IOMUX_MSPI_PIN_REG_CLK_EN_V << IOMUX_MSPI_PIN_REG_CLK_EN_S)
#define IOMUX_MSPI_PIN_REG_CLK_EN_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_CLK_EN_S 0
/** IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x1c)
/** IOMUX_MSPI_PIN_REG_PSRAM_D_DLI : R/W; bitpos: [3:0]; default: 0;
* psram d dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_D_DLC : R/W; bitpos: [7:4]; default: 0;
* psram d dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_D_HYS : R/W; bitpos: [8]; default: 0;
* psram d sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_D_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_D_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_D_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_D_WPU : R/W; bitpos: [10]; default: 0;
* psram d wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_D_WPD : R/W; bitpos: [11]; default: 0;
* psram d wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_D_DRV : R/W; bitpos: [14:12]; default: 4;
* psram d drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD : R/W; bitpos: [15]; default: 0;
* psram d hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_Q_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_Q_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x20)
/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI : R/W; bitpos: [3:0]; default: 0;
* psram q dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC : R/W; bitpos: [7:4]; default: 0;
* psram q dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS : R/W; bitpos: [8]; default: 0;
* psram q sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_Q_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU : R/W; bitpos: [10]; default: 0;
* psram q wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD : R/W; bitpos: [11]; default: 0;
* psram q wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV : R/W; bitpos: [14:12]; default: 4;
* psram q drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD : R/W; bitpos: [15]; default: 0;
* psram q hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_WP_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_WP_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x24)
/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI : R/W; bitpos: [3:0]; default: 0;
* psram wp dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC : R/W; bitpos: [7:4]; default: 0;
* psram wp dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS : R/W; bitpos: [8]; default: 0;
* psram wp sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_WP_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU : R/W; bitpos: [10]; default: 0;
* psram wp wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD : R/W; bitpos: [11]; default: 0;
* psram wp wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV : R/W; bitpos: [14:12]; default: 4;
* psram wp drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD : R/W; bitpos: [15]; default: 0;
* psram wp hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_HOLD_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_HOLD_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x28)
/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI : R/W; bitpos: [3:0]; default: 0;
* psram hold dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC : R/W; bitpos: [7:4]; default: 0;
* psram hold dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS : R/W; bitpos: [8]; default: 0;
* psram hold sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU : R/W; bitpos: [10]; default: 0;
* psram hold wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD : R/W; bitpos: [11]; default: 0;
* psram hold wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV : R/W; bitpos: [14:12]; default: 4;
* psram hold drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD : R/W; bitpos: [15]; default: 0;
* psram hold hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_DQ4_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_DQ4_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x2c)
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI : R/W; bitpos: [3:0]; default: 0;
* psram dq4 dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC : R/W; bitpos: [7:4]; default: 0;
* psram dq4 dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS : R/W; bitpos: [8]; default: 0;
* psram dq4 sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU : R/W; bitpos: [10]; default: 0;
* psram dq4 wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD : R/W; bitpos: [11]; default: 0;
* psram dq4 wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV : R/W; bitpos: [14:12]; default: 4;
* psram dq4 drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD : R/W; bitpos: [15]; default: 0;
* psram dq4 hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_DQ5_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_DQ5_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x30)
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI : R/W; bitpos: [3:0]; default: 0;
* psram dq5 dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC : R/W; bitpos: [7:4]; default: 0;
* psram dq5 dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS : R/W; bitpos: [8]; default: 0;
* psram dq5 sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU : R/W; bitpos: [10]; default: 0;
* psram dq5 wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD : R/W; bitpos: [11]; default: 0;
* psram dq5 wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV : R/W; bitpos: [14:12]; default: 4;
* psram dq5 drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD : R/W; bitpos: [15]; default: 0;
* psram dq5 hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_DQ6_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_DQ6_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x34)
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI : R/W; bitpos: [3:0]; default: 0;
* psram dq6 dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC : R/W; bitpos: [7:4]; default: 0;
* psram dq6 dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS : R/W; bitpos: [8]; default: 0;
* psram dq6 sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU : R/W; bitpos: [10]; default: 0;
* psram dq6 wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD : R/W; bitpos: [11]; default: 0;
* psram dq6 wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV : R/W; bitpos: [14:12]; default: 4;
* psram dq6 drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD : R/W; bitpos: [15]; default: 0;
* psram dq6 hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_DQ7_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_DQ7_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x38)
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI : R/W; bitpos: [3:0]; default: 0;
* psram dq7 dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC : R/W; bitpos: [7:4]; default: 0;
* psram dq7 dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS : R/W; bitpos: [8]; default: 0;
* psram dq7 sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU : R/W; bitpos: [10]; default: 0;
* psram dq7 wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD : R/W; bitpos: [11]; default: 0;
* psram dq7 wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV : R/W; bitpos: [14:12]; default: 4;
* psram dq7 drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD : R/W; bitpos: [15]; default: 0;
* psram dq7 hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_DQS_0_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_DQS_0_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x3c)
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD : R/W; bitpos: [0]; default: 0;
* psram xpd dqs0
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD (BIT(0))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE : R/W; bitpos: [2:1]; default: 0;
* psram dqs0 phase
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE 0x00000003U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_V 0x00000003U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_S 1
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI : R/W; bitpos: [6:3]; default: 0;
* psram dqs0 dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_S 3
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90 : R/W; bitpos: [10:7]; default: 0;
* psram dqs0 delay 90
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_S 7
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS : R/W; bitpos: [11]; default: 0;
* psram dqs0 sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE : R/W; bitpos: [12]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE (BIT(12))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU : R/W; bitpos: [13]; default: 0;
* psram dqs0 wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU (BIT(13))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_S 13
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD : R/W; bitpos: [14]; default: 0;
* psram dqs0 wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD (BIT(14))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_S 14
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV : R/W; bitpos: [17:15]; default: 4;
* psram dqs0 drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_S 15
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270 : R/W; bitpos: [21:18]; default: 0;
* psram dqs0 delay 270
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_S 18
/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD : R/W; bitpos: [22]; default: 0;
* psram dqs hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD (BIT(22))
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_S 22
/** IOMUX_MSPI_PIN_PSRAM_CK_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_CK_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x40)
/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI : R/W; bitpos: [3:0]; default: 0;
* psram ck dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC : R/W; bitpos: [7:4]; default: 0;
* psram ck dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS : R/W; bitpos: [8]; default: 0;
* psram ck sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_CK_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU : R/W; bitpos: [10]; default: 0;
* psram ck wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD : R/W; bitpos: [11]; default: 0;
* psram ck wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV : R/W; bitpos: [14:12]; default: 4;
* psram ck drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD : R/W; bitpos: [15]; default: 0;
* psram ck hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_S 15
/** IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
#define IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x44)
/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI : R/W; bitpos: [3:0]; default: 0;
* psram cs dli
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_S 0
/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC : R/W; bitpos: [7:4]; default: 0;
* psram cs dlc
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_V 0x0000000FU
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_S 4
/** IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS : R/W; bitpos: [8]; default: 0;
* psram cs sl
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS (BIT(8))
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_S 8
/** IOMUX_MSPI_PIN_REG_PSRAM_CS_IE : R/W; bitpos: [9]; default: 0;
* Reserved
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE (BIT(9))
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_S 9
/** IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU : R/W; bitpos: [10]; default: 0;
* psram cs wpu
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU (BIT(10))
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_S 10
/** IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD : R/W; bitpos: [11]; default: 0;
* psram cs wpd
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD (BIT(11))
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_S 11
/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV : R/W; bitpos: [14:12]; default: 4;
* psram cs drv
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_V 0x00000007U
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_S 12
/** IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD : R/W; bitpos: [15]; default: 0;
* psram cs hold
*/
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD (BIT(15))
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_S)
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_V 0x00000001U
#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_S 15
#ifdef __cplusplus
}
#endif

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components/soc/esp32s31/register/soc/iomux_mspi_pin_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: clk_en */
/** Type of clk_en0 register
* apb registers auto clock gating reg
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* 1: auto clock gating on
* 0: auto clock gating off
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} iomux_mspi_pin_clk_en0_reg_t;
/** Group: psram_d_pin */
/** Type of psram_d_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_d_dli : R/W; bitpos: [3:0]; default: 0;
* psram d dli
*/
uint32_t reg_psram_d_dli:4;
/** reg_psram_d_dlc : R/W; bitpos: [7:4]; default: 0;
* psram d dlc
*/
uint32_t reg_psram_d_dlc:4;
/** reg_psram_d_hys : R/W; bitpos: [8]; default: 0;
* psram d sl
*/
uint32_t reg_psram_d_hys:1;
/** reg_psram_d_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_d_ie:1;
/** reg_psram_d_wpu : R/W; bitpos: [10]; default: 0;
* psram d wpu
*/
uint32_t reg_psram_d_wpu:1;
/** reg_psram_d_wpd : R/W; bitpos: [11]; default: 0;
* psram d wpd
*/
uint32_t reg_psram_d_wpd:1;
/** reg_psram_d_drv : R/W; bitpos: [14:12]; default: 4;
* psram d drv
*/
uint32_t reg_psram_d_drv:3;
/** reg_psram_d_hold : R/W; bitpos: [15]; default: 0;
* psram d hold
*/
uint32_t reg_psram_d_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_d_pin0_reg_t;
/** Group: psram_q_pin */
/** Type of psram_q_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_q_dli : R/W; bitpos: [3:0]; default: 0;
* psram q dli
*/
uint32_t reg_psram_q_dli:4;
/** reg_psram_q_dlc : R/W; bitpos: [7:4]; default: 0;
* psram q dlc
*/
uint32_t reg_psram_q_dlc:4;
/** reg_psram_q_hys : R/W; bitpos: [8]; default: 0;
* psram q sl
*/
uint32_t reg_psram_q_hys:1;
/** reg_psram_q_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_q_ie:1;
/** reg_psram_q_wpu : R/W; bitpos: [10]; default: 0;
* psram q wpu
*/
uint32_t reg_psram_q_wpu:1;
/** reg_psram_q_wpd : R/W; bitpos: [11]; default: 0;
* psram q wpd
*/
uint32_t reg_psram_q_wpd:1;
/** reg_psram_q_drv : R/W; bitpos: [14:12]; default: 4;
* psram q drv
*/
uint32_t reg_psram_q_drv:3;
/** reg_psram_q_hold : R/W; bitpos: [15]; default: 0;
* psram q hold
*/
uint32_t reg_psram_q_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_q_pin0_reg_t;
/** Group: psram_wp_pin */
/** Type of psram_wp_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_wp_dli : R/W; bitpos: [3:0]; default: 0;
* psram wp dli
*/
uint32_t reg_psram_wp_dli:4;
/** reg_psram_wp_dlc : R/W; bitpos: [7:4]; default: 0;
* psram wp dlc
*/
uint32_t reg_psram_wp_dlc:4;
/** reg_psram_wp_hys : R/W; bitpos: [8]; default: 0;
* psram wp sl
*/
uint32_t reg_psram_wp_hys:1;
/** reg_psram_wp_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_wp_ie:1;
/** reg_psram_wp_wpu : R/W; bitpos: [10]; default: 0;
* psram wp wpu
*/
uint32_t reg_psram_wp_wpu:1;
/** reg_psram_wp_wpd : R/W; bitpos: [11]; default: 0;
* psram wp wpd
*/
uint32_t reg_psram_wp_wpd:1;
/** reg_psram_wp_drv : R/W; bitpos: [14:12]; default: 4;
* psram wp drv
*/
uint32_t reg_psram_wp_drv:3;
/** reg_psram_wp_hold : R/W; bitpos: [15]; default: 0;
* psram wp hold
*/
uint32_t reg_psram_wp_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_wp_pin0_reg_t;
/** Group: psram_hold_pin */
/** Type of psram_hold_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_hold_dli : R/W; bitpos: [3:0]; default: 0;
* psram hold dli
*/
uint32_t reg_psram_hold_dli:4;
/** reg_psram_hold_dlc : R/W; bitpos: [7:4]; default: 0;
* psram hold dlc
*/
uint32_t reg_psram_hold_dlc:4;
/** reg_psram_hold_hys : R/W; bitpos: [8]; default: 0;
* psram hold sl
*/
uint32_t reg_psram_hold_hys:1;
/** reg_psram_hold_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_hold_ie:1;
/** reg_psram_hold_wpu : R/W; bitpos: [10]; default: 0;
* psram hold wpu
*/
uint32_t reg_psram_hold_wpu:1;
/** reg_psram_hold_wpd : R/W; bitpos: [11]; default: 0;
* psram hold wpd
*/
uint32_t reg_psram_hold_wpd:1;
/** reg_psram_hold_drv : R/W; bitpos: [14:12]; default: 4;
* psram hold drv
*/
uint32_t reg_psram_hold_drv:3;
/** reg_psram_hold_hold : R/W; bitpos: [15]; default: 0;
* psram hold hold
*/
uint32_t reg_psram_hold_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_hold_pin0_reg_t;
/** Group: psram_dq4_pin */
/** Type of psram_dq4_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_dq4_dli : R/W; bitpos: [3:0]; default: 0;
* psram dq4 dli
*/
uint32_t reg_psram_dq4_dli:4;
/** reg_psram_dq4_dlc : R/W; bitpos: [7:4]; default: 0;
* psram dq4 dlc
*/
uint32_t reg_psram_dq4_dlc:4;
/** reg_psram_dq4_hys : R/W; bitpos: [8]; default: 0;
* psram dq4 sl
*/
uint32_t reg_psram_dq4_hys:1;
/** reg_psram_dq4_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_dq4_ie:1;
/** reg_psram_dq4_wpu : R/W; bitpos: [10]; default: 0;
* psram dq4 wpu
*/
uint32_t reg_psram_dq4_wpu:1;
/** reg_psram_dq4_wpd : R/W; bitpos: [11]; default: 0;
* psram dq4 wpd
*/
uint32_t reg_psram_dq4_wpd:1;
/** reg_psram_dq4_drv : R/W; bitpos: [14:12]; default: 4;
* psram dq4 drv
*/
uint32_t reg_psram_dq4_drv:3;
/** reg_psram_dq4_hold : R/W; bitpos: [15]; default: 0;
* psram dq4 hold
*/
uint32_t reg_psram_dq4_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_dq4_pin0_reg_t;
/** Group: psram_dq5_pin */
/** Type of psram_dq5_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_dq5_dli : R/W; bitpos: [3:0]; default: 0;
* psram dq5 dli
*/
uint32_t reg_psram_dq5_dli:4;
/** reg_psram_dq5_dlc : R/W; bitpos: [7:4]; default: 0;
* psram dq5 dlc
*/
uint32_t reg_psram_dq5_dlc:4;
/** reg_psram_dq5_hys : R/W; bitpos: [8]; default: 0;
* psram dq5 sl
*/
uint32_t reg_psram_dq5_hys:1;
/** reg_psram_dq5_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_dq5_ie:1;
/** reg_psram_dq5_wpu : R/W; bitpos: [10]; default: 0;
* psram dq5 wpu
*/
uint32_t reg_psram_dq5_wpu:1;
/** reg_psram_dq5_wpd : R/W; bitpos: [11]; default: 0;
* psram dq5 wpd
*/
uint32_t reg_psram_dq5_wpd:1;
/** reg_psram_dq5_drv : R/W; bitpos: [14:12]; default: 4;
* psram dq5 drv
*/
uint32_t reg_psram_dq5_drv:3;
/** reg_psram_dq5_hold : R/W; bitpos: [15]; default: 0;
* psram dq5 hold
*/
uint32_t reg_psram_dq5_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_dq5_pin0_reg_t;
/** Group: psram_dq6_pin */
/** Type of psram_dq6_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_dq6_dli : R/W; bitpos: [3:0]; default: 0;
* psram dq6 dli
*/
uint32_t reg_psram_dq6_dli:4;
/** reg_psram_dq6_dlc : R/W; bitpos: [7:4]; default: 0;
* psram dq6 dlc
*/
uint32_t reg_psram_dq6_dlc:4;
/** reg_psram_dq6_hys : R/W; bitpos: [8]; default: 0;
* psram dq6 sl
*/
uint32_t reg_psram_dq6_hys:1;
/** reg_psram_dq6_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_dq6_ie:1;
/** reg_psram_dq6_wpu : R/W; bitpos: [10]; default: 0;
* psram dq6 wpu
*/
uint32_t reg_psram_dq6_wpu:1;
/** reg_psram_dq6_wpd : R/W; bitpos: [11]; default: 0;
* psram dq6 wpd
*/
uint32_t reg_psram_dq6_wpd:1;
/** reg_psram_dq6_drv : R/W; bitpos: [14:12]; default: 4;
* psram dq6 drv
*/
uint32_t reg_psram_dq6_drv:3;
/** reg_psram_dq6_hold : R/W; bitpos: [15]; default: 0;
* psram dq6 hold
*/
uint32_t reg_psram_dq6_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_dq6_pin0_reg_t;
/** Group: psram_dq7_pin */
/** Type of psram_dq7_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_dq7_dli : R/W; bitpos: [3:0]; default: 0;
* psram dq7 dli
*/
uint32_t reg_psram_dq7_dli:4;
/** reg_psram_dq7_dlc : R/W; bitpos: [7:4]; default: 0;
* psram dq7 dlc
*/
uint32_t reg_psram_dq7_dlc:4;
/** reg_psram_dq7_hys : R/W; bitpos: [8]; default: 0;
* psram dq7 sl
*/
uint32_t reg_psram_dq7_hys:1;
/** reg_psram_dq7_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_dq7_ie:1;
/** reg_psram_dq7_wpu : R/W; bitpos: [10]; default: 0;
* psram dq7 wpu
*/
uint32_t reg_psram_dq7_wpu:1;
/** reg_psram_dq7_wpd : R/W; bitpos: [11]; default: 0;
* psram dq7 wpd
*/
uint32_t reg_psram_dq7_wpd:1;
/** reg_psram_dq7_drv : R/W; bitpos: [14:12]; default: 4;
* psram dq7 drv
*/
uint32_t reg_psram_dq7_drv:3;
/** reg_psram_dq7_hold : R/W; bitpos: [15]; default: 0;
* psram dq7 hold
*/
uint32_t reg_psram_dq7_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_dq7_pin0_reg_t;
/** Group: psram_dqs_0_pin */
/** Type of psram_dqs_0_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_dqs_0_xpd : R/W; bitpos: [0]; default: 0;
* psram xpd dqs0
*/
uint32_t reg_psram_dqs_0_xpd:1;
/** reg_psram_dqs_0_phase : R/W; bitpos: [2:1]; default: 0;
* psram dqs0 phase
*/
uint32_t reg_psram_dqs_0_phase:2;
/** reg_psram_dqs_0_dli : R/W; bitpos: [6:3]; default: 0;
* psram dqs0 dli
*/
uint32_t reg_psram_dqs_0_dli:4;
/** reg_psram_dqs_0_delay_90 : R/W; bitpos: [10:7]; default: 0;
* psram dqs0 delay 90
*/
uint32_t reg_psram_dqs_0_delay_90:4;
/** reg_psram_dqs_0_hys : R/W; bitpos: [11]; default: 0;
* psram dqs0 sl
*/
uint32_t reg_psram_dqs_0_hys:1;
/** reg_psram_dqs_0_ie : R/W; bitpos: [12]; default: 0;
* Reserved
*/
uint32_t reg_psram_dqs_0_ie:1;
/** reg_psram_dqs_0_wpu : R/W; bitpos: [13]; default: 0;
* psram dqs0 wpu
*/
uint32_t reg_psram_dqs_0_wpu:1;
/** reg_psram_dqs_0_wpd : R/W; bitpos: [14]; default: 0;
* psram dqs0 wpd
*/
uint32_t reg_psram_dqs_0_wpd:1;
/** reg_psram_dqs_0_drv : R/W; bitpos: [17:15]; default: 4;
* psram dqs0 drv
*/
uint32_t reg_psram_dqs_0_drv:3;
/** reg_psram_dqs_0_delay_270 : R/W; bitpos: [21:18]; default: 0;
* psram dqs0 delay 270
*/
uint32_t reg_psram_dqs_0_delay_270:4;
/** reg_psram_dqs_hold : R/W; bitpos: [22]; default: 0;
* psram dqs hold
*/
uint32_t reg_psram_dqs_hold:1;
uint32_t reserved_23:9;
};
uint32_t val;
} iomux_mspi_pin_psram_dqs_0_pin0_reg_t;
/** Group: psram_ck_pin */
/** Type of psram_ck_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_ck_dli : R/W; bitpos: [3:0]; default: 0;
* psram ck dli
*/
uint32_t reg_psram_ck_dli:4;
/** reg_psram_ck_dlc : R/W; bitpos: [7:4]; default: 0;
* psram ck dlc
*/
uint32_t reg_psram_ck_dlc:4;
/** reg_psram_ck_hys : R/W; bitpos: [8]; default: 0;
* psram ck sl
*/
uint32_t reg_psram_ck_hys:1;
/** reg_psram_ck_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_ck_ie:1;
/** reg_psram_ck_wpu : R/W; bitpos: [10]; default: 0;
* psram ck wpu
*/
uint32_t reg_psram_ck_wpu:1;
/** reg_psram_ck_wpd : R/W; bitpos: [11]; default: 0;
* psram ck wpd
*/
uint32_t reg_psram_ck_wpd:1;
/** reg_psram_ck_drv : R/W; bitpos: [14:12]; default: 4;
* psram ck drv
*/
uint32_t reg_psram_ck_drv:3;
/** reg_psram_ck_hold : R/W; bitpos: [15]; default: 0;
* psram ck hold
*/
uint32_t reg_psram_ck_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_ck_pin0_reg_t;
/** Group: psram_cs_pin */
/** Type of psram_cs_pin0 register
* IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
*/
typedef union {
struct {
/** reg_psram_cs_dli : R/W; bitpos: [3:0]; default: 0;
* psram cs dli
*/
uint32_t reg_psram_cs_dli:4;
/** reg_psram_cs_dlc : R/W; bitpos: [7:4]; default: 0;
* psram cs dlc
*/
uint32_t reg_psram_cs_dlc:4;
/** reg_psram_cs_hys : R/W; bitpos: [8]; default: 0;
* psram cs sl
*/
uint32_t reg_psram_cs_hys:1;
/** reg_psram_cs_ie : R/W; bitpos: [9]; default: 0;
* Reserved
*/
uint32_t reg_psram_cs_ie:1;
/** reg_psram_cs_wpu : R/W; bitpos: [10]; default: 0;
* psram cs wpu
*/
uint32_t reg_psram_cs_wpu:1;
/** reg_psram_cs_wpd : R/W; bitpos: [11]; default: 0;
* psram cs wpd
*/
uint32_t reg_psram_cs_wpd:1;
/** reg_psram_cs_drv : R/W; bitpos: [14:12]; default: 4;
* psram cs drv
*/
uint32_t reg_psram_cs_drv:3;
/** reg_psram_cs_hold : R/W; bitpos: [15]; default: 0;
* psram cs hold
*/
uint32_t reg_psram_cs_hold:1;
uint32_t reserved_16:16;
};
uint32_t val;
} iomux_mspi_pin_psram_cs_pin0_reg_t;
typedef struct {
volatile iomux_mspi_pin_clk_en0_reg_t clk_en0;
uint32_t reserved_004[6];
volatile iomux_mspi_pin_psram_d_pin0_reg_t psram_d_pin0;
volatile iomux_mspi_pin_psram_q_pin0_reg_t psram_q_pin0;
volatile iomux_mspi_pin_psram_wp_pin0_reg_t psram_wp_pin0;
volatile iomux_mspi_pin_psram_hold_pin0_reg_t psram_hold_pin0;
volatile iomux_mspi_pin_psram_dq4_pin0_reg_t psram_dq4_pin0;
volatile iomux_mspi_pin_psram_dq5_pin0_reg_t psram_dq5_pin0;
volatile iomux_mspi_pin_psram_dq6_pin0_reg_t psram_dq6_pin0;
volatile iomux_mspi_pin_psram_dq7_pin0_reg_t psram_dq7_pin0;
volatile iomux_mspi_pin_psram_dqs_0_pin0_reg_t psram_dqs_0_pin0;
volatile iomux_mspi_pin_psram_ck_pin0_reg_t psram_ck_pin0;
volatile iomux_mspi_pin_psram_cs_pin0_reg_t psram_cs_pin0;
} iomux_mspi_pin_dev_t;
extern iomux_mspi_pin_dev_t MSPI_IOMUX;
#ifndef __cplusplus
_Static_assert(sizeof(iomux_mspi_pin_dev_t) == 0x48, "Invalid size of iomux_mspi_pin_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif